Pass local scope precision from compiler to vvp/etc.
[iverilog.git] / sync.cc
blob50454a7876f7662c6a67b6808fae0420519ebdec
1 /*
2 * Copyright (c) 2002 Stephen Williams (steve@icarus.com)
4 * This source code is free software; you can redistribute it
5 * and/or modify it in source code form under the terms of the GNU
6 * General Public License as published by the Free Software
7 * Foundation; either version 2 of the License, or (at your option)
8 * any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
19 #ifdef HAVE_CVS_IDENT
20 #ident "$Id: sync.cc,v 1.3 2002/09/24 00:58:35 steve Exp $"
21 #endif
23 # include "config.h"
25 # include "functor.h"
26 # include "netlist.h"
27 # include <assert.h>
30 * Most process statements are not roots of synchronous logic.
32 bool NetProc::is_synchronous()
34 return false;
37 bool NetEvWait::is_synchronous()
39 for (unsigned idx = 0 ; idx < nevents_ ; idx += 1) {
40 NetEvent*ev = events_[idx];
42 if (ev->nprobe() == 0)
43 return false;
45 for (unsigned pdx = 0 ; pdx < ev->nprobe() ; pdx += 1) {
46 NetEvProbe*pr = ev->probe(pdx);
48 /* No level sensitive clocks. */
49 if (pr->edge() == NetEvProbe::ANYEDGE)
50 return false;
55 /* So we know that there is a clock source. Check that the
56 input to the storage is asynchronous. */
57 return true; //statement_->is_asynchronous();
60 bool NetProcTop::is_synchronous()
62 if (type_ == NetProcTop::KINITIAL)
63 return false;
65 return statement_->is_synchronous();
69 * $Log: sync.cc,v $
70 * Revision 1.3 2002/09/24 00:58:35 steve
71 * More detailed check of process edge events.
73 * Revision 1.2 2002/09/16 21:55:06 steve
74 * Reject multiple probes on synchronous logic.
76 * Revision 1.1 2002/09/16 00:30:33 steve
77 * Add to synth2 support for synthesis of
78 * synchronous logic. This includes DFF enables
79 * modeled by if/then/else.