Fix the debugger to finish correctly.
[iverilog.git] / PWire.cc
blob5b0a07fcdecc25234f0a04ad6ae273ea8c9d1481
1 /*
2 * Copyright (c) 1999-2007 Stephen Williams (steve@icarus.com)
4 * This source code is free software; you can redistribute it
5 * and/or modify it in source code form under the terms of the GNU
6 * General Public License as published by the Free Software
7 * Foundation; either version 2 of the License, or (at your option)
8 * any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
19 #ifdef HAVE_CVS_IDENT
20 #ident "$Id: PWire.cc,v 1.14 2007/05/24 04:07:11 steve Exp $"
21 #endif
23 # include "config.h"
24 # include "PWire.h"
25 # include "PExpr.h"
26 # include <assert.h>
28 PWire::PWire(const pform_name_t&n,
29 NetNet::Type t,
30 NetNet::PortType pt,
31 ivl_variable_type_t dt)
32 : hname_(n), type_(t), port_type_(pt), data_type_(dt),
33 signed_(false), isint_(false), port_set_(false), net_set_(false),
34 port_msb_(0), port_lsb_(0), net_msb_(0), net_lsb_(0), error_cnt_(0),
35 lidx_(0), ridx_(0)
37 if (t == NetNet::INTEGER) {
38 type_ = NetNet::REG;
39 signed_ = true;
40 isint_ = true;
44 NetNet::Type PWire::get_wire_type() const
46 return type_;
49 const pform_name_t& PWire::path() const
51 return hname_;
54 bool PWire::set_wire_type(NetNet::Type t)
56 assert(t != NetNet::IMPLICIT);
58 switch (type_) {
59 case NetNet::IMPLICIT:
60 type_ = t;
61 return true;
62 case NetNet::IMPLICIT_REG:
63 if (t == NetNet::REG) { type_ = t; return true; }
64 return false;
65 case NetNet::REG:
66 if (t == NetNet::INTEGER) {
67 isint_ = true;
68 return true;
70 if (t == NetNet::REG) return true;
71 return false;
72 default:
73 if (type_ != t)
74 return false;
75 else
76 return true;
80 NetNet::PortType PWire::get_port_type() const
82 return port_type_;
85 bool PWire::set_port_type(NetNet::PortType pt)
87 assert(pt != NetNet::NOT_A_PORT);
88 assert(pt != NetNet::PIMPLICIT);
90 switch (port_type_) {
91 case NetNet::PIMPLICIT:
92 port_type_ = pt;
93 return true;
95 case NetNet::NOT_A_PORT:
96 return false;
98 default:
99 if (port_type_ != pt)
100 return false;
101 else
102 return true;
106 bool PWire::set_data_type(ivl_variable_type_t dt)
108 if (data_type_ != IVL_VT_NO_TYPE)
109 if (data_type_ != dt)
110 return false;
111 else
112 return true;
114 assert(data_type_ == IVL_VT_NO_TYPE);
115 data_type_ = dt;
116 return true;
119 void PWire::set_signed(bool flag)
121 signed_ = flag;
124 bool PWire::get_signed() const
126 return signed_;
129 bool PWire::get_isint() const
131 return isint_;
135 * Since implicitly defined list of port declarations are no longer
136 * considered fully defined we no longer need this routine to force
137 * them to be fully defined.
139 void PWire::set_net_range()
141 net_msb_ = port_msb_;
142 net_lsb_ = port_lsb_;
143 net_set_ = true;
147 void PWire::set_range(PExpr*m, PExpr*l, PWSRType type)
149 switch (type) {
150 case SR_PORT:
151 if (port_set_) {
152 cerr << get_line() << ": error: Port ``" << hname_
153 << "'' has already been declared a port." << endl;
154 error_cnt_ += 1;
155 } else {
156 port_msb_ = m;
157 port_lsb_ = l;
158 port_set_ = true;
160 return;
162 case SR_NET:
163 if (net_set_) {
164 cerr << get_line() << ": error: Net ``" << hname_
165 << "'' has already been declared." << endl;
166 error_cnt_ += 1;
167 } else {
168 net_msb_ = m;
169 net_lsb_ = l;
170 net_set_ = true;
172 return;
174 case SR_BOTH:
175 if (port_set_ || net_set_) {
176 if (port_set_) {
177 cerr << get_line() << ": error: Port ``" << hname_
178 << "'' has already been declared a port." << endl;
179 error_cnt_ += 1;
181 if (net_set_) {
182 cerr << get_line() << ": error: Net ``" << hname_
183 << "'' has already been declared." << endl;
184 error_cnt_ += 1;
186 } else {
187 port_msb_ = m;
188 port_lsb_ = l;
189 port_set_ = true;
190 net_msb_ = m;
191 net_lsb_ = l;
192 net_set_ = true;
194 return;
198 void PWire::set_memory_idx(PExpr*ldx, PExpr*rdx)
200 if (lidx_ != 0 || ridx_ != 0) {
201 cerr << get_line() << ": error: Array ``" << hname_
202 << "'' has already been declared." << endl;
203 error_cnt_ += 1;
204 } else {
205 lidx_ = ldx;
206 ridx_ = rdx;