Fix the debugger to finish correctly.
[iverilog.git] / target.h
bloba227aa66930e22c7da4dba64b8b18a75433a14f9
1 #ifndef __target_H
2 #define __target_H
3 /*
4 * Copyright (c) 1998-2003 Stephen Williams (steve@icarus.com)
6 * This source code is free software; you can redistribute it
7 * and/or modify it in source code form under the terms of the GNU
8 * General Public License as published by the Free Software
9 * Foundation; either version 2 of the License, or (at your option)
10 * any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
21 #ifdef HAVE_CVS_IDENT
22 #ident "$Id: target.h,v 1.77 2007/01/16 05:44:16 steve Exp $"
23 #endif
25 # include "netlist.h"
28 * This header file describes the types and constants used to describe
29 * the possible target output types of the compiler. The backends
30 * provide one of these in order to tell the previous steps what the
31 * backend is able to do.
35 * The backend driver is hooked into the compiler, and given a name,
36 * by creating an instance of the target structure. The structure has
37 * the name that the compiler will use to locate the driver, and a
38 * pointer to a target_t object that is the actual driver.
40 struct target {
41 const char* name;
42 struct target_t* meth;
46 * The emit process uses a target_t driver to send the completed
47 * design to a file. It is up to the driver object to follow along in
48 * the iteration through the design, generating output as it can.
51 struct target_t {
52 virtual ~target_t();
54 /* Start the design. This sets the main output file stream
55 that the target should use. */
56 virtual bool start_design(const Design*) =0;
58 /* This is called once for each scope in the design, before
59 anything else is called. */
60 virtual void scope(const NetScope*);
62 /* Output an event object. Called for each named event in the scope. */
63 virtual void event(const NetEvent*);
65 /* Output a signal (called for each signal) */
66 virtual void signal(const NetNet*) =0;
67 virtual bool signal_paths(const NetNet*);
69 /* Output a defined task. */
70 virtual void task_def(const NetScope*);
71 virtual bool func_def(const NetScope*);
73 /* LPM style components are handled here. */
74 virtual void lpm_add_sub(const NetAddSub*);
75 virtual bool lpm_array_dq(const NetArrayDq*);
76 virtual void lpm_clshift(const NetCLShift*);
77 virtual void lpm_compare(const NetCompare*);
78 virtual void lpm_divide(const NetDivide*);
79 virtual void lpm_modulo(const NetModulo*);
80 virtual void lpm_ff(const NetFF*);
81 virtual void lpm_mult(const NetMult*);
82 virtual void lpm_mux(const NetMux*);
84 virtual bool concat(const NetConcat*);
85 virtual bool part_select(const NetPartSelect*);
86 virtual bool replicate(const NetReplicate*);
88 /* Output a gate (called for each gate) */
89 virtual void logic(const NetLogic*);
90 virtual bool ureduce(const NetUReduce*); /* unary reduction operator */
91 virtual bool bufz(const NetBUFZ*);
92 virtual void udp(const NetUDP*);
93 virtual void net_case_cmp(const NetCaseCmp*);
94 virtual bool net_const(const NetConst*);
95 virtual bool net_sysfunction(const NetSysFunc*);
96 virtual bool net_function(const NetUserFunc*);
97 virtual bool net_literal(const NetLiteral*);
98 virtual void net_probe(const NetEvProbe*);
99 virtual bool sign_extend(const NetSignExtend*);
101 /* Output a process (called for each process). It is up to the
102 target to recurse if desired. */
103 virtual bool process(const NetProcTop*);
105 /* Various kinds of process nodes are dispatched through these. */
106 virtual void proc_assign(const NetAssign*);
107 virtual void proc_assign_nb(const NetAssignNB*);
108 virtual bool proc_block(const NetBlock*);
109 virtual void proc_case(const NetCase*);
110 virtual bool proc_cassign(const NetCAssign*);
111 virtual bool proc_condit(const NetCondit*);
112 virtual bool proc_deassign(const NetDeassign*);
113 virtual bool proc_delay(const NetPDelay*);
114 virtual bool proc_disable(const NetDisable*);
115 virtual bool proc_force(const NetForce*);
116 virtual void proc_forever(const NetForever*);
117 virtual bool proc_release(const NetRelease*);
118 virtual void proc_repeat(const NetRepeat*);
119 virtual bool proc_trigger(const NetEvTrig*);
120 virtual void proc_stask(const NetSTask*);
121 virtual void proc_utask(const NetUTask*);
122 virtual bool proc_wait(const NetEvWait*);
123 virtual void proc_while(const NetWhile*);
125 /* Done with the design. The target returns !0 if there is
126 some error in the code generation. */
127 virtual int end_design(const Design*);
130 /* This class is used by the NetExpr class to help with the scanning
131 of expressions. */
132 struct expr_scan_t {
133 virtual ~expr_scan_t();
134 virtual void expr_const(const NetEConst*);
135 virtual void expr_param(const NetEConstParam*);
136 virtual void expr_rparam(const NetECRealParam*);
137 virtual void expr_creal(const NetECReal*);
138 virtual void expr_concat(const NetEConcat*);
139 virtual void expr_event(const NetEEvent*);
140 virtual void expr_scope(const NetEScope*);
141 virtual void expr_select(const NetESelect*);
142 virtual void expr_sfunc(const NetESFunc*);
143 virtual void expr_signal(const NetESignal*);
144 virtual void expr_ternary(const NetETernary*);
145 virtual void expr_ufunc(const NetEUFunc*);
146 virtual void expr_unary(const NetEUnary*);
147 virtual void expr_binary(const NetEBinary*);
151 /* The emit functions take a design and emit it to the output stream
152 using the specified target. If the target is given by name, it is
153 located in the target_table and used. */
154 extern int emit(const Design*des, const char*type);
156 /* This function takes a fully qualified verilog name (which may have,
157 for example, dots in it) and produces a mangled version that can be
158 used by most any language. */
159 extern string mangle(const string&str);
161 /* This function takes a string and produces an escaped version that can be
162 used inside a string constant for a C++ compiler. */
163 extern string stresc(const string&str);
165 /* This is the table of supported output targets. It is a null
166 terminated array of pointers to targets. */
167 extern const struct target *target_table[];
170 * $Log: target.h,v $
171 * Revision 1.77 2007/01/16 05:44:16 steve
172 * Major rework of array handling. Memories are replaced with the
173 * more general concept of arrays. The NetMemory and NetEMemory
174 * classes are removed from the ivl core program, and the IVL_LPM_RAM
175 * lpm type is removed from the ivl_target API.
177 * Revision 1.76 2006/11/10 05:44:45 steve
178 * Process delay paths in second path over signals.
180 * Revision 1.75 2006/06/18 04:15:50 steve
181 * Add support for system functions in continuous assignments.
183 * Revision 1.74 2005/07/11 16:56:51 steve
184 * Remove NetVariable and ivl_variable_t structures.
186 * Revision 1.73 2005/07/07 16:22:49 steve
187 * Generalize signals to carry types.
189 * Revision 1.72 2005/05/24 01:44:28 steve
190 * Do sign extension of structuran nets.
192 * Revision 1.71 2005/02/08 00:12:36 steve
193 * Add the NetRepeat node, and code generator support.
195 * Revision 1.70 2005/02/03 04:56:21 steve
196 * laborate reduction gates into LPM_RED_ nodes.
198 * Revision 1.69 2005/01/24 05:28:31 steve
199 * Remove the NetEBitSel and combine all bit/part select
200 * behavior into the NetESelect node and IVL_EX_SELECT
201 * ivl_target expression type.
203 * Revision 1.68 2005/01/22 01:06:55 steve
204 * Change case compare from logic to an LPM node.
206 * Revision 1.67 2004/12/29 23:55:43 steve
207 * Unify elaboration of l-values for all proceedural assignments,
208 * including assing, cassign and force.
210 * Generate NetConcat devices for gate outputs that feed into a
211 * vector results. Use this to hande gate arrays. Also let gate
212 * arrays handle vectors of gates when the outputs allow for it.
214 * Revision 1.66 2004/12/11 02:31:28 steve
215 * Rework of internals to carry vectors through nexus instead
216 * of single bits. Make the ivl, tgt-vvp and vvp initial changes
217 * down this path.
219 * Revision 1.65 2004/05/31 23:34:39 steve
220 * Rewire/generalize parsing an elaboration of
221 * function return values to allow for better
222 * speed and more type support.
224 * Revision 1.64 2003/05/30 02:55:32 steve
225 * Support parameters in real expressions and
226 * as real expressions, and fix multiply and
227 * divide with real results.
229 * Revision 1.63 2003/04/22 04:48:30 steve
230 * Support event names as expressions elements.
232 * Revision 1.62 2003/03/10 23:40:54 steve
233 * Keep parameter constants for the ivl_target API.
235 * Revision 1.61 2003/01/26 21:15:59 steve
236 * Rework expression parsing and elaboration to
237 * accommodate real/realtime values and expressions.
239 * Revision 1.60 2002/08/12 01:35:01 steve
240 * conditional ident string using autoconfig.
242 * Revision 1.59 2002/06/05 03:44:25 steve
243 * Add support for memory words in l-value of
244 * non-blocking assignments, and remove the special
245 * NetAssignMem_ and NetAssignMemNB classes.
247 * Revision 1.58 2002/06/04 05:38:44 steve
248 * Add support for memory words in l-value of
249 * blocking assignments, and remove the special
250 * NetAssignMem class.
252 * Revision 1.57 2002/03/09 02:10:22 steve
253 * Add the NetUserFunc netlist node.
255 * Revision 1.56 2002/01/28 00:52:41 steve
256 * Add support for bit select of parameters.
257 * This leads to a NetESelect node and the
258 * vvp code generator to support that.
260 * Revision 1.55 2002/01/19 19:02:08 steve
261 * Pass back target errors processing conditionals.
263 * Revision 1.54 2001/08/25 23:50:03 steve
264 * Change the NetAssign_ class to refer to the signal
265 * instead of link into the netlist. This is faster
266 * and uses less space. Make the NetAssignNB carry
267 * the delays instead of the NetAssign_ lval objects.
269 * Change the vvp code generator to support multiple
270 * l-values, i.e. concatenations of part selects.
272 * Revision 1.53 2001/07/27 04:51:44 steve
273 * Handle part select expressions as variants of
274 * NetESignal/IVL_EX_SIGNAL objects, instead of
275 * creating new and useless temporary signals.
277 * Revision 1.52 2001/04/22 23:09:46 steve
278 * More UDP consolidation from Stephan Boettcher.
280 #endif