vvp/arith.cc

   1 /*
   2  * Copyright (c) 2001-2005 Stephen Williams (steve@icarus.com)
   3  *
   4  *    This source code is free software; you can redistribute it
   5  *    and/or modify it in source code form under the terms of the GNU
   6  *    General Public License as published by the Free Software
   7  *    Foundation; either version 2 of the License, or (at your option)
   8  *    any later version.
   9  *
  10  *    This program is distributed in the hope that it will be useful,
  11  *    but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  *    GNU General Public License for more details.
  14  *
  15  *    You should have received a copy of the GNU General Public License
  16  *    along with this program; if not, write to the Free Software
  17  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  18  */
  19 #ifdef HAVE_CVS_IDENT
  20 #ident "$Id: arith.cc,v 1.50 2007/01/20 02:09:54 steve Exp $"
  21 #endif
  22
  23 # include  "arith.h"
  24 # include  "schedule.h"
  25 # include  <limits.h>
  26 # include  <iostream>
  27 # include  <assert.h>
  28 # include  <stdlib.h>
  29 #ifdef HAVE_MALLOC_H
  30 # include  <malloc.h>
  31 #endif
  32
  33 vvp_arith_::vvp_arith_(unsigned wid)
  34 : wid_(wid), x_val_(wid)
  35 {
  36       for (unsigned idx = 0 ;  idx < wid ;  idx += 1)
  37             x_val_.set_bit(idx, BIT4_X);
  38
  39       op_a_ = x_val_;
  40       op_b_ = x_val_;
  41 }
  42
  43 void vvp_arith_::dispatch_operand_(vvp_net_ptr_t ptr, vvp_vector4_t bit)
  44 {
  45       unsigned port = ptr.port();
  46       switch (port) {
  47           case 0:
  48             op_a_ = bit;
  49             break;
  50           case 1:
  51             op_b_ = bit;
  52             break;
  53           default:
  54             fprintf(stderr, "Unsupported port type %d.\n", port);
  55             assert(0);
  56       }
  57 }
  58
  59
  60 // Division
  61
  62 vvp_arith_div::vvp_arith_div(unsigned wid, bool signed_flag)
  63 : vvp_arith_(wid), signed_flag_(signed_flag)
  64 {
  65 }
  66
  67 vvp_arith_div::~vvp_arith_div()
  68 {
  69 }
  70
  71 void vvp_arith_div::wide4_(vvp_net_ptr_t ptr)
  72 {
  73       vvp_vector2_t a2 (op_a_);
  74       if (a2.is_NaN()) {
  75             vvp_send_vec4(ptr.ptr()->out, x_val_);
  76             return;
  77       }
  78
  79       vvp_vector2_t b2 (op_b_);
  80       if (b2.is_NaN()) {
  81             vvp_send_vec4(ptr.ptr()->out, x_val_);
  82             return;
  83       }
  84
  85       vvp_vector2_t res2 = a2 / b2;
  86       vvp_send_vec4(ptr.ptr()->out, vector2_to_vector4(res2, wid_));
  87 }
  88
  89 void vvp_arith_div::recv_vec4(vvp_net_ptr_t ptr, const vvp_vector4_t&bit)
  90 {
  91       dispatch_operand_(ptr, bit);
  92
  93       if (wid_ > 8 * sizeof(unsigned long)) {
  94             wide4_(ptr);
  95             return ;
  96       }
  97
  98       unsigned long a;
  99       if (! vector4_to_value(op_a_, a)) {
 100             vvp_send_vec4(ptr.ptr()->out, x_val_);
 101             return;
 102       }
 103
 104       unsigned long b;
 105       if (! vector4_to_value(op_b_, b)) {
 106             vvp_send_vec4(ptr.ptr()->out, x_val_);
 107             return;
 108       }
 109
 110       bool negate = false;
 111         /* If we are doing signed divide, then take the sign out of
 112            the operands for now, and remember to put the sign back
 113            later. */
 114       if (signed_flag_) {
 115             if (op_a_.value(op_a_.size()-1)) {
 116                   a = (-a) & ~ (-1UL << op_a_.size());
 117                   negate = !negate;
 118             }
 119
 120             if (op_b_.value(op_b_.size()-1)) {
 121                   b = (-b) & ~ (-1UL << op_b_.size());
 122                   negate = ! negate;
 123             }
 124       }
 125
 126       unsigned long val = a / b;
 127       if (negate)
 128             val = -val;
 129
 130       assert(wid_ <= 8*sizeof(val));
 131
 132       vvp_vector4_t vval (wid_);
 133       for (unsigned idx = 0 ;  idx < wid_ ;  idx += 1) {
 134             if (val & 1)
 135                   vval.set_bit(idx, BIT4_1);
 136             else
 137                   vval.set_bit(idx, BIT4_0);
 138
 139             val >>= 1;
 140       }
 141
 142       vvp_send_vec4(ptr.ptr()->out, vval);
 143 }
 144
 145
 146 vvp_arith_mod::vvp_arith_mod(unsigned wid, bool sf)
 147 : vvp_arith_(wid), signed_flag_(sf)
 148 {
 149 }
 150
 151 vvp_arith_mod::~vvp_arith_mod()
 152 {
 153 }
 154
 155 void vvp_arith_mod::wide_(vvp_net_ptr_t ptr)
 156 {
 157       vvp_vector2_t a2 (op_a_);
 158       if (a2.is_NaN()) {
 159             vvp_send_vec4(ptr.ptr()->out, x_val_);
 160             return;
 161       }
 162
 163       vvp_vector2_t b2 (op_b_);
 164       if (b2.is_NaN()) {
 165             vvp_send_vec4(ptr.ptr()->out, x_val_);
 166             return;
 167       }
 168
 169       vvp_vector2_t res = a2 % b2;
 170       vvp_send_vec4(ptr.ptr()->out, vector2_to_vector4(res, res.size()));
 171 }
 172
 173 void vvp_arith_mod::recv_vec4(vvp_net_ptr_t ptr, const vvp_vector4_t&bit)
 174 {
 175       dispatch_operand_(ptr, bit);
 176
 177       if (wid_ > 8 * sizeof(unsigned long)) {
 178             wide_(ptr);
 179             return ;
 180       }
 181
 182       unsigned long a;
 183       if (! vector4_to_value(op_a_, a)) {
 184             vvp_send_vec4(ptr.ptr()->out, x_val_);
 185             return;
 186       }
 187
 188       unsigned long b;
 189       if (! vector4_to_value(op_b_, b)) {
 190             vvp_send_vec4(ptr.ptr()->out, x_val_);
 191             return;
 192       }
 193
 194       bool negate = false;
 195         /* If we are doing signed divide, then take the sign out of
 196            the operands for now, and remember to put the sign back
 197            later. */
 198       if (signed_flag_) {
 199             if (op_a_.value(op_a_.size()-1)) {
 200                   a = (-a) & ~ (-1UL << op_a_.size());
 201                   negate = !negate;
 202             }
 203
 204             if (op_b_.value(op_b_.size()-1)) {
 205                   b = (-b) & ~ (-1UL << op_b_.size());
 206                   negate = ! negate;
 207             }
 208       }
 209
 210       if (b == 0) {
 211             vvp_vector4_t xval (wid_);
 212             for (unsigned idx = 0 ;  idx < wid_ ;  idx += 1)
 213                   xval.set_bit(idx, BIT4_X);
 214
 215             vvp_send_vec4(ptr.ptr()->out, xval);
 216             return;
 217       }
 218
 219       unsigned long val = a % b;
 220       if (negate)
 221             val = -val;
 222
 223       assert(wid_ <= 8*sizeof(val));
 224
 225       vvp_vector4_t vval (wid_);
 226       for (unsigned idx = 0 ;  idx < wid_ ;  idx += 1) {
 227             if (val & 1)
 228                   vval.set_bit(idx, BIT4_1);
 229             else
 230                   vval.set_bit(idx, BIT4_0);
 231
 232             val >>= 1;
 233       }
 234
 235       vvp_send_vec4(ptr.ptr()->out, vval);
 236 }
 237
 238
 239 // Multiplication
 240
 241 vvp_arith_mult::vvp_arith_mult(unsigned wid)
 242 : vvp_arith_(wid)
 243 {
 244 }
 245
 246 vvp_arith_mult::~vvp_arith_mult()
 247 {
 248 }
 249
 250 void vvp_arith_mult::wide_(vvp_net_ptr_t ptr)
 251 {
 252       vvp_vector2_t a2 (op_a_);
 253       vvp_vector2_t b2 (op_b_);
 254
 255       if (a2.is_NaN() || b2.is_NaN()) {
 256             vvp_send_vec4(ptr.ptr()->out, x_val_);
 257             return;
 258       }
 259
 260       vvp_vector2_t result = a2 * b2;
 261
 262       vvp_vector4_t res4 = vector2_to_vector4(result, wid_);
 263       vvp_send_vec4(ptr.ptr()->out, res4);
 264 }
 265
 266 void vvp_arith_mult::recv_vec4(vvp_net_ptr_t ptr, const vvp_vector4_t&bit)
 267 {
 268       dispatch_operand_(ptr, bit);
 269
 270       if (wid_ > 8 * sizeof(unsigned long)) {
 271             wide_(ptr);
 272             return ;
 273       }
 274
 275       unsigned long a;
 276       if (! vector4_to_value(op_a_, a)) {
 277             vvp_send_vec4(ptr.ptr()->out, x_val_);
 278             return;
 279       }
 280
 281       unsigned long b;
 282       if (! vector4_to_value(op_b_, b)) {
 283             vvp_send_vec4(ptr.ptr()->out, x_val_);
 284             return;
 285       }
 286
 287       unsigned long val = a * b;
 288       assert(wid_ <= 8*sizeof(val));
 289
 290       vvp_vector4_t vval (wid_);
 291       for (unsigned idx = 0 ;  idx < wid_ ;  idx += 1) {
 292             if (val & 1)
 293                   vval.set_bit(idx, BIT4_1);
 294             else
 295                   vval.set_bit(idx, BIT4_0);
 296
 297             val >>= 1;
 298       }
 299
 300       vvp_send_vec4(ptr.ptr()->out, vval);
 301 }
 302
 303
 304 #if 0
 305 void vvp_arith_mult::set(vvp_ipoint_t i, bool push, unsigned val, unsigned)
 306 {
 307       put(i, val);
 308       vvp_ipoint_t base = ipoint_make(i,0);
 309
 310       if(wid_ > 8*sizeof(unsigned long)) {
 311             wide(base, push);
 312             return;
 313       }
 314
 315       unsigned long a = 0, b = 0;
 316
 317       for (unsigned idx = 0 ;  idx < wid_ ;  idx += 1) {
 318             vvp_ipoint_t ptr = ipoint_index(base,idx);
 319             functor_t obj = functor_index(ptr);
 320
 321             unsigned val = obj->ival;
 322             if (val & 0xaa) {
 323                   output_x_(base, push);
 324                   return;
 325             }
 326
 327             if (val & 0x01)
 328                   a += 1UL << idx;
 329             if (val & 0x04)
 330                   b += 1UL << idx;
 331       }
 332
 333       output_val_(base, push, a*b);
 334 }
 335 #endif
 336
 337 #if 0
 338 void vvp_arith_mult::wide(vvp_ipoint_t base, bool push)
 339 {
 340       unsigned char *a, *b, *sum;
 341       a = new unsigned char[wid_];
 342       b = new unsigned char[wid_];
 343       sum = new unsigned char[wid_];
 344
 345       unsigned mxa = 0;
 346       unsigned mxb = 0;
 347
 348       for (unsigned idx = 0 ;  idx < wid_ ;  idx += 1) {
 349             vvp_ipoint_t ptr = ipoint_index(base, idx);
 350             functor_t obj = functor_index(ptr);
 351
 352             unsigned ival = obj->ival;
 353             if (ival & 0xaa) {
 354                   output_x_(base, push);
 355                   delete[]sum;
 356                   delete[]b;
 357                   delete[]a;
 358                   return;
 359             }
 360
 361             if((a[idx] = ((ival & 0x01) != 0))) mxa=idx+1;
 362             if((b[idx] = ((ival & 0x04) != 0))) mxb=idx;
 363             sum[idx] = 0;
 364       }
 365
 366         /* do the a*b multiply using the long method we learned in
 367            grade school. We know at this point that there are no X or
 368            Z values in the a or b vectors. */
 369
 370       for(unsigned i=0 ;  i<=mxb ;  i += 1) {
 371             if(b[i]) {
 372                   unsigned char carry=0;
 373                   unsigned char temp;
 374
 375                   for(unsigned j=0 ;  j<=mxa ;  j += 1) {
 376
 377                         if((i+j) >= wid_)
 378                               break;
 379
 380                         temp=sum[i+j] + a[j] + carry;
 381                         sum[i+j]=(temp&1);
 382                         carry=(temp>>1);
 383                   }
 384             }
 385       }
 386
 387       for (unsigned idx = 0 ;  idx < wid_ ;  idx += 1) {
 388             vvp_ipoint_t ptr = ipoint_index(base,idx);
 389             functor_t obj = functor_index(ptr);
 390
 391             unsigned val = sum[idx];
 392
 393             obj->put_oval(val, push);
 394       }
 395
 396       delete[]sum;
 397       delete[]b;
 398       delete[]a;
 399 }
 400 #endif
 401
 402 // Addition
 403
 404 vvp_arith_sum::vvp_arith_sum(unsigned wid)
 405 : vvp_arith_(wid)
 406 {
 407 }
 408
 409 vvp_arith_sum::~vvp_arith_sum()
 410 {
 411 }
 412
 413 void vvp_arith_sum::recv_vec4(vvp_net_ptr_t ptr, const vvp_vector4_t&bit)
 414 {
 415       dispatch_operand_(ptr, bit);
 416
 417       vvp_net_t*net = ptr.ptr();
 418
 419       vvp_vector4_t value (wid_);
 420
 421         /* Pad input vectors with this value to widen to the desired
 422            output width. */
 423       const vvp_bit4_t pad = BIT4_0;
 424
 425       vvp_bit4_t carry = BIT4_0;
 426       for (unsigned idx = 0 ;  idx < wid_ ;  idx += 1) {
 427             vvp_bit4_t a = (idx >= op_a_.size())? pad : op_a_.value(idx);
 428             vvp_bit4_t b = (idx >= op_b_.size())? pad : op_b_.value(idx);
 429             vvp_bit4_t cur = add_with_carry(a, b, carry);
 430
 431             if (cur == BIT4_X) {
 432                   vvp_send_vec4(net->out, x_val_);
 433                   return;
 434             }
 435
 436             value.set_bit(idx, cur);
 437       }
 438
 439       vvp_send_vec4(net->out, value);
 440 }
 441
 442 vvp_arith_sub::vvp_arith_sub(unsigned wid)
 443 : vvp_arith_(wid)
 444 {
 445 }
 446
 447 vvp_arith_sub::~vvp_arith_sub()
 448 {
 449 }
 450
 451 /*
 452  * Subtraction works by adding the 2s complement of the B input from
 453  * the A input. The 2s complement is the 1s complement plus one, so we
 454  * further reduce the operation to adding in the inverted value and
 455  * adding a correction.
 456  */
 457 void vvp_arith_sub::recv_vec4(vvp_net_ptr_t ptr, const vvp_vector4_t&bit)
 458 {
 459       dispatch_operand_(ptr, bit);
 460
 461       vvp_net_t*net = ptr.ptr();
 462
 463       vvp_vector4_t value (wid_);
 464
 465         /* Pad input vectors with this value to widen to the desired
 466            output width. */
 467       const vvp_bit4_t pad = BIT4_1;
 468
 469       vvp_bit4_t carry = BIT4_1;
 470       for (unsigned idx = 0 ;  idx < wid_ ;  idx += 1) {
 471             vvp_bit4_t a = (idx >= op_a_.size())? pad : op_a_.value(idx);
 472             vvp_bit4_t b = (idx >= op_b_.size())? pad : ~op_b_.value(idx);
 473             vvp_bit4_t cur = add_with_carry(a, b, carry);
 474
 475             if (cur == BIT4_X) {
 476                   vvp_send_vec4(net->out, x_val_);
 477                   return;
 478             }
 479
 480             value.set_bit(idx, cur);
 481       }
 482
 483       vvp_send_vec4(net->out, value);
 484 }
 485
 486 vvp_cmp_eeq::vvp_cmp_eeq(unsigned wid)
 487 : vvp_arith_(wid)
 488 {
 489 }
 490
 491 void vvp_cmp_eeq::recv_vec4(vvp_net_ptr_t ptr, const vvp_vector4_t&bit)
 492 {
 493       dispatch_operand_(ptr, bit);
 494
 495       vvp_vector4_t eeq (1);
 496       eeq.set_bit(0, BIT4_1);
 497
 498       assert(op_a_.size() == op_b_.size());
 499       for (unsigned idx = 0 ;  idx < op_a_.size() ;  idx += 1)
 500             if (op_a_.value(idx) != op_b_.value(idx)) {
 501                   eeq.set_bit(0, BIT4_0);
 502                   break;
 503             }
 504
 505
 506       vvp_net_t*net = ptr.ptr();
 507       vvp_send_vec4(net->out, eeq);
 508 }
 509
 510 vvp_cmp_nee::vvp_cmp_nee(unsigned wid)
 511 : vvp_arith_(wid)
 512 {
 513 }
 514
 515 void vvp_cmp_nee::recv_vec4(vvp_net_ptr_t ptr, const vvp_vector4_t&bit)
 516 {
 517       dispatch_operand_(ptr, bit);
 518
 519       vvp_vector4_t eeq (1);
 520       eeq.set_bit(0, BIT4_0);
 521
 522       assert(op_a_.size() == op_b_.size());
 523       for (unsigned idx = 0 ;  idx < op_a_.size() ;  idx += 1)
 524             if (op_a_.value(idx) != op_b_.value(idx)) {
 525                   eeq.set_bit(0, BIT4_1);
 526                   break;
 527             }
 528
 529
 530       vvp_net_t*net = ptr.ptr();
 531       vvp_send_vec4(net->out, eeq);
 532 }
 533
 534 vvp_cmp_eq::vvp_cmp_eq(unsigned wid)
 535 : vvp_arith_(wid)
 536 {
 537 }
 538
 539 /*
 540  * Compare Vector a and Vector b. If in any bit position the a and b
 541  * bits are known and different, then the result is 0. Otherwise, if
 542  * there are X/Z bits anywhere in A or B, the result is X. Finally,
 543  * the result is 1.
 544  */
 545 void vvp_cmp_eq::recv_vec4(vvp_net_ptr_t ptr, const vvp_vector4_t&bit)
 546 {
 547       dispatch_operand_(ptr, bit);
 548
 549       if (op_a_.size() != op_b_.size()) {
 550             cerr << "COMPARISON size mismatch. "
 551                  << "a=" << op_a_ << ", b=" << op_b_ << endl;
 552             assert(0);
 553       }
 554
 555       vvp_vector4_t res (1);
 556       res.set_bit(0, BIT4_1);
 557
 558       for (unsigned idx = 0 ;  idx < op_a_.size() ;  idx += 1) {
 559             vvp_bit4_t a = op_a_.value(idx);
 560             vvp_bit4_t b = op_b_.value(idx);
 561
 562             if (a == BIT4_X)
 563                   res.set_bit(0, BIT4_X);
 564             else if (a == BIT4_Z)
 565                   res.set_bit(0, BIT4_X);
 566             else if (b == BIT4_X)
 567                   res.set_bit(0, BIT4_X);
 568             else if (b == BIT4_Z)
 569                   res.set_bit(0, BIT4_X);
 570             else if (a != b) {
 571                   res.set_bit(0, BIT4_0);
 572                   break;
 573             }
 574       }
 575
 576       vvp_net_t*net = ptr.ptr();
 577       vvp_send_vec4(net->out, res);
 578 }
 579
 580
 581 vvp_cmp_ne::vvp_cmp_ne(unsigned wid)
 582 : vvp_arith_(wid)
 583 {
 584 }
 585
 586 /*
 587  * Compare Vector a and Vector b. If in any bit position the a and b
 588  * bits are known and different, then the result is 1. Otherwise, if
 589  * there are X/Z bits anywhere in A or B, the result is X. Finally,
 590  * the result is 0.
 591  */
 592 void vvp_cmp_ne::recv_vec4(vvp_net_ptr_t ptr, const vvp_vector4_t&bit)
 593 {
 594       dispatch_operand_(ptr, bit);
 595
 596       assert(op_a_.size() == op_b_.size());
 597
 598       vvp_vector4_t res (1);
 599       res.set_bit(0, BIT4_0);
 600
 601       for (unsigned idx = 0 ;  idx < op_a_.size() ;  idx += 1) {
 602             vvp_bit4_t a = op_a_.value(idx);
 603             vvp_bit4_t b = op_b_.value(idx);
 604
 605             if (a == BIT4_X)
 606                   res.set_bit(0, BIT4_X);
 607             else if (a == BIT4_Z)
 608                   res.set_bit(0, BIT4_X);
 609             else if (b == BIT4_X)
 610                   res.set_bit(0, BIT4_X);
 611             else if (b == BIT4_Z)
 612                   res.set_bit(0, BIT4_X);
 613             else if (a != b) {
 614                   res.set_bit(0, BIT4_1);
 615                   break;
 616             }
 617       }
 618
 619       vvp_net_t*net = ptr.ptr();
 620       vvp_send_vec4(net->out, res);
 621 }
 622
 623
 624 vvp_cmp_gtge_base_::vvp_cmp_gtge_base_(unsigned wid, bool flag)
 625 : vvp_arith_(wid), signed_flag_(flag)
 626 {
 627 }
 628
 629
 630 void vvp_cmp_gtge_base_::recv_vec4_base_(vvp_net_ptr_t ptr,
 631                                          vvp_vector4_t bit,
 632                                          vvp_bit4_t out_if_equal)
 633 {
 634       dispatch_operand_(ptr, bit);
 635
 636       vvp_bit4_t out = signed_flag_
 637             ? compare_gtge_signed(op_a_, op_b_, out_if_equal)
 638             : compare_gtge(op_a_, op_b_, out_if_equal);
 639       vvp_vector4_t val (1);
 640       val.set_bit(0, out);
 641       vvp_send_vec4(ptr.ptr()->out, val);
 642
 643       return;
 644 }
 645
 646
 647 vvp_cmp_ge::vvp_cmp_ge(unsigned wid, bool flag)
 648 : vvp_cmp_gtge_base_(wid, flag)
 649 {
 650 }
 651
 652 void vvp_cmp_ge::recv_vec4(vvp_net_ptr_t ptr, const vvp_vector4_t&bit)
 653 {
 654       recv_vec4_base_(ptr, bit, BIT4_1);
 655 }
 656
 657 vvp_cmp_gt::vvp_cmp_gt(unsigned wid, bool flag)
 658 : vvp_cmp_gtge_base_(wid, flag)
 659 {
 660 }
 661
 662 void vvp_cmp_gt::recv_vec4(vvp_net_ptr_t ptr, const vvp_vector4_t&bit)
 663 {
 664       recv_vec4_base_(ptr, bit, BIT4_0);
 665 }
 666
 667
 668 vvp_shiftl::vvp_shiftl(unsigned wid)
 669 : vvp_arith_(wid)
 670 {
 671 }
 672
 673 vvp_shiftl::~vvp_shiftl()
 674 {
 675 }
 676
 677 void vvp_shiftl::recv_vec4(vvp_net_ptr_t ptr, const vvp_vector4_t&bit)
 678 {
 679       dispatch_operand_(ptr, bit);
 680
 681       vvp_vector4_t out (op_a_.size());
 682
 683       unsigned long shift;
 684       if (! vector4_to_value(op_b_, shift)) {
 685             vvp_send_vec4(ptr.ptr()->out, x_val_);
 686             return;
 687       }
 688
 689       if (shift > out.size())
 690             shift = out.size();
 691
 692       for (unsigned idx = 0 ;  idx < shift ;  idx += 1)
 693             out.set_bit(idx, BIT4_0);
 694
 695       for (unsigned idx = shift ;  idx < out.size() ;  idx += 1)
 696             out.set_bit(idx, op_a_.value(idx-shift));
 697
 698       vvp_send_vec4(ptr.ptr()->out, out);
 699 }
 700
 701 vvp_shiftr::vvp_shiftr(unsigned wid, bool signed_flag)
 702 : vvp_arith_(wid), signed_flag_(signed_flag)
 703 {
 704 }
 705
 706 vvp_shiftr::~vvp_shiftr()
 707 {
 708 }
 709
 710 void vvp_shiftr::recv_vec4(vvp_net_ptr_t ptr, const vvp_vector4_t&bit)
 711 {
 712       dispatch_operand_(ptr, bit);
 713
 714       vvp_vector4_t out (op_a_.size());
 715
 716       unsigned long shift;
 717       if (! vector4_to_value(op_b_, shift)) {
 718             vvp_send_vec4(ptr.ptr()->out, x_val_);
 719             return;
 720       }
 721
 722       if (shift > out.size())
 723             shift = out.size();
 724
 725       for (unsigned idx = shift ;  idx < out.size() ;  idx += 1)
 726             out.set_bit(idx-shift, op_a_.value(idx));
 727
 728       vvp_bit4_t pad = BIT4_0;
 729       if (signed_flag_ && op_a_.size() > 0)
 730             pad = op_a_.value(op_a_.size()-1);
 731
 732       for (unsigned idx = 0 ;  idx < shift ;  idx += 1)
 733             out.set_bit(idx+out.size()-shift, pad);
 734
 735       vvp_send_vec4(ptr.ptr()->out, out);
 736 }
 737
 738
 739 vvp_arith_real_::vvp_arith_real_()
 740 {
 741 }
 742
 743 void vvp_arith_real_::dispatch_operand_(vvp_net_ptr_t ptr, double bit)
 744 {
 745       switch (ptr.port()) {
 746           case 0:
 747             op_a_ = bit;
 748             break;
 749           case 1:
 750             op_b_ = bit;
 751             break;
 752           default:
 753             fprintf(stderr, "Unsupported port type %d.\n", ptr.port());
 754             assert(0);
 755       }
 756 }
 757
 758
 759 vvp_arith_div_real::vvp_arith_div_real()
 760 {
 761 }
 762
 763 vvp_arith_div_real::~vvp_arith_div_real()
 764 {
 765 }
 766
 767 void vvp_arith_div_real::recv_real(vvp_net_ptr_t ptr, double bit)
 768 {
 769       dispatch_operand_(ptr, bit);
 770
 771       double val = op_a_ / op_b_;
 772       vvp_send_real(ptr.ptr()->out, val);
 773 }
 774
 775 vvp_arith_sub_real::vvp_arith_sub_real()
 776 {
 777 }
 778
 779 vvp_arith_sub_real::~vvp_arith_sub_real()
 780 {
 781 }
 782
 783 void vvp_arith_sub_real::recv_real(vvp_net_ptr_t ptr, double bit)
 784 {
 785       dispatch_operand_(ptr, bit);
 786
 787       double val = op_a_ - op_b_;
 788       vvp_send_real(ptr.ptr()->out, val);
 789 }
 790