tgt-fpga/d-generic.c

   1 /*
   2  * Copyright (c) 2001 Stephen Williams (steve@icarus.com)
   3  *
   4  *    This source code is free software; you can redistribute it
   5  *    and/or modify it in source code form under the terms of the GNU
   6  *    General Public License as published by the Free Software
   7  *    Foundation; either version 2 of the License, or (at your option)
   8  *    any later version.
   9  *
  10  *    This program is distributed in the hope that it will be useful,
  11  *    but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  *    GNU General Public License for more details.
  14  *
  15  *    You should have received a copy of the GNU General Public License
  16  *    along with this program; if not, write to the Free Software
  17  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  18  */
  19 #ifdef HAVE_CVS_IDENT
  20 #ident "$Id: d-generic.c,v 1.14 2003/11/12 03:20:14 steve Exp $"
  21 #endif
  22
  23 # include  "device.h"
  24 # include  "fpga_priv.h"
  25 # include  <assert.h>
  26
  27 /*
  28  * This is the device emitter for the most generic FPGA. It doesn't
  29  * know anything special about device types, so can't handle complex
  30  * logic.
  31  */
  32
  33 static void xnf_draw_pin(ivl_nexus_t nex, const char*nam, char dir)
  34 {
  35       const char*use_name = nam;
  36       const char*nex_name = xnf_mangle_nexus_name(nex);
  37       int invert = 0;
  38
  39       if (use_name[0] == '~') {
  40             invert = 1;
  41             use_name += 1;
  42       }
  43
  44       fprintf(xnf, "    PIN, %s, %c, %s", use_name, dir, nex_name);
  45
  46       if (invert)
  47             fprintf(xnf, ",,INV");
  48
  49       fprintf(xnf, "\n");
  50 }
  51
  52 static void show_root_ports_xnf(ivl_scope_t root)
  53 {
  54       unsigned cnt = ivl_scope_sigs(root);
  55       unsigned idx;
  56
  57       for (idx = 0 ;  idx < cnt ;  idx += 1) {
  58             ivl_signal_t sig = ivl_scope_sig(root, idx);
  59             const char*use_name;
  60
  61             if (ivl_signal_port(sig) == IVL_SIP_NONE)
  62                   continue;
  63
  64             use_name = ivl_signal_basename(sig);
  65             if (ivl_signal_pins(sig) == 1) {
  66                   ivl_nexus_t nex = ivl_signal_pin(sig, 0);
  67                   fprintf(xnf, "SIG, %s, PIN=%s\n",
  68                           xnf_mangle_nexus_name(nex), use_name);
  69
  70             } else {
  71                   unsigned pin;
  72
  73                   for (pin = 0 ; pin < ivl_signal_pins(sig); pin += 1) {
  74                         ivl_nexus_t nex = ivl_signal_pin(sig, pin);
  75                         fprintf(xnf, "SIG, %s, PIN=%s%u\n",
  76                                 xnf_mangle_nexus_name(nex), use_name,
  77                                 pin);
  78                   }
  79             }
  80       }
  81 }
  82
  83 static void show_design_consts_xnf(ivl_design_t des)
  84 {
  85       unsigned idx;
  86
  87       for (idx = 0 ;  idx < ivl_design_consts(des) ;  idx += 1) {
  88             unsigned pin;
  89             ivl_net_const_t net = ivl_design_const(des, idx);
  90             const char*val = ivl_const_bits(net);
  91
  92             for (pin = 0 ;  pin < ivl_const_pins(net) ;  pin += 1) {
  93                   ivl_nexus_t nex = ivl_const_pin(net, pin);
  94                   fprintf(xnf, "PWR,%c,%s\n", val[pin],
  95                           xnf_mangle_nexus_name(nex));
  96             }
  97       }
  98 }
  99
 100 static void generic_show_header(ivl_design_t des)
 101 {
 102       ivl_scope_t root = ivl_design_root(des);
 103
 104       fprintf(xnf, "LCANET,6\n");
 105       fprintf(xnf, "PROG,iverilog,$Name:  $,\"Icarus Verilog/fpga.tgt\"\n");
 106
 107       if (part && (part[0]!=0)) {
 108             fprintf(xnf, "PART,%s\n", part);
 109       }
 110
 111       show_root_ports_xnf(root);
 112 }
 113
 114 static void generic_show_footer(ivl_design_t des)
 115 {
 116       show_design_consts_xnf(des);
 117       fprintf(xnf, "EOF\n");
 118 }
 119
 120
 121 static void generic_show_logic(ivl_net_logic_t net)
 122 {
 123       char name[1024];
 124       ivl_nexus_t nex;
 125       unsigned idx;
 126
 127       xnf_mangle_logic_name(net, name, sizeof name);
 128
 129       switch (ivl_logic_type(net)) {
 130
 131           case IVL_LO_AND:
 132             fprintf(xnf, "SYM, %s, AND, LIBVER=2.0.0\n", name);
 133             nex = ivl_logic_pin(net, 0);
 134             xnf_draw_pin(nex, "O", 'O');
 135             for (idx = 1 ;  idx < ivl_logic_pins(net) ;  idx += 1) {
 136                   char ipin[32];
 137                   nex = ivl_logic_pin(net, idx);
 138                   sprintf(ipin, "I%u", idx-1);
 139                   xnf_draw_pin(nex, ipin, 'I');
 140             }
 141             fprintf(xnf, "END\n");
 142             break;
 143
 144           case IVL_LO_BUF:
 145             assert(ivl_logic_pins(net) == 2);
 146             fprintf(xnf, "SYM, %s, BUF, LIBVER=2.0.0\n", name);
 147             nex = ivl_logic_pin(net, 0);
 148             xnf_draw_pin(nex, "O", 'O');
 149             nex = ivl_logic_pin(net, 1);
 150             xnf_draw_pin(nex, "I", 'I');
 151             fprintf(xnf, "END\n");
 152             break;
 153
 154           case IVL_LO_NAND:
 155             fprintf(xnf, "SYM, %s, NAND, LIBVER=2.0.0\n", name);
 156             nex = ivl_logic_pin(net, 0);
 157             xnf_draw_pin(nex, "O", 'O');
 158             for (idx = 1 ;  idx < ivl_logic_pins(net) ;  idx += 1) {
 159                   char ipin[32];
 160                   nex = ivl_logic_pin(net, idx);
 161                   sprintf(ipin, "I%u", idx-1);
 162                   xnf_draw_pin(nex, ipin, 'I');
 163             }
 164             fprintf(xnf, "END\n");
 165             break;
 166
 167           case IVL_LO_NOR:
 168             fprintf(xnf, "SYM, %s, NOR, LIBVER=2.0.0\n", name);
 169             nex = ivl_logic_pin(net, 0);
 170             xnf_draw_pin(nex, "O", 'O');
 171             for (idx = 1 ;  idx < ivl_logic_pins(net) ;  idx += 1) {
 172                   char ipin[32];
 173                   nex = ivl_logic_pin(net, idx);
 174                   sprintf(ipin, "I%u", idx-1);
 175                   xnf_draw_pin(nex, ipin, 'I');
 176             }
 177             fprintf(xnf, "END\n");
 178             break;
 179
 180           case IVL_LO_NOT:
 181             assert(ivl_logic_pins(net) == 2);
 182             fprintf(xnf, "SYM, %s, INV, LIBVER=2.0.0\n", name);
 183             nex = ivl_logic_pin(net, 0);
 184             xnf_draw_pin(nex, "O", 'O');
 185             nex = ivl_logic_pin(net, 1);
 186             xnf_draw_pin(nex, "I", 'I');
 187             fprintf(xnf, "END\n");
 188             break;
 189
 190           case IVL_LO_OR:
 191             fprintf(xnf, "SYM, %s, OR, LIBVER=2.0.0\n", name);
 192             nex = ivl_logic_pin(net, 0);
 193             xnf_draw_pin(nex, "O", 'O');
 194             for (idx = 1 ;  idx < ivl_logic_pins(net) ;  idx += 1) {
 195                   char ipin[32];
 196                   nex = ivl_logic_pin(net, idx);
 197                   sprintf(ipin, "I%u", idx-1);
 198                   xnf_draw_pin(nex, ipin, 'I');
 199             }
 200             fprintf(xnf, "END\n");
 201             break;
 202
 203           case IVL_LO_XOR:
 204             fprintf(xnf, "SYM, %s, XOR, LIBVER=2.0.0\n", name);
 205             nex = ivl_logic_pin(net, 0);
 206             xnf_draw_pin(nex, "O", 'O');
 207             for (idx = 1 ;  idx < ivl_logic_pins(net) ;  idx += 1) {
 208                   char ipin[32];
 209                   nex = ivl_logic_pin(net, idx);
 210                   sprintf(ipin, "I%u", idx-1);
 211                   xnf_draw_pin(nex, ipin, 'I');
 212             }
 213             fprintf(xnf, "END\n");
 214             break;
 215
 216           case IVL_LO_XNOR:
 217             fprintf(xnf, "SYM, %s, XNOR, LIBVER=2.0.0\n", name);
 218             nex = ivl_logic_pin(net, 0);
 219             xnf_draw_pin(nex, "O", 'O');
 220             for (idx = 1 ;  idx < ivl_logic_pins(net) ;  idx += 1) {
 221                   char ipin[32];
 222                   nex = ivl_logic_pin(net, idx);
 223                   sprintf(ipin, "I%u", idx-1);
 224                   xnf_draw_pin(nex, ipin, 'I');
 225             }
 226             fprintf(xnf, "END\n");
 227             break;
 228
 229           case IVL_LO_BUFIF0:
 230             fprintf(xnf, "SYM, %s, TBUF, LIBVER=2.0.0\n", name);
 231             nex = ivl_logic_pin(net, 0);
 232             xnf_draw_pin(nex, "O", 'O');
 233             nex = ivl_logic_pin(net, 1);
 234             xnf_draw_pin(nex, "I", 'I');
 235             nex = ivl_logic_pin(net, 2);
 236             xnf_draw_pin(nex, "~T", 'I');
 237             fprintf(xnf, "END\n");
 238             break;
 239
 240           case IVL_LO_BUFIF1:
 241             fprintf(xnf, "SYM, %s, TBUF, LIBVER=2.0.0\n", name);
 242             nex = ivl_logic_pin(net, 0);
 243             xnf_draw_pin(nex, "O", 'O');
 244             nex = ivl_logic_pin(net, 1);
 245             xnf_draw_pin(nex, "I", 'I');
 246             nex = ivl_logic_pin(net, 2);
 247             xnf_draw_pin(nex, "T", 'I');
 248             fprintf(xnf, "END\n");
 249             break;
 250
 251           default:
 252             fprintf(stderr, "fpga.tgt: unknown logic type %u\n",
 253                     ivl_logic_type(net));
 254             break;
 255       }
 256
 257 }
 258
 259 static void generic_show_dff(ivl_lpm_t net)
 260 {
 261       char name[1024];
 262       ivl_nexus_t nex;
 263
 264       xnf_mangle_lpm_name(net, name, sizeof name);
 265
 266       fprintf(xnf, "SYM, %s, DFF, LIBVER=2.0.0\n", name);
 267
 268       nex = ivl_lpm_q(net, 0);
 269       xnf_draw_pin(nex, "Q", 'O');
 270
 271       nex = ivl_lpm_data(net, 0);
 272       xnf_draw_pin(nex, "D", 'I');
 273
 274       nex = ivl_lpm_clk(net);
 275       xnf_draw_pin(nex, "C", 'I');
 276
 277       if ((nex = ivl_lpm_enable(net)))
 278             xnf_draw_pin(nex, "CE", 'I');
 279
 280       fprintf(xnf, "END\n");
 281 }
 282
 283 /*
 284  * The generic == comparator uses EQN records to generate 2-bit
 285  * comparators, that are then connected together by a wide AND gate.
 286  */
 287 static void generic_show_cmp_eq(ivl_lpm_t net)
 288 {
 289       ivl_nexus_t nex;
 290       unsigned idx;
 291       char name[1024];
 292         /* Make this many dual pair comparators, and */
 293       unsigned deqn = ivl_lpm_width(net) / 2;
 294         /* Make this many single pair comparators. */
 295       unsigned seqn = ivl_lpm_width(net) % 2;
 296
 297       xnf_mangle_lpm_name(net, name, sizeof name);
 298
 299       for (idx = 0 ;  idx < deqn ;  idx += 1) {
 300             fprintf(xnf, "SYM, %s/CD%u, EQN, "
 301                     "EQN=(~((I0 @ I1) + (I2 @ I3)))\n",
 302                     name, idx);
 303
 304             fprintf(xnf, "    PIN, O, O, %s/CDO%u\n", name, idx);
 305
 306             nex = ivl_lpm_data(net, 2*idx);
 307             xnf_draw_pin(nex, "I0", 'I');
 308             nex = ivl_lpm_datab(net, 2*idx);
 309             xnf_draw_pin(nex, "I1", 'I');
 310
 311             nex = ivl_lpm_data(net, 2*idx+1);
 312             xnf_draw_pin(nex, "I2", 'I');
 313             nex = ivl_lpm_datab(net, 2*idx+1);
 314             xnf_draw_pin(nex, "I3", 'I');
 315
 316             fprintf(xnf, "END\n");
 317       }
 318
 319       if (seqn != 0) {
 320             fprintf(xnf, "SYM, %s/CT, XNOR, LIBVER=2.0.0\n", name);
 321
 322             fprintf(xnf, "    PIN, O, O, %s/CTO\n", name);
 323
 324             nex = ivl_lpm_data(net, 2*deqn);
 325             xnf_draw_pin(nex, "I0", 'I');
 326
 327             nex = ivl_lpm_datab(net, 2*deqn);
 328             xnf_draw_pin(nex, "I1", 'I');
 329
 330             fprintf(xnf, "END\n");
 331       }
 332
 333       if (ivl_lpm_type(net) == IVL_LPM_CMP_EQ)
 334             fprintf(xnf, "SYM, %s/OUT, AND, LIBVER=2.0.0\n", name);
 335       else
 336             fprintf(xnf, "SYM, %s/OUT, NAND, LIBVER=2.0.0\n", name);
 337
 338       nex = ivl_lpm_q(net, 0);
 339       xnf_draw_pin(nex, "O", 'O');
 340
 341       for (idx = 0 ;  idx < deqn ;  idx += 1)
 342             fprintf(xnf, "    PIN, I%u, I, %s/CDO%u\n", idx, name, idx);
 343
 344       for (idx = 0 ;  idx < seqn ;  idx += 1)
 345             fprintf(xnf, "    PIN, I%u, I, %s/CTO\n", deqn+idx, name);
 346
 347       fprintf(xnf, "END\n");
 348 }
 349
 350 /*
 351  * This function draws N-bit wide binary mux devices. These are so
 352  * very popular because they are the result of such expressions as:
 353  *
 354  *        x = sel? a : b;
 355  *
 356  * This code only supports the case where sel is a single bit. It
 357  * works by drawing for each bit of the width an EQN device that takes
 358  * as inputs I0 and I1 the alternative inputs, and I2 the select. The
 359  * select bit is common with all the generated mux devices.
 360  */
 361 static void generic_show_mux(ivl_lpm_t net)
 362 {
 363       char name[1024];
 364       ivl_nexus_t nex, sel;
 365       unsigned idx;
 366
 367       xnf_mangle_lpm_name(net, name, sizeof name);
 368
 369         /* Access the single select bit. This is common to the whole
 370            width of the mux. */
 371       assert(ivl_lpm_selects(net) == 1);
 372       sel = ivl_lpm_select(net, 0);
 373
 374       for (idx = 0 ;  idx < ivl_lpm_width(net) ;  idx += 1) {
 375             fprintf(xnf, "SYM, %s/M%u, EQN, "
 376                     "EQN=((I0 * ~I2) + (I1 * I2))\n",
 377                     name, idx);
 378
 379             nex = ivl_lpm_q(net, idx);
 380             xnf_draw_pin(nex, "O", 'O');
 381
 382             nex = ivl_lpm_data2(net, 0, idx);
 383             xnf_draw_pin(nex, "I0", 'I');
 384
 385             nex = ivl_lpm_data2(net, 1, idx);
 386             xnf_draw_pin(nex, "I1", 'I');
 387
 388             xnf_draw_pin(sel, "I2", 'I');
 389
 390             fprintf(xnf, "END\n");
 391       }
 392 }
 393
 394 /*
 395  * This code cheats and just generates ADD4 devices enough to support
 396  * the add. Make no effort to optimize, because we have no idea what
 397  * kind of device we have.
 398  */
 399 static void generic_show_add(ivl_lpm_t net)
 400 {
 401       char name[1024];
 402       ivl_nexus_t nex;
 403       unsigned idx, nadd4, tail;
 404
 405       xnf_mangle_lpm_name(net, name, sizeof name);
 406
 407         /* Make this many ADD4 devices. */
 408       nadd4 = ivl_lpm_width(net) / 4;
 409       tail  = ivl_lpm_width(net) % 4;
 410
 411       for (idx = 0 ;  idx < nadd4 ;  idx += 1) {
 412             fprintf(xnf, "SYM, %s/A%u, ADD4\n", name, idx);
 413
 414             if (idx > 0)
 415                   fprintf(xnf, "    PIN, CI, I, %s/CO%u\n", name, idx-1);
 416
 417             nex = ivl_lpm_q(net, idx*4+0);
 418             xnf_draw_pin(nex, "S0", 'O');
 419
 420             nex = ivl_lpm_q(net, idx*4+1);
 421             xnf_draw_pin(nex, "S1", 'O');
 422
 423             nex = ivl_lpm_q(net, idx*4+2);
 424             xnf_draw_pin(nex, "S2", 'O');
 425
 426             nex = ivl_lpm_q(net, idx*4+3);
 427             xnf_draw_pin(nex, "S3", 'O');
 428
 429             nex = ivl_lpm_data(net, idx*4+0);
 430             xnf_draw_pin(nex, "A0", 'I');
 431
 432             nex = ivl_lpm_data(net, idx*4+1);
 433             xnf_draw_pin(nex, "A1", 'I');
 434
 435             nex = ivl_lpm_data(net, idx*4+2);
 436             xnf_draw_pin(nex, "A2", 'I');
 437
 438             nex = ivl_lpm_data(net, idx*4+3);
 439             xnf_draw_pin(nex, "A3", 'I');
 440
 441             nex = ivl_lpm_datab(net, idx*4+0);
 442             xnf_draw_pin(nex, "B0", 'I');
 443
 444             nex = ivl_lpm_datab(net, idx*4+1);
 445             xnf_draw_pin(nex, "B1", 'I');
 446
 447             nex = ivl_lpm_datab(net, idx*4+2);
 448             xnf_draw_pin(nex, "B2", 'I');
 449
 450             nex = ivl_lpm_datab(net, idx*4+3);
 451             xnf_draw_pin(nex, "B3", 'I');
 452
 453             if ((idx*4+4) < ivl_lpm_width(net))
 454                   fprintf(xnf, "    PIN, CO, O, %s/CO%u\n", name, idx);
 455
 456             fprintf(xnf, "END\n");
 457       }
 458
 459       if (tail > 0) {
 460             fprintf(xnf, "SYM, %s/A%u, ADD4\n", name, nadd4);
 461             if (nadd4 > 0)
 462                   fprintf(xnf, "    PIN, CI, I, %s/CO%u\n", name, nadd4-1);
 463
 464             switch (tail) {
 465                 case 3:
 466                   nex = ivl_lpm_data(net, nadd4*4+2);
 467                   xnf_draw_pin(nex, "A2", 'I');
 468
 469                   nex = ivl_lpm_datab(net, nadd4*4+2);
 470                   xnf_draw_pin(nex, "B2", 'I');
 471
 472                   nex = ivl_lpm_q(net, nadd4*4+2);
 473                   xnf_draw_pin(nex, "S2", 'O');
 474                 case 2:
 475                   nex = ivl_lpm_data(net, nadd4*4+1);
 476                   xnf_draw_pin(nex, "A1", 'I');
 477
 478                   nex = ivl_lpm_datab(net, nadd4*4+1);
 479                   xnf_draw_pin(nex, "B1", 'I');
 480
 481                   nex = ivl_lpm_q(net, nadd4*4+1);
 482                   xnf_draw_pin(nex, "S1", 'O');
 483                 case 1:
 484                   nex = ivl_lpm_data(net, nadd4*4+0);
 485                   xnf_draw_pin(nex, "A0", 'I');
 486
 487                   nex = ivl_lpm_datab(net, nadd4*4+0);
 488                   xnf_draw_pin(nex, "B0", 'I');
 489
 490                   nex = ivl_lpm_q(net, nadd4*4+0);
 491                   xnf_draw_pin(nex, "S0", 'O');
 492             }
 493
 494             fprintf(xnf, "END\n");
 495       }
 496 }
 497
 498 const struct device_s d_generic = {
 499       generic_show_header,
 500       generic_show_footer,
 501       0, /* show_scope */
 502       0, /* show_pad not implemented */
 503       generic_show_logic,
 504       generic_show_dff,
 505       generic_show_cmp_eq,
 506       generic_show_cmp_eq,
 507       0, /* ge not implemented */
 508       0, /* gt not implemented */
 509       generic_show_mux,
 510       generic_show_add,
 511       0, /* subtract not implemented */
 512       0,
 513       0
 514 };
 515
 516
 517 /*
 518  * $Log: d-generic.c,v $
 519  * Revision 1.14  2003/11/12 03:20:14  steve
 520  *  devices need show_cmp_gt
 521  *
 522  * Revision 1.13  2003/06/24 03:55:00  steve
 523  *  Add ivl_synthesis_cell support for virtex2.
 524  *
 525  * Revision 1.12  2002/10/28 02:05:56  steve
 526  *  Add Virtex code generators for left shift,
 527  *  subtraction, and GE comparators.
 528  *
 529  * Revision 1.11  2002/08/12 01:35:02  steve
 530  *  conditional ident string using autoconfig.
 531  *
 532  * Revision 1.10  2002/08/11 23:47:04  steve
 533  *  Add missing Log and Ident strings.
 534  *
 535  * Revision 1.9  2001/09/16 01:48:16  steve
 536  *  Suppor the PAD attribute on signals.
 537  *
 538  * Revision 1.8  2001/09/02 21:33:07  steve
 539  *  Rearrange the XNF code generator to be generic-xnf
 540  *  so that non-XNF code generation is also possible.
 541  *
 542  *  Start into the virtex EDIF output driver.
 543  *
 544  * Revision 1.7  2001/09/01 04:30:44  steve
 545  *  Generic ADD code.
 546  *
 547  * Revision 1.6  2001/09/01 02:28:42  steve
 548  *  Generate code for MUX devices.
 549  *
 550  * Revision 1.5  2001/09/01 02:01:30  steve
 551  *  identity compare, and PWR records for constants.
 552  *
 553  * Revision 1.4  2001/08/31 23:02:13  steve
 554  *  Relax pin count restriction on logic gates.
 555  *
 556  * Revision 1.3  2001/08/31 04:17:56  steve
 557  *  Many more logic gate types.
 558  *
 559  * Revision 1.2  2001/08/31 02:59:06  steve
 560  *  Add root port SIG records.
 561  *
 562  * Revision 1.1  2001/08/28 04:14:20  steve
 563  *  Add the fpga target.
 564  *
 565  */
 566