tgt-fpga/fpga.c

   1 /*
   2  * Copyright (c) 2001 Stephen Williams (steve@icarus.com)
   3  *
   4  *    This source code is free software; you can redistribute it
   5  *    and/or modify it in source code form under the terms of the GNU
   6  *    General Public License as published by the Free Software
   7  *    Foundation; either version 2 of the License, or (at your option)
   8  *    any later version.
   9  *
  10  *    This program is distributed in the hope that it will be useful,
  11  *    but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  *    GNU General Public License for more details.
  14  *
  15  *    You should have received a copy of the GNU General Public License
  16  *    along with this program; if not, write to the Free Software
  17  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  18  */
  19 #ifdef HAVE_CVS_IDENT
  20 #ident "$Id: fpga.c,v 1.10 2003/10/27 02:18:28 steve Exp $"
  21 #endif
  22
  23 # include "config.h"
  24
  25 /*
  26  * This is the FPGA target module.
  27  */
  28
  29 # include  <ivl_target.h>
  30 # include  <string.h>
  31 # include  "fpga_priv.h"
  32 # include  <assert.h>
  33
  34 /* This is the opened xnf file descriptor. It is the output that this
  35    code generator writes to. */
  36 FILE*xnf = 0;
  37
  38 const char*part = 0;
  39 const char*arch = 0;
  40 device_t device = 0;
  41
  42 int scope_has_attribute(ivl_scope_t s, const char *name)
  43 {
  44       int i;
  45       const struct ivl_attribute_s *a;
  46       for (i=0; i<ivl_scope_attr_cnt(s); i++) {
  47               a = ivl_scope_attr_val(s, i);
  48               if (strcmp(a->key,name) == 0)
  49                     return 1;
  50       }
  51       return 0;
  52 }
  53
  54 static int show_process(ivl_process_t net, void*x)
  55 {
  56       ivl_scope_t scope = ivl_process_scope(net);
  57
  58         /* Ignore processes that are within scopes that are cells. The
  59            cell_scope will generate a cell to represent the entire
  60            scope. */
  61       if (scope_has_attribute(scope, "ivl_synthesis_cell"))
  62             return 0;
  63
  64       fprintf(stderr, "fpga target: unsynthesized behavioral code\n");
  65       return 0;
  66 }
  67
  68 static void show_pads(ivl_scope_t scope)
  69 {
  70       unsigned idx;
  71
  72       if (device->show_pad == 0)
  73             return;
  74
  75       for (idx = 0 ;  idx < ivl_scope_sigs(scope) ;  idx += 1) {
  76             ivl_signal_t sig = ivl_scope_sig(scope, idx);
  77             const char*pad;
  78
  79             if (ivl_signal_port(sig) == IVL_SIP_NONE)
  80                   continue;
  81
  82             pad = ivl_signal_attr(sig, "PAD");
  83             if (pad == 0)
  84                   continue;
  85
  86             assert(device->show_pad);
  87             device->show_pad(sig, pad);
  88       }
  89 }
  90
  91 static void show_constants(ivl_design_t des)
  92 {
  93       unsigned idx;
  94
  95       if (device->show_constant == 0)
  96             return;
  97
  98       for (idx = 0 ;  idx < ivl_design_consts(des) ;  idx += 1) {
  99             ivl_net_const_t con = ivl_design_const(des, idx);
 100             device->show_constant(con);
 101       }
 102 }
 103
 104 /*
 105  * This is the main entry point that ivl uses to invoke me, the code
 106  * generator.
 107  */
 108 int target_design(ivl_design_t des)
 109 {
 110       ivl_scope_t root = ivl_design_root(des);
 111       const char*path = ivl_design_flag(des, "-o");
 112
 113       xnf = fopen(path, "w");
 114       if (xnf == 0) {
 115             perror(path);
 116             return -1;
 117       }
 118
 119       part = ivl_design_flag(des, "part");
 120       if (part && (part[0] == 0))
 121             part = 0;
 122
 123       arch = ivl_design_flag(des, "arch");
 124       if (arch && (arch[0] == 0))
 125             arch = 0;
 126
 127       if (arch == 0)
 128             arch = "lpm";
 129
 130       device = device_from_arch(arch);
 131       if (device == 0) {
 132             fprintf(stderr, "Unknown architecture arch=%s\n", arch);
 133             return -1;
 134       }
 135
 136         /* Call the device driver to generate the netlist header. */
 137       device->show_header(des);
 138
 139         /* Catch any behavioral code that is left, and write warnings
 140            that it is not supported. */
 141       ivl_design_process(des, show_process, 0);
 142
 143         /* Get the pads from the design, and draw them to connect to
 144            the associated signals. */
 145       show_pads(root);
 146
 147         /* Scan the scopes, looking for gates to draw into the output
 148            netlist. */
 149       show_scope_gates(root, 0);
 150
 151       show_constants(des);
 152
 153         /* Call the device driver to close out the file. */
 154       device->show_footer(des);
 155
 156       fclose(xnf);
 157       xnf = 0;
 158       return 0;
 159 }
 160
 161 /*
 162  * $Log: fpga.c,v $
 163  * Revision 1.10  2003/10/27 02:18:28  steve
 164  *  Emit constants for LPM device.
 165  *
 166  * Revision 1.9  2003/08/07 04:04:01  steve
 167  *  Add an LPM device type.
 168  *
 169  * Revision 1.8  2003/06/25 01:49:06  steve
 170  *  Spelling fixes.
 171  *
 172  * Revision 1.7  2003/06/24 03:55:00  steve
 173  *  Add ivl_synthesis_cell support for virtex2.
 174  *
 175  * Revision 1.6  2002/08/12 01:35:02  steve
 176  *  conditional ident string using autoconfig.
 177  *
 178  * Revision 1.5  2001/09/16 01:48:16  steve
 179  *  Suppor the PAD attribute on signals.
 180  *
 181  * Revision 1.4  2001/09/02 21:33:07  steve
 182  *  Rearrange the XNF code generator to be generic-xnf
 183  *  so that non-XNF code generation is also possible.
 184  *
 185  *  Start into the virtex EDIF output driver.
 186  *
 187  * Revision 1.3  2001/09/01 02:01:30  steve
 188  *  identity compare, and PWR records for constants.
 189  *
 190  * Revision 1.2  2001/08/31 02:59:06  steve
 191  *  Add root port SIG records.
 192  *
 193  * Revision 1.1  2001/08/28 04:14:20  steve
 194  *  Add the fpga target.
 195  *
 196  */
 197