tgt-fpga/xilinx.c

   1 /*
   2  * Copyright (c) 2003 Stephen Williams (steve at icarus.com)
   3  *
   4  *    This source code is free software; you can redistribute it
   5  *    and/or modify it in source code form under the terms of the GNU
   6  *    General Public License as published by the Free Software
   7  *    Foundation; either version 2 of the License, or (at your option)
   8  *    any later version.
   9  *
  10  *    This program is distributed in the hope that it will be useful,
  11  *    but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  *    GNU General Public License for more details.
  14  *
  15  *    You should have received a copy of the GNU General Public License
  16  *    along with this program; if not, write to the Free Software
  17  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  18  */
  19 #ifdef HAVE_CVS_IDENT
  20 #ident "$Id: xilinx.c,v 1.13 2007/02/26 19:49:50 steve Exp $"
  21 #endif
  22
  23 # include  "edif.h"
  24 # include  "generic.h"
  25 # include  "xilinx.h"
  26 # include  "fpga_priv.h"
  27 # include  <stdlib.h>
  28 # include  <string.h>
  29 #ifdef HAVE_MALLOC_H
  30 # include  <malloc.h>
  31 #endif
  32 # include  <assert.h>
  33
  34 edif_cell_t xilinx_cell_buf(edif_xlibrary_t xlib)
  35 {
  36       static edif_cell_t cell = 0;
  37       if (cell) return cell;
  38
  39       cell = edif_xcell_create(xlib, "BUF", 2);
  40       edif_cell_portconfig(cell, BUF_O, "O", IVL_SIP_OUTPUT);
  41       edif_cell_portconfig(cell, BUF_I, "I", IVL_SIP_INPUT);
  42       return cell;
  43 }
  44
  45 edif_cell_t xilinx_cell_bufe(edif_xlibrary_t xlib)
  46 {
  47       static edif_cell_t cell = 0;
  48       if (cell) return cell;
  49
  50       cell = edif_xcell_create(xlib, "BUFE", 3);
  51       edif_cell_portconfig(cell, BUF_O, "O", IVL_SIP_OUTPUT);
  52       edif_cell_portconfig(cell, BUF_I, "I", IVL_SIP_INPUT);
  53       edif_cell_portconfig(cell, BUF_T, "E", IVL_SIP_INPUT);
  54       return cell;
  55 }
  56
  57 edif_cell_t xilinx_cell_bufg(edif_xlibrary_t xlib)
  58 {
  59       static edif_cell_t cell = 0;
  60       if (cell) return cell;
  61
  62       cell = edif_xcell_create(xlib, "BUFG", 2);
  63       edif_cell_portconfig(cell, BUF_O, "O", IVL_SIP_OUTPUT);
  64       edif_cell_portconfig(cell, BUF_I, "I", IVL_SIP_INPUT);
  65       return cell;
  66 }
  67
  68 edif_cell_t xilinx_cell_buft(edif_xlibrary_t xlib)
  69 {
  70       static edif_cell_t cell = 0;
  71       if (cell) return cell;
  72
  73       cell = edif_xcell_create(xlib, "BUFT", 3);
  74       edif_cell_portconfig(cell, BUF_O, "O", IVL_SIP_OUTPUT);
  75       edif_cell_portconfig(cell, BUF_I, "I", IVL_SIP_INPUT);
  76       edif_cell_portconfig(cell, BUF_T, "T", IVL_SIP_INPUT);
  77       return cell;
  78 }
  79
  80 edif_cell_t xilinx_cell_ibuf(edif_xlibrary_t xlib)
  81 {
  82       static edif_cell_t cell = 0;
  83       if (cell) return cell;
  84
  85       cell = edif_xcell_create(xlib, "IBUF", 2);
  86       edif_cell_portconfig(cell, BUF_O, "O", IVL_SIP_OUTPUT);
  87       edif_cell_portconfig(cell, BUF_I, "I", IVL_SIP_INPUT);
  88       return cell;
  89 }
  90
  91 edif_cell_t xilinx_cell_inv(edif_xlibrary_t xlib)
  92 {
  93       static edif_cell_t cell = 0;
  94       if (cell) return cell;
  95
  96       cell = edif_xcell_create(xlib, "INV", 2);
  97       edif_cell_portconfig(cell, BUF_O, "O", IVL_SIP_OUTPUT);
  98       edif_cell_portconfig(cell, BUF_I, "I", IVL_SIP_INPUT);
  99       return cell;
 100 }
 101
 102 edif_cell_t xilinx_cell_muxf5(edif_xlibrary_t xlib)
 103 {
 104       static edif_cell_t cell = 0;
 105       if (cell) return cell;
 106
 107       cell = edif_xcell_create(xlib, "MUXF5", 4);
 108       edif_cell_portconfig(cell, MUXF_O,  "O",  IVL_SIP_OUTPUT);
 109       edif_cell_portconfig(cell, MUXF_I0, "I0", IVL_SIP_INPUT);
 110       edif_cell_portconfig(cell, MUXF_I1, "I1", IVL_SIP_INPUT);
 111       edif_cell_portconfig(cell, MUXF_S,  "S",  IVL_SIP_INPUT);
 112       return cell;
 113 }
 114
 115 edif_cell_t xilinx_cell_muxf6(edif_xlibrary_t xlib)
 116 {
 117       static edif_cell_t cell = 0;
 118       if (cell) return cell;
 119
 120       cell = edif_xcell_create(xlib, "MUXF6", 4);
 121       edif_cell_portconfig(cell, MUXF_O,  "O",  IVL_SIP_OUTPUT);
 122       edif_cell_portconfig(cell, MUXF_I0, "I0", IVL_SIP_INPUT);
 123       edif_cell_portconfig(cell, MUXF_I1, "I1", IVL_SIP_INPUT);
 124       edif_cell_portconfig(cell, MUXF_S,  "S",  IVL_SIP_INPUT);
 125       return cell;
 126 }
 127
 128 edif_cell_t xilinx_cell_obuf(edif_xlibrary_t xlib)
 129 {
 130       static edif_cell_t cell = 0;
 131       if (cell) return cell;
 132
 133       cell = edif_xcell_create(xlib, "OBUF", 2);
 134       edif_cell_portconfig(cell, BUF_O, "O", IVL_SIP_OUTPUT);
 135       edif_cell_portconfig(cell, BUF_I, "I", IVL_SIP_INPUT);
 136       return cell;
 137 }
 138
 139
 140 edif_cell_t xilinx_cell_lut2(edif_xlibrary_t xlib)
 141 {
 142       static edif_cell_t cell = 0;
 143       if (cell != 0) return cell;
 144
 145       cell = edif_xcell_create(xlib, "LUT2", 3);
 146       edif_cell_portconfig(cell, LUT_O,  "O",  IVL_SIP_OUTPUT);
 147       edif_cell_portconfig(cell, LUT_I0, "I0", IVL_SIP_INPUT);
 148       edif_cell_portconfig(cell, LUT_I1, "I1", IVL_SIP_INPUT);
 149       return cell;
 150 }
 151
 152 edif_cell_t xilinx_cell_lut3(edif_xlibrary_t xlib)
 153 {
 154       static edif_cell_t cell = 0;
 155       if (cell != 0) return cell;
 156
 157       cell = edif_xcell_create(xlib, "LUT3", 4);
 158       edif_cell_portconfig(cell, LUT_O,  "O",  IVL_SIP_OUTPUT);
 159       edif_cell_portconfig(cell, LUT_I0, "I0", IVL_SIP_INPUT);
 160       edif_cell_portconfig(cell, LUT_I1, "I1", IVL_SIP_INPUT);
 161       edif_cell_portconfig(cell, LUT_I2, "I2", IVL_SIP_INPUT);
 162       return cell;
 163 }
 164
 165 edif_cell_t xilinx_cell_lut4(edif_xlibrary_t xlib)
 166 {
 167       static edif_cell_t cell = 0;
 168       if (cell != 0) return cell;
 169
 170       cell = edif_xcell_create(xlib, "LUT4", 5);
 171       edif_cell_portconfig(cell, LUT_O,  "O",  IVL_SIP_OUTPUT);
 172       edif_cell_portconfig(cell, LUT_I0, "I0", IVL_SIP_INPUT);
 173       edif_cell_portconfig(cell, LUT_I1, "I1", IVL_SIP_INPUT);
 174       edif_cell_portconfig(cell, LUT_I2, "I2", IVL_SIP_INPUT);
 175       edif_cell_portconfig(cell, LUT_I3, "I3", IVL_SIP_INPUT);
 176       return cell;
 177 }
 178
 179
 180 edif_cell_t xilinx_cell_fdce(edif_xlibrary_t xlib)
 181 {
 182       static edif_cell_t cell = 0;
 183       if (cell != 0) return cell;
 184
 185       cell = edif_xcell_create(xlib, "FDCE", 5);
 186       edif_cell_portconfig(cell, FDCE_Q,  "Q",   IVL_SIP_OUTPUT);
 187       edif_cell_portconfig(cell, FDCE_D,  "D",   IVL_SIP_INPUT);
 188       edif_cell_portconfig(cell, FDCE_C,  "C",   IVL_SIP_INPUT);
 189       edif_cell_portconfig(cell, FDCE_CE, "CE",  IVL_SIP_INPUT);
 190       edif_cell_portconfig(cell, FDCE_CLR,"CLR", IVL_SIP_INPUT);
 191       return cell;
 192 }
 193
 194 edif_cell_t xilinx_cell_fdcpe(edif_xlibrary_t xlib)
 195 {
 196       static edif_cell_t cell = 0;
 197       if (cell != 0) return cell;
 198
 199       cell = edif_xcell_create(xlib, "FDCPE", 6);
 200       edif_cell_portconfig(cell, FDCE_Q,  "Q",   IVL_SIP_OUTPUT);
 201       edif_cell_portconfig(cell, FDCE_D,  "D",   IVL_SIP_INPUT);
 202       edif_cell_portconfig(cell, FDCE_C,  "C",   IVL_SIP_INPUT);
 203       edif_cell_portconfig(cell, FDCE_CE, "CE",  IVL_SIP_INPUT);
 204       edif_cell_portconfig(cell, FDCE_CLR,"CLR", IVL_SIP_INPUT);
 205       edif_cell_portconfig(cell, FDCE_PRE,"PRE", IVL_SIP_INPUT);
 206       return cell;
 207 }
 208
 209 edif_cell_t xilinx_cell_fdre(edif_xlibrary_t xlib)
 210 {
 211       static edif_cell_t cell = 0;
 212       if (cell != 0) return cell;
 213
 214       cell = edif_xcell_create(xlib, "FDRE", 5);
 215       edif_cell_portconfig(cell, FDCE_Q,  "Q",   IVL_SIP_OUTPUT);
 216       edif_cell_portconfig(cell, FDCE_D,  "D",   IVL_SIP_INPUT);
 217       edif_cell_portconfig(cell, FDCE_C,  "C",   IVL_SIP_INPUT);
 218       edif_cell_portconfig(cell, FDCE_CE, "CE",  IVL_SIP_INPUT);
 219       edif_cell_portconfig(cell, FDCE_CLR,"R",   IVL_SIP_INPUT);
 220       return cell;
 221 }
 222
 223
 224 edif_cell_t xilinx_cell_mult_and(edif_xlibrary_t xlib)
 225 {
 226       static edif_cell_t cell = 0;
 227       if (cell != 0) return cell;
 228
 229       cell = edif_xcell_create(xlib, "MULT_AND", 3);
 230       edif_cell_portconfig(cell, MULT_AND_LO, "LO", IVL_SIP_OUTPUT);
 231       edif_cell_portconfig(cell, MULT_AND_I0, "I0", IVL_SIP_INPUT);
 232       edif_cell_portconfig(cell, MULT_AND_I1, "I1", IVL_SIP_INPUT);
 233       return cell;
 234 }
 235
 236 edif_cell_t xilinx_cell_muxcy(edif_xlibrary_t xlib)
 237 {
 238       static edif_cell_t cell = 0;
 239       if (cell != 0) return cell;
 240
 241       cell = edif_xcell_create(xlib, "MUXCY", 4);
 242       edif_cell_portconfig(cell, MUXCY_O,  "O",  IVL_SIP_OUTPUT);
 243       edif_cell_portconfig(cell, MUXCY_DI, "DI", IVL_SIP_INPUT);
 244       edif_cell_portconfig(cell, MUXCY_CI, "CI", IVL_SIP_INPUT);
 245       edif_cell_portconfig(cell, MUXCY_S,  "S",  IVL_SIP_INPUT);
 246       return cell;
 247 }
 248
 249 edif_cell_t xilinx_cell_muxcy_l(edif_xlibrary_t xlib)
 250 {
 251       static edif_cell_t cell = 0;
 252       if (cell != 0) return cell;
 253
 254       cell = edif_xcell_create(xlib, "MUXCY_L", 4);
 255       edif_cell_portconfig(cell, MUXCY_O,  "LO", IVL_SIP_OUTPUT);
 256       edif_cell_portconfig(cell, MUXCY_DI, "DI", IVL_SIP_INPUT);
 257       edif_cell_portconfig(cell, MUXCY_CI, "CI", IVL_SIP_INPUT);
 258       edif_cell_portconfig(cell, MUXCY_S,  "S",  IVL_SIP_INPUT);
 259       return cell;
 260 }
 261
 262 edif_cell_t xilinx_cell_xorcy(edif_xlibrary_t xlib)
 263 {
 264       static edif_cell_t cell = 0;
 265       if (cell != 0) return cell;
 266
 267       cell = edif_xcell_create(xlib, "XORCY", 3);
 268       edif_cell_portconfig(cell, XORCY_O,  "O",  IVL_SIP_OUTPUT);
 269       edif_cell_portconfig(cell, XORCY_CI, "CI", IVL_SIP_INPUT);
 270       edif_cell_portconfig(cell, XORCY_LI, "LI", IVL_SIP_INPUT);
 271       return cell;
 272 }
 273
 274 /*
 275  * This function does a lot of the stuff common to the header
 276  * functions of various Xilinx families. This includes creating the edf
 277  * object that holds the netlist.
 278  */
 279 void xilinx_common_header(ivl_design_t des)
 280 {
 281       unsigned idx;
 282       ivl_scope_t root = ivl_design_root(des);
 283       unsigned sig_cnt = ivl_scope_sigs(root);
 284       unsigned nports = 0, pidx;
 285
 286         /* Count the ports I'm going to use. */
 287       for (idx = 0 ;  idx < sig_cnt ;  idx += 1) {
 288             ivl_signal_t sig = ivl_scope_sig(root, idx);
 289
 290             if (ivl_signal_port(sig) == IVL_SIP_NONE)
 291                   continue;
 292
 293             if (ivl_signal_attr(sig, "PAD") != 0)
 294                   continue;
 295
 296             nports += ivl_signal_pins(sig);
 297       }
 298
 299       edf = edif_create(ivl_scope_basename(root), nports);
 300
 301       pidx = 0;
 302       for (idx = 0 ;  idx < sig_cnt ;  idx += 1) {
 303             edif_joint_t jnt;
 304             ivl_signal_t sig = ivl_scope_sig(root, idx);
 305
 306             if (ivl_signal_port(sig) == IVL_SIP_NONE)
 307                   continue;
 308
 309             if (ivl_signal_attr(sig, "PAD") != 0)
 310                   continue;
 311
 312             if (ivl_signal_pins(sig) == 1) {
 313                   edif_portconfig(edf, pidx, ivl_signal_basename(sig),
 314                                   ivl_signal_port(sig));
 315
 316                   assert(ivl_signal_pins(sig) == 1);
 317                   jnt = edif_joint_of_nexus(edf, ivl_signal_pin(sig, 0));
 318                   edif_port_to_joint(jnt, edf, pidx);
 319
 320             } else {
 321                   const char*name = ivl_signal_basename(sig);
 322                   ivl_signal_port_t dir = ivl_signal_port(sig);
 323                   char buf[128];
 324                   unsigned bit;
 325                   for (bit = 0 ;  bit < ivl_signal_pins(sig) ; bit += 1) {
 326                         const char*tmp;
 327                         sprintf(buf, "%s[%u]", name, bit);
 328                         tmp = strdup(buf);
 329                         edif_portconfig(edf, pidx+bit, tmp, dir);
 330
 331                         jnt = edif_joint_of_nexus(edf,ivl_signal_pin(sig,bit));
 332                         edif_port_to_joint(jnt, edf, pidx+bit);
 333                   }
 334             }
 335
 336             pidx += ivl_signal_pins(sig);
 337       }
 338
 339       assert(pidx == nports);
 340 }
 341
 342 void xilinx_show_footer(ivl_design_t des)
 343 {
 344       unsigned idx;
 345
 346       for (idx = 0 ;  idx < ivl_design_consts(des) ;  idx += 1) {
 347             unsigned pin;
 348             ivl_net_const_t net = ivl_design_const(des, idx);
 349             const char*val = ivl_const_bits(net);
 350
 351             for (pin = 0 ;  pin < ivl_const_pins(net) ;  pin += 1) {
 352                   edif_joint_t jnt;
 353                   edif_cellref_t pad;
 354
 355                   jnt = edif_joint_of_nexus(edf, ivl_const_pin(net, pin));
 356                   switch (val[pin]) {
 357                       case '0':
 358                         pad = edif_cellref_create(edf, cell_0);
 359                         break;
 360                       case '1':
 361                         pad = edif_cellref_create(edf, cell_1);
 362                         break;
 363                       default:
 364                         assert(0);
 365                         break;
 366                   }
 367
 368                   edif_add_to_joint(jnt, pad, 0);
 369             }
 370       }
 371
 372       edif_print(xnf, edf);
 373 }
 374
 375 /*
 376  * Make (or retrieve) a cell in the external library that reflects the
 377  * scope with its ports.
 378  */
 379 void xilinx_show_scope(ivl_scope_t scope)
 380 {
 381       edif_cell_t cell;
 382       edif_cellref_t ref;
 383
 384       unsigned port, idx;
 385
 386       cell = edif_xlibrary_scope_cell(xlib, scope);
 387       ref = edif_cellref_create(edf, cell);
 388
 389       for (idx = 0 ;  idx < ivl_scope_sigs(scope) ;  idx += 1) {
 390             edif_joint_t jnt;
 391             ivl_signal_t sig = ivl_scope_sig(scope, idx);
 392
 393             if (ivl_signal_port(sig) == IVL_SIP_NONE)
 394                   continue;
 395
 396             port = edif_cell_port_byname(cell, ivl_signal_basename(sig));
 397             jnt = edif_joint_of_nexus(edf, ivl_signal_pin(sig, 0));
 398             edif_add_to_joint(jnt, ref, port);
 399       }
 400 }
 401
 402 void xilinx_pad(ivl_signal_t sig, const char*str)
 403 {
 404       unsigned idx;
 405       char**pins;
 406
 407       if (cell_ipad == 0) {
 408             cell_ipad = edif_xcell_create(xlib, "IPAD", 1);
 409             edif_cell_portconfig(cell_ipad, 0, "IPAD", IVL_SIP_OUTPUT);
 410       }
 411
 412       if (cell_opad == 0) {
 413             cell_opad = edif_xcell_create(xlib, "OPAD", 1);
 414             edif_cell_portconfig(cell_opad, 0, "OPAD", IVL_SIP_INPUT);
 415       }
 416
 417       if (cell_iopad == 0) {
 418             cell_iopad = edif_xcell_create(xlib, "IOPAD", 1);
 419             edif_cell_portconfig(cell_iopad, 0, "IOPAD", IVL_SIP_INOUT);
 420       }
 421
 422         /* Collect an array of pin assignments from the attribute
 423            string passed in as str. The format is a comma separated
 424            list of location names. */
 425       pins = calloc(ivl_signal_pins(sig), sizeof(char*));
 426       for (idx = 0 ;  idx < ivl_signal_pins(sig) ;  idx += 1) {
 427             const char*tmp = strchr(str, ',');
 428             if (tmp == 0) tmp = str+strlen(str);
 429
 430             pins[idx] = malloc(tmp-str+1);
 431             strncpy(pins[idx], str, tmp-str);
 432             pins[idx][tmp-str] = 0;
 433
 434             if (*tmp != 0)
 435                   tmp += 1;
 436
 437             str = tmp;
 438       }
 439
 440         /* Now go through the pins of the signal, creating pads and
 441            bufs and joining them to the signal nexus. */
 442       for (idx = 0 ;  idx < ivl_signal_pins(sig) ;  idx += 1) {
 443             edif_joint_t jnt;
 444             edif_cellref_t pad, buf;
 445
 446             const char*name_str = ivl_signal_basename(sig);
 447             if (ivl_signal_pins(sig) > 1) {
 448                   char name_buf[128];
 449                   sprintf(name_buf, "%s[%u]", name_str, idx);
 450                   name_str = strdup(name_buf);
 451             }
 452
 453             switch (ivl_signal_port(sig)) {
 454                 case IVL_SIP_INPUT:
 455                   pad = edif_cellref_create(edf, cell_ipad);
 456                   buf = edif_cellref_create(edf, xilinx_cell_ibuf(xlib));
 457
 458                   jnt = edif_joint_create(edf);
 459                   edif_joint_rename(jnt, name_str);
 460                   edif_add_to_joint(jnt, pad, 0);
 461                   edif_add_to_joint(jnt, buf, BUF_I);
 462
 463                   jnt = edif_joint_of_nexus(edf, ivl_signal_pin(sig, idx));
 464                   edif_add_to_joint(jnt, buf, BUF_O);
 465                   break;
 466
 467                 case IVL_SIP_OUTPUT:
 468                   pad = edif_cellref_create(edf, cell_opad);
 469                   buf = edif_cellref_create(edf, xilinx_cell_obuf(xlib));
 470
 471                   jnt = edif_joint_create(edf);
 472                   edif_joint_rename(jnt, name_str);
 473                   edif_add_to_joint(jnt, pad, 0);
 474                   edif_add_to_joint(jnt, buf, BUF_O);
 475
 476                   jnt = edif_joint_of_nexus(edf, ivl_signal_pin(sig, idx));
 477                   edif_add_to_joint(jnt, buf, BUF_I);
 478                   break;
 479
 480                 case IVL_SIP_INOUT:
 481                   pad = edif_cellref_create(edf, cell_iopad);
 482
 483                   jnt = edif_joint_of_nexus(edf, ivl_signal_pin(sig, idx));
 484                   edif_add_to_joint(jnt, pad, 0);
 485                   break;
 486
 487                 default:
 488                   assert(0);
 489             }
 490
 491             if (pins[idx])
 492                   edif_cellref_pstring(pad, "LOC", pins[idx]);
 493
 494       }
 495
 496         /* Don't free the allocated pad name strings. The
 497            edif_cellref_pstring function attached the string to the
 498            LOC attribute, so the reference is permanent. */
 499
 500       free(pins);
 501 }
 502
 503 /*
 504  * This function handles the case where the user specifies the cell to
 505  * use by attribute.
 506  */
 507 static void edif_cellref_logic(ivl_net_logic_t net, const char*def)
 508 {
 509       char*str = strdup(def);
 510       char*pins;
 511       edif_cell_t cell;
 512       edif_cellref_t ref;
 513       edif_joint_t jnt;
 514       unsigned idx, port;
 515
 516       pins = strchr(str, ':');
 517       assert(pins);
 518       *pins++ = 0;
 519
 520         /* Locate the cell in the library, lookup by name. */
 521       cell = edif_xlibrary_findcell(xlib, str);
 522       assert(cell);
 523
 524       ref = edif_cellref_create(edf, cell);
 525
 526       for (idx = 0 ;  idx < ivl_logic_pins(net) ;  idx += 1) {
 527             char*tmp;
 528
 529             assert(pins);
 530             tmp = strchr(pins,',');
 531             if (tmp != 0)
 532                   *tmp++ = 0;
 533             else
 534                   tmp = 0;
 535
 536             port = edif_cell_port_byname(cell, pins);
 537             jnt = edif_joint_of_nexus(edf, ivl_logic_pin(net, idx));
 538             edif_add_to_joint(jnt, ref, port);
 539
 540             pins = tmp;
 541       }
 542
 543       free(str);
 544 }
 545
 546 static void lut_logic(ivl_net_logic_t net, const char*init3,
 547                       const char*init4, const char*init5)
 548 {
 549       edif_cellref_t lut = NULL;  /* initialization shuts up gcc -Wall */
 550       edif_joint_t jnt;
 551       const char* init = NULL;    /* ditto */
 552
 553       assert(ivl_logic_pins(net) <= 5);
 554       assert(ivl_logic_pins(net) >= 3);
 555
 556       switch (ivl_logic_pins(net)) {
 557           case 3:
 558             lut = edif_cellref_create(edf, xilinx_cell_lut2(xlib));
 559             init = init3;
 560             break;
 561
 562           case 4:
 563             lut = edif_cellref_create(edf, xilinx_cell_lut3(xlib));
 564             init = init4;
 565             break;
 566
 567           case 5:
 568             lut = edif_cellref_create(edf, xilinx_cell_lut4(xlib));
 569             init = init5;
 570             break;
 571       }
 572
 573       edif_cellref_pstring(lut, "INIT", init);
 574
 575       switch (ivl_logic_pins(net)) {
 576           case 5:
 577             jnt = edif_joint_of_nexus(edf, ivl_logic_pin(net, 4));
 578             edif_add_to_joint(jnt, lut, LUT_I3);
 579           case 4:
 580             jnt = edif_joint_of_nexus(edf, ivl_logic_pin(net, 3));
 581             edif_add_to_joint(jnt, lut, LUT_I2);
 582           case 3:
 583             jnt = edif_joint_of_nexus(edf, ivl_logic_pin(net, 2));
 584             edif_add_to_joint(jnt, lut, LUT_I1);
 585       }
 586
 587       jnt = edif_joint_of_nexus(edf, ivl_logic_pin(net, 1));
 588       edif_add_to_joint(jnt, lut, LUT_I0);
 589
 590       jnt = edif_joint_of_nexus(edf, ivl_logic_pin(net, 0));
 591       edif_add_to_joint(jnt, lut, LUT_O);
 592 }
 593
 594
 595 void xilinx_logic(ivl_net_logic_t net)
 596 {
 597       edif_cellref_t obj;
 598       edif_joint_t   jnt;
 599
 600       { const char*cellref_attribute = ivl_logic_attr(net, "cellref");
 601         if (cellref_attribute != 0) {
 602               edif_cellref_logic(net, cellref_attribute);
 603               return;
 604         }
 605       }
 606
 607       switch (ivl_logic_type(net)) {
 608
 609           case IVL_LO_BUF:
 610           case IVL_LO_BUFZ:
 611             assert(ivl_logic_pins(net) == 2);
 612
 613             obj = edif_cellref_create(edf, xilinx_cell_buf(xlib));
 614
 615             jnt = edif_joint_of_nexus(edf, ivl_logic_pin(net, 0));
 616             edif_add_to_joint(jnt, obj, BUF_O);
 617
 618             jnt = edif_joint_of_nexus(edf, ivl_logic_pin(net, 1));
 619             edif_add_to_joint(jnt, obj, BUF_I);
 620             break;
 621
 622           case IVL_LO_BUFIF0:
 623               /* The Xilinx BUFT devices is a BUF that adds a T
 624                  input. The output is tri-stated if the T input is
 625                  1. In other words, it acts just like bufif0. */
 626             assert(ivl_logic_pins(net) == 3);
 627
 628             obj = edif_cellref_create(edf, xilinx_cell_buft(xlib));
 629
 630             jnt = edif_joint_of_nexus(edf, ivl_logic_pin(net, 0));
 631             edif_add_to_joint(jnt, obj, BUF_O);
 632
 633             jnt = edif_joint_of_nexus(edf, ivl_logic_pin(net, 1));
 634             edif_add_to_joint(jnt, obj, BUF_I);
 635
 636             jnt = edif_joint_of_nexus(edf, ivl_logic_pin(net, 2));
 637             edif_add_to_joint(jnt, obj, BUF_T);
 638             break;
 639
 640           case IVL_LO_BUFIF1:
 641               /* The Xilinx BUFE devices is a BUF that adds an enable
 642                  input. The output is tri-stated if the E input is 0.
 643                  In other words, it acts just like bufif1. */
 644             assert(ivl_logic_pins(net) == 3);
 645
 646             obj = edif_cellref_create(edf, xilinx_cell_bufe(xlib));
 647
 648             jnt = edif_joint_of_nexus(edf, ivl_logic_pin(net, 0));
 649             edif_add_to_joint(jnt, obj, BUF_O);
 650
 651             jnt = edif_joint_of_nexus(edf, ivl_logic_pin(net, 1));
 652             edif_add_to_joint(jnt, obj, BUF_I);
 653
 654             jnt = edif_joint_of_nexus(edf, ivl_logic_pin(net, 2));
 655             edif_add_to_joint(jnt, obj, BUF_T);
 656             break;
 657
 658           case IVL_LO_NOT:
 659             assert(ivl_logic_pins(net) == 2);
 660
 661             obj = edif_cellref_create(edf, xilinx_cell_inv(xlib));
 662
 663             jnt = edif_joint_of_nexus(edf, ivl_logic_pin(net, 0));
 664             edif_add_to_joint(jnt, obj, BUF_O);
 665
 666             jnt = edif_joint_of_nexus(edf, ivl_logic_pin(net, 1));
 667             edif_add_to_joint(jnt, obj, BUF_I);
 668             break;
 669
 670           case IVL_LO_AND:
 671             assert(ivl_logic_pins(net) <= 5);
 672             assert(ivl_logic_pins(net) >= 3);
 673             lut_logic(net, "8", "80", "8000");
 674             break;
 675
 676           case IVL_LO_NOR:
 677             assert(ivl_logic_pins(net) <= 5);
 678             assert(ivl_logic_pins(net) >= 3);
 679             lut_logic(net, "1", "01", "0001");
 680             break;
 681
 682           case IVL_LO_OR:
 683             assert(ivl_logic_pins(net) <= 5);
 684             assert(ivl_logic_pins(net) >= 3);
 685             lut_logic(net, "E", "FE", "FFFE");
 686             break;
 687
 688           case IVL_LO_XNOR:
 689             assert(ivl_logic_pins(net) <= 5);
 690             assert(ivl_logic_pins(net) >= 3);
 691             lut_logic(net, "9", "69", "9669");
 692             break;
 693
 694           case IVL_LO_XOR:
 695             assert(ivl_logic_pins(net) <= 5);
 696             assert(ivl_logic_pins(net) >= 3);
 697             lut_logic(net, "6", "96", "6996");
 698             break;
 699
 700           default:
 701             fprintf(stderr, "UNSUPPORTED LOGIC TYPE: %u\n",
 702                     ivl_logic_type(net));
 703             break;
 704       }
 705 }
 706
 707 /*
 708  * A fully generic Xilinx MUX is implemented entirely from LUT
 709  * devices.
 710  */
 711 void xilinx_mux(ivl_lpm_t net)
 712 {
 713       unsigned idx;
 714
 715       edif_cellref_t lut;
 716       edif_joint_t jnt;
 717
 718       assert(ivl_lpm_selects(net) == 1);
 719
 720         /* A/B Mux devices are made from LUT3 devices. I0 is connected
 721            to A, I1 to B, and I2 to the Select input. Create as many
 722            as are needed to implement the requested width.
 723
 724            S B A | Q
 725            ------+--
 726            0 0 0 | 0
 727            0 0 1 | 1
 728            0 1 0 | 0
 729            0 1 1 | 1
 730            1 0 0 | 0
 731            1 0 1 | 0
 732            1 1 0 | 1
 733            1 1 1 | 1
 734
 735            INIT = "CA" */
 736
 737       for (idx = 0 ;  idx < ivl_lpm_width(net) ;  idx += 1) {
 738
 739             lut = edif_cellref_create(edf, xilinx_cell_lut3(xlib));
 740
 741             jnt = edif_joint_of_nexus(edf, ivl_lpm_q(net, idx));
 742             edif_add_to_joint(jnt, lut, LUT_O);
 743
 744             jnt = edif_joint_of_nexus(edf, ivl_lpm_data2(net, 0, idx));
 745             edif_add_to_joint(jnt, lut, LUT_I0);
 746
 747             jnt = edif_joint_of_nexus(edf, ivl_lpm_data2(net, 1, idx));
 748             edif_add_to_joint(jnt, lut, LUT_I1);
 749
 750             jnt = edif_joint_of_nexus(edf, ivl_lpm_select(net, 0));
 751             edif_add_to_joint(jnt, lut, LUT_I2);
 752
 753             edif_cellref_pstring(lut, "INIT", "CA");
 754       }
 755 }
 756
 757 /*
 758  * Any Xilinx device works with this adder.
 759  * Generic Xilinx add only works for single bit slices.
 760  */
 761 void xilinx_add(ivl_lpm_t net)
 762 {
 763       const char*ha_init = 0;
 764       edif_cellref_t lut;
 765       edif_joint_t jnt;
 766
 767       switch (ivl_lpm_type(net)) {
 768             case IVL_LPM_ADD:
 769             ha_init = "6";
 770             break;
 771           case IVL_LPM_SUB:
 772             ha_init = "9";
 773             break;
 774           default:
 775             assert(0);
 776       }
 777
 778         /* If this is a single bit wide, then generate only a
 779            half-adder. Normally this is an XOR, but if this is a SUB
 780            then it is an XNOR. */
 781       if (ivl_lpm_width(net) == 1) {
 782
 783             lut = edif_cellref_create(edf, xilinx_cell_lut2(xlib));
 784
 785             jnt = edif_joint_of_nexus(edf, ivl_lpm_q(net, 0));
 786             edif_add_to_joint(jnt, lut, LUT_O);
 787
 788             jnt = edif_joint_of_nexus(edf, ivl_lpm_data(net, 0));
 789             edif_add_to_joint(jnt, lut, LUT_I0);
 790
 791             jnt = edif_joint_of_nexus(edf, ivl_lpm_datab(net, 0));
 792             edif_add_to_joint(jnt, lut, LUT_I1);
 793
 794             edif_cellref_pstring(lut, "INIT", ha_init);
 795             return;
 796       }
 797
 798       assert(0);
 799 }
 800
 801 /*
 802  * The left shift is implemented as a matrix of MUX2_1 devices. The
 803  * matrix has as many rows as the device width, and a column for each
 804  * select.
 805  */
 806 void xilinx_shiftl(ivl_lpm_t net)
 807 {
 808       unsigned width = ivl_lpm_width(net);
 809       unsigned nsel = 0, swid = 0;
 810       unsigned sdx, qdx;
 811
 812       edif_cellref_t* cells;
 813       edif_cellref_t**table;
 814
 815       edif_cellref_t pad0_cell;
 816       edif_joint_t pad0;
 817
 818
 819         /* First, find out how many select inputs we really need. We
 820            can only use the selects that are enough to shift out the
 821            entire width of the device. The excess can be used as an
 822            enable for the last column. When disabled, the last column
 823            emits zeros. */
 824
 825       while (nsel < ivl_lpm_selects(net)) {
 826
 827             nsel += 1;
 828
 829             swid = 1 << nsel;
 830             if (swid >= width)
 831                   break;
 832       }
 833
 834       assert(nsel > 0);
 835
 836         /* Allocate a matrix of edif_cellref_t variables. A devices
 837            will be addressed by the expression table[sdx][qdx];
 838            This should make the algorithm code easier to read. */
 839       cells = calloc(nsel * width, sizeof(edif_cellref_t));
 840       table = calloc(nsel, sizeof(edif_cellref_t*));
 841
 842       for (sdx = 0 ;  sdx < nsel ;  sdx += 1)
 843             table[sdx] = cells + sdx*width;
 844
 845         /* Make a 0 valued pad bit. I will use this for all the shift in
 846            values that are beyond the input. */
 847       pad0_cell = edif_cellref_create(edf, cell_0);
 848       pad0 = edif_joint_create(edf);
 849       edif_add_to_joint(pad0, pad0_cell, 0);
 850
 851         /* The LUT matrix is <nsel> columns of <width> devices, with
 852            the last column a LUT4 devices. The extra input of the
 853            LUT4s in the last column are used as an enable to collect
 854            all the excess select inputs. */
 855
 856         /* Allocate the LUT devices of the matrix, and connect the
 857            select inputs to I2 of all the devices of the column. */
 858       for (sdx = 0 ;  sdx < nsel ;  sdx += 1) {
 859             const char*init_string = 0;
 860             ivl_nexus_t nex = ivl_lpm_select(net,sdx);
 861             edif_joint_t sdx_jnt = edif_joint_of_nexus(edf, nex);
 862
 863             edif_cell_t lut;
 864
 865             if (((sdx+1) == nsel) && (nsel < ivl_lpm_selects(net))) {
 866                   lut = xilinx_cell_lut4(xlib);
 867                   init_string = "00CA";
 868             } else {
 869                   lut = xilinx_cell_lut3(xlib);
 870                   init_string = "CA";
 871             }
 872
 873             for (qdx = 0 ;  qdx < width ;  qdx += 1) {
 874                   table[sdx][qdx] = edif_cellref_create(edf, lut);
 875                   edif_add_to_joint(sdx_jnt, table[sdx][qdx], LUT_I2);
 876
 877                   edif_cellref_pstring(table[sdx][qdx], "INIT", init_string);
 878             }
 879       }
 880
 881         /* Connect the inputs of the SHIFTL device to the column 0 LUT
 882            inputs. The slice on the low end shifts in a 0 for a select
 883            input. */
 884       for (qdx = 0 ;  qdx < width ;  qdx += 1) {
 885             ivl_nexus_t nex0, nex1;
 886             edif_joint_t jnt0;
 887             edif_joint_t jnt1;
 888
 889             nex0 = ivl_lpm_data(net,qdx);
 890             jnt0 = edif_joint_of_nexus(edf, nex0);
 891
 892             if (qdx > 0) {
 893                   nex1 = ivl_lpm_data(net,qdx-1);
 894                   jnt1 = edif_joint_of_nexus(edf, nex1);
 895             } else {
 896                   jnt1 = pad0;
 897             }
 898
 899             edif_add_to_joint(jnt0, table[0][qdx], LUT_I0);
 900             edif_add_to_joint(jnt1, table[0][qdx], LUT_I1);
 901       }
 902
 903         /* Make the inner connections between LUT devices. Each column
 904            connects to the previous column, shifted by the power of
 905            the column value. If the shifted input falls off the end,
 906            then pad with zero. */
 907       for (sdx = 1 ;  sdx < nsel ;  sdx += 1) {
 908
 909             for (qdx = 0 ;  qdx < width ;  qdx += 1) {
 910                   unsigned shift = 1 << sdx;
 911                   edif_joint_t jnt0 = edif_joint_create(edf);
 912                   edif_joint_t jnt1 = (qdx >= shift)
 913                         ? edif_joint_create(edf)
 914                         : pad0;
 915
 916                   edif_add_to_joint(jnt0, table[sdx][qdx], LUT_I0);
 917                   edif_add_to_joint(jnt1, table[sdx][qdx], LUT_I1);
 918
 919                   edif_add_to_joint(jnt0, table[sdx-1][qdx], LUT_O);
 920                   if (qdx >= shift)
 921                        edif_add_to_joint(jnt1, table[sdx-1][qdx-shift], LUT_O);
 922             }
 923       }
 924
 925         /* Connect the output of the last column to the output of the
 926            SHIFTL device. */
 927       for (qdx = 0 ; qdx < width ;  qdx += 1) {
 928             ivl_nexus_t nex = ivl_lpm_q(net,qdx);
 929             edif_joint_t jnt = edif_joint_of_nexus(edf, nex);
 930
 931             edif_add_to_joint(jnt, table[nsel-1][qdx], LUT_O);
 932       }
 933
 934         /* Connect the excess select inputs to the enable inputs of
 935            the LUT4 devices in the last column. */
 936       if (nsel < ivl_lpm_selects(net)) {
 937             edif_joint_t jnt;
 938
 939               /* XXXX Only support 1 excess bit for now. */
 940             assert((nsel + 1) == ivl_lpm_selects(net));
 941
 942             jnt = edif_joint_of_nexus(edf, ivl_lpm_select(net,nsel));
 943             for (qdx = 0 ;  qdx < width ;  qdx += 1)
 944                   edif_add_to_joint(jnt, table[nsel-1][qdx], LUT_I3);
 945       }
 946
 947       free(cells);
 948       free(table);
 949 }
 950
 951
 952 /*
 953  * $Log: xilinx.c,v $
 954  * Revision 1.13  2007/02/26 19:49:50  steve
 955  *  Spelling fixes (larry doolittle)
 956  *
 957  * Revision 1.12  2004/02/15 18:03:30  steve
 958  *  Cleanup of warnings.
 959  *
 960  * Revision 1.11  2004/02/10 16:39:33  steve
 961  *  Fix direction of Q/D signals of FD devices.
 962  *
 963  * Revision 1.10  2003/08/15 02:23:53  steve
 964  *  Add synthesis support for synchronous reset.
 965  *
 966  * Revision 1.9  2003/07/04 01:08:03  steve
 967  *  PAD attribute can be used to assign pins.
 968  *
 969  * Revision 1.8  2003/07/04 00:10:09  steve
 970  *  Generate MUXF5 based 4-input N-wide muxes.
 971  *
 972  * Revision 1.7  2003/07/03 17:46:33  steve
 973  *  IOPAD support.
 974  *
 975  * Revision 1.6  2003/07/02 03:02:15  steve
 976  *  More xilinx common code.
 977  *
 978  * Revision 1.5  2003/07/02 00:25:40  steve
 979  *  Add xilinx support for bufif1.
 980  *
 981  * Revision 1.4  2003/06/28 04:18:47  steve
 982  *  Add support for wide OR/NOR gates.
 983  *
 984  * Revision 1.3  2003/06/26 03:57:05  steve
 985  *  Add Xilinx support for A/B MUX devices.
 986  *
 987  * Revision 1.2  2003/06/25 02:55:57  steve
 988  *  Virtex and Virtex2 share much code.
 989  *
 990  * Revision 1.1  2003/04/05 05:53:34  steve
 991  *  Move library cell management to common file.
 992  *
 993  */
 994