tgt-fpga/xilinx.h

   1 #ifndef __xilinx_H
   2 #define __xilinx_H
   3 /*
   4  * Copyright (c) 2003 Stephen Williams (steve at icarus.com)
   5  *
   6  *    This source code is free software; you can redistribute it
   7  *    and/or modify it in source code form under the terms of the GNU
   8  *    General Public License as published by the Free Software
   9  *    Foundation; either version 2 of the License, or (at your option)
  10  *    any later version.
  11  *
  12  *    This program is distributed in the hope that it will be useful,
  13  *    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *    GNU General Public License for more details.
  16  *
  17  *    You should have received a copy of the GNU General Public License
  18  *    along with this program; if not, write to the Free Software
  19  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  20  */
  21 #ifdef HAVE_CVS_IDENT
  22 #ident "$Id: xilinx.h,v 1.9 2007/02/26 19:49:50 steve Exp $"
  23 #endif
  24
  25 /*
  26  * This header file includes XILINX library support functions. They
  27  * manage the creation and reference of cells from the library. Use
  28  * the xilinx_cell_* functions to get an edif_cell_t from the
  29  * library. The function will create the cell in the library if
  30  * needed, or will return the existing cell if it was already called.
  31  */
  32 # include  "edif.h"
  33
  34
  35 /* === BUF Devices === */
  36
  37 /* Buffer types of devices have the BUF_O and BUF_I pin
  38    assignments. The BUF, INV, and certain specialized devices fit in
  39    this category. */
  40 extern edif_cell_t xilinx_cell_buf (edif_xlibrary_t xlib);
  41 extern edif_cell_t xilinx_cell_bufe(edif_xlibrary_t xlib);
  42 extern edif_cell_t xilinx_cell_bufg(edif_xlibrary_t xlib);
  43 extern edif_cell_t xilinx_cell_buft(edif_xlibrary_t xlib);
  44 extern edif_cell_t xilinx_cell_inv (edif_xlibrary_t xlib);
  45 extern edif_cell_t xilinx_cell_ibuf(edif_xlibrary_t xlib);
  46 extern edif_cell_t xilinx_cell_obuf(edif_xlibrary_t xlib);
  47 #define BUF_O 0
  48 #define BUF_I 1
  49   /* Only bufe and buft buffers have this input. */
  50 #define BUF_T 2
  51
  52 /* === LUT Devices === */
  53
  54 /* Most Xilinx devices have LUT2/3/4 devices that take, respectively,
  55    2, 3 or 4 inputs. All forms have a single bit output. Also, the
  56    real behavior of the device will need to be specified by an INIT
  57    parameter string. */
  58 extern edif_cell_t xilinx_cell_lut2(edif_xlibrary_t xlib);
  59 extern edif_cell_t xilinx_cell_lut3(edif_xlibrary_t xlib);
  60 extern edif_cell_t xilinx_cell_lut4(edif_xlibrary_t xlib);
  61 #define LUT_O  0
  62 #define LUT_I0 1
  63 #define LUT_I1 2
  64 #define LUT_I2 3
  65 #define LUT_I3 4
  66
  67
  68 /* === Flip-Flop Devices === */
  69
  70 /*
  71  * These are flip-flops of various sort, but similar pinouts.
  72  */
  73 extern edif_cell_t xilinx_cell_fdce(edif_xlibrary_t xlib);
  74 extern edif_cell_t xilinx_cell_fdcpe(edif_xlibrary_t xlib);
  75 extern edif_cell_t xilinx_cell_fdre(edif_xlibrary_t xlib);
  76 #define FDCE_Q   0
  77 #define FDCE_C   1
  78 #define FDCE_D   2
  79 #define FDCE_CE  3
  80 #define FDCE_CLR 4
  81 #define FDCE_PRE 5
  82
  83
  84 /* === Virtex/Virtex2 Carry Chain Logic === */
  85
  86 extern edif_cell_t xilinx_cell_mult_and(edif_xlibrary_t xlib);
  87 #define MULT_AND_LO 0
  88 #define MULT_AND_I0 1
  89 #define MULT_AND_I1 2
  90
  91 extern edif_cell_t xilinx_cell_muxcy(edif_xlibrary_t xlib);
  92 extern edif_cell_t xilinx_cell_muxcy_l(edif_xlibrary_t xlib);
  93 #define MUXCY_O  0
  94 #define MUXCY_DI 1
  95 #define MUXCY_CI 2
  96 #define MUXCY_S  3
  97
  98 extern edif_cell_t xilinx_cell_xorcy(edif_xlibrary_t xlib);
  99 #define XORCY_O  0
 100 #define XORCY_CI 1
 101 #define XORCY_LI 2
 102
 103 /* === Virtex/Virtex2 MUX devices */
 104 extern edif_cell_t xilinx_cell_muxf5(edif_xlibrary_t xlib);
 105 extern edif_cell_t xilinx_cell_muxf6(edif_xlibrary_t xlib);
 106 extern edif_cell_t xilinx_cell_muxf7(edif_xlibrary_t xlib);
 107 extern edif_cell_t xilinx_cell_muxf8(edif_xlibrary_t xlib);
 108 #define MUXF_O  0
 109 #define MUXF_I0 1
 110 #define MUXF_I1 2
 111 #define MUXF_S  3
 112
 113 /* === Inheritable Methods === */
 114
 115 extern void virtex_logic(ivl_net_logic_t net);
 116 extern void virtex_generic_dff(ivl_lpm_t net);
 117 extern void virtex_eq(ivl_lpm_t net);
 118 extern void virtex_ge(ivl_lpm_t net);
 119 extern void virtex_mux(ivl_lpm_t net);
 120 extern void virtex_add(ivl_lpm_t net);
 121
 122 extern void xilinx_common_header(ivl_design_t des);
 123 extern void xilinx_show_footer(ivl_design_t des);
 124 extern void xilinx_show_scope(ivl_scope_t scope);
 125 extern void xilinx_pad(ivl_signal_t, const char*str);
 126 extern void xilinx_logic(ivl_net_logic_t net);
 127 extern void xilinx_mux(ivl_lpm_t net);
 128 extern void xilinx_add(ivl_lpm_t net);
 129 extern void xilinx_shiftl(ivl_lpm_t net);
 130
 131 /*
 132  * $Log: xilinx.h,v $
 133  * Revision 1.9  2007/02/26 19:49:50  steve
 134  *  Spelling fixes (larry doolittle)
 135  *
 136  * Revision 1.8  2003/08/15 02:23:53  steve
 137  *  Add synthesis support for synchronous reset.
 138  *
 139  * Revision 1.7  2003/07/04 00:10:09  steve
 140  *  Generate MUXF5 based 4-input N-wide muxes.
 141  *
 142  * Revision 1.6  2003/07/02 03:02:15  steve
 143  *  More xilinx common code.
 144  *
 145  * Revision 1.5  2003/07/02 00:25:40  steve
 146  *  Add xilinx support for bufif1.
 147  *
 148  * Revision 1.4  2003/06/28 04:18:47  steve
 149  *  Add support for wide OR/NOR gates.
 150  *
 151  * Revision 1.3  2003/06/26 03:57:05  steve
 152  *  Add Xilinx support for A/B MUX devices.
 153  *
 154  * Revision 1.2  2003/06/25 02:55:57  steve
 155  *  Virtex and Virtex2 share much code.
 156  *
 157  * Revision 1.1  2003/04/05 05:53:34  steve
 158  *  Move library cell management to common file.
 159  *
 160  */
 161 #endif