PGate.h

   1 #ifndef __PGate_H
   2 #define __PGate_H
   3 /*
   4  * Copyright (c) 1998-2004 Stephen Williams (steve@icarus.com)
   5  *
   6  *    This source code is free software; you can redistribute it
   7  *    and/or modify it in source code form under the terms of the GNU
   8  *    General Public License as published by the Free Software
   9  *    Foundation; either version 2 of the License, or (at your option)
  10  *    any later version.
  11  *
  12  *    This program is distributed in the hope that it will be useful,
  13  *    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *    GNU General Public License for more details.
  16  *
  17  *    You should have received a copy of the GNU General Public License
  18  *    along with this program; if not, write to the Free Software
  19  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  20  */
  21 #ifdef HAVE_CVS_IDENT
  22 #ident "$Id: PGate.h,v 1.32 2006/04/10 00:37:42 steve Exp $"
  23 #endif
  24
  25 # include  "svector.h"
  26 # include  "StringHeap.h"
  27 # include  "named.h"
  28 # include  "LineInfo.h"
  29 # include  "PDelays.h"
  30 # include  "netlist.h"
  31 # include  <map>
  32 # include  <string>
  33 class PExpr;
  34 class PUdp;
  35 class Module;
  36
  37 /*
  38  * A PGate represents a Verilog gate. The gate has a name and other
  39  * properties, and a set of pins that connect to wires. It is known at
  40  * the time a gate is constructed how many pins the gate has.
  41  *
  42  * This pins of a gate are connected to expressions. The elaboration
  43  * step will need to convert expressions to a network of gates in
  44  * order to elaborate expression inputs, but that can easily be done.
  45  *
  46  * The PGate base class also carries the strength0 and strength1
  47  * strengths for those gates where the driver[s] can be described by a
  48  * single strength pair. There is a strength of the 0 drive, and a
  49  * strength of the 1 drive.
  50  */
  51 class PGate : public LineInfo {
  52
  53     public:
  54       enum strength_t { HIGHZ, WEAK, PULL, STRONG, SUPPLY };
  55
  56       explicit PGate(perm_string name, svector<PExpr*>*pins,
  57                      const svector<PExpr*>*del);
  58
  59       explicit PGate(perm_string name, svector<PExpr*>*pins,
  60                      PExpr*del);
  61
  62       explicit PGate(perm_string name, svector<PExpr*>*pins);
  63
  64       virtual ~PGate();
  65
  66       perm_string get_name() const { return name_; }
  67
  68         // This method evaluates the delays all the way to an
  69         // integer. If the delay is non-constant, then set the times
  70         // to 0, print an error message and mark an error to the
  71         // design.
  72       void eval_delays(Design*des, NetScope*scope,
  73                        unsigned long&rise_time,
  74                        unsigned long&fall_time,
  75                        unsigned long&decay_time) const;
  76
  77         // This evaluates the delays as far as possible, but returns
  78         // an expression, and do not signal errors.
  79       void eval_delays(Design*des, NetScope*scope,
  80                        NetExpr*&rise_time,
  81                        NetExpr*&fall_time,
  82                        NetExpr*&decay_time,
  83                        bool as_net_flag =false) const;
  84
  85       unsigned pin_count() const { return pins_? pins_->count() : 0; }
  86       const PExpr*pin(unsigned idx) const { return (*pins_)[idx]; }
  87
  88       strength_t strength0() const;
  89       strength_t strength1() const;
  90
  91       void strength0(strength_t);
  92       void strength1(strength_t);
  93
  94       map<perm_string,PExpr*> attributes;
  95
  96       virtual void dump(ostream&out, unsigned ind =4) const;
  97       virtual void elaborate(Design*des, NetScope*scope) const;
  98       virtual void elaborate_scope(Design*des, NetScope*sc) const;
  99       virtual bool elaborate_sig(Design*des, NetScope*scope) const;
 100
 101     protected:
 102       const svector<PExpr*>& get_pins() const { return *pins_; }
 103
 104       void dump_pins(ostream&out) const;
 105       void dump_delays(ostream&out) const;
 106
 107     private:
 108       perm_string name_;
 109       PDelays delay_;
 110       svector<PExpr*>*pins_;
 111
 112       strength_t str0_, str1_;
 113
 114     private: // not implemented
 115       PGate(const PGate&);
 116       PGate& operator= (const PGate&);
 117 };
 118
 119 /* A continuous assignment has a single output and a single input. The
 120    input is passed directly to the output. This is different from a
 121    BUF because elaboration may need to turn this into a vector of
 122    gates. */
 123 class PGAssign  : public PGate {
 124
 125     public:
 126       explicit PGAssign(svector<PExpr*>*pins);
 127       explicit PGAssign(svector<PExpr*>*pins, svector<PExpr*>*dels);
 128       ~PGAssign();
 129
 130       void dump(ostream&out, unsigned ind =4) const;
 131       virtual void elaborate(Design*des, NetScope*scope) const;
 132
 133     private:
 134 };
 135
 136
 137 /*
 138  * The Builtin class is specifically a gate with one of the builtin
 139  * types. The parser recognizes these types during parse. These types
 140  * have special properties that allow them to be treated specially.
 141  *
 142  * A PGBuiltin can be grouped into an array of devices. If this is
 143  * done, the msb_ and lsb_ are set to the indices of the array
 144  * range. Elaboration causes a gate to be created for each element of
 145  * the array, and a name will be generated for each gate.
 146  */
 147 class PGBuiltin  : public PGate {
 148
 149     public:
 150       enum Type { AND, NAND, OR, NOR, XOR, XNOR, BUF, BUFIF0, BUFIF1,
 151                   NOT, NOTIF0, NOTIF1, PULLDOWN, PULLUP, NMOS, RNMOS,
 152                   PMOS, RPMOS, CMOS, RCMOS, TRAN, RTRAN, TRANIF0,
 153                   TRANIF1, RTRANIF0, RTRANIF1 };
 154
 155     public:
 156       explicit PGBuiltin(Type t, perm_string name,
 157                          svector<PExpr*>*pins,
 158                          svector<PExpr*>*del);
 159       explicit PGBuiltin(Type t, perm_string name,
 160                          svector<PExpr*>*pins,
 161                          PExpr*del);
 162       ~PGBuiltin();
 163
 164       Type type() const { return type_; }
 165       void set_range(PExpr*msb, PExpr*lsb);
 166
 167       virtual void dump(ostream&out, unsigned ind =4) const;
 168       virtual void elaborate(Design*, NetScope*scope) const;
 169
 170     private:
 171       Type type_;
 172
 173       PExpr*msb_;
 174       PExpr*lsb_;
 175 };
 176
 177 /*
 178  * This kind of gate is an instantiation of a module. The stored type
 179  * is the name of a module definition somewhere in the pform. This
 180  * type also handles UDP devices, because it is generally not known at
 181  * parse time whether a name belongs to a module or a UDP.
 182  */
 183 class PGModule  : public PGate {
 184
 185     public:
 186         // The name is the *instance* name of the gate.
 187
 188         // If the binding of ports is by position, this constructor
 189         // builds everything all at once.
 190       explicit PGModule(perm_string type, perm_string name,
 191                         svector<PExpr*>*pins);
 192
 193         // If the binding of ports is by name, this constructor takes
 194         // the bindings and stores them for later elaboration.
 195       explicit PGModule(perm_string type, perm_string name,
 196                         named<PExpr*>*pins, unsigned npins);
 197
 198
 199       ~PGModule();
 200
 201         // Parameter overrides can come as an ordered list, or a set
 202         // of named expressions.
 203       void set_parameters(svector<PExpr*>*o);
 204       void set_parameters(named<PExpr*>*pa, unsigned npa);
 205
 206         // Modules can be instantiated in ranges. The parser uses this
 207         // method to pass the range to the pform.
 208       void set_range(PExpr*msb, PExpr*lsb);
 209
 210       virtual void dump(ostream&out, unsigned ind =4) const;
 211       virtual void elaborate(Design*, NetScope*scope) const;
 212       virtual void elaborate_scope(Design*des, NetScope*sc) const;
 213       virtual bool elaborate_sig(Design*des, NetScope*scope) const;
 214
 215         // This returns the module name of this module. It is a
 216         // permallocated string.
 217       perm_string get_type();
 218
 219     private:
 220       perm_string type_;
 221       svector<PExpr*>*overrides_;
 222       named<PExpr*>*pins_;
 223       unsigned npins_;
 224
 225         // These members support parameter override by name
 226       named<PExpr*>*parms_;
 227       unsigned nparms_;
 228
 229         // Arrays of modules are give if these are set.
 230       PExpr*msb_;
 231       PExpr*lsb_;
 232
 233       void elaborate_mod_(Design*, Module*mod, NetScope*scope) const;
 234       void elaborate_udp_(Design*, PUdp  *udp, NetScope*scope) const;
 235       void elaborate_scope_mod_(Design*des, Module*mod, NetScope*sc) const;
 236       bool elaborate_sig_mod_(Design*des, NetScope*scope, Module*mod) const;
 237
 238       NetNet*resize_net_to_port_(Design*des, NetScope*scope,
 239                                  NetNet*sig, unsigned port_wid,
 240                                  NetNet::PortType dir) const;
 241 };
 242
 243 #endif