Module.cc

   1 /*
   2  * Copyright (c) 1998-2000 Stephen Williams (steve@icarus.com)
   3  *
   4  *    This source code is free software; you can redistribute it
   5  *    and/or modify it in source code form under the terms of the GNU
   6  *    General Public License as published by the Free Software
   7  *    Foundation; either version 2 of the License, or (at your option)
   8  *    any later version.
   9  *
  10  *    This program is distributed in the hope that it will be useful,
  11  *    but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  *    GNU General Public License for more details.
  14  *
  15  *    You should have received a copy of the GNU General Public License
  16  *    along with this program; if not, write to the Free Software
  17  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  18  */
  19 #ifdef HAVE_CVS_IDENT
  20 #ident "$Id: Module.cc,v 1.27 2007/05/24 04:07:11 steve Exp $"
  21 #endif
  22
  23 # include "config.h"
  24
  25 # include  "Module.h"
  26 # include  "PGate.h"
  27 # include  "PWire.h"
  28 # include  <assert.h>
  29
  30 /* n is a permallocated string. */
  31 Module::Module(perm_string n)
  32 : name_(n)
  33 {
  34       library_flag = false;
  35       default_nettype = NetNet::NONE;
  36 }
  37
  38 Module::~Module()
  39 {
  40 }
  41
  42 void Module::add_gate(PGate*gate)
  43 {
  44       gates_.push_back(gate);
  45 }
  46
  47 void Module::add_task(perm_string name, PTask*task)
  48 {
  49       tasks_[name] = task;
  50 }
  51
  52 void Module::add_function(perm_string name, PFunction *func)
  53 {
  54       funcs_[name] = func;
  55 }
  56
  57 PWire* Module::add_wire(PWire*wire)
  58 {
  59       PWire*&ep = wires_[wire->path()];
  60       if (ep) return ep;
  61
  62       assert(ep == 0);
  63       ep = wire;
  64       return wire;
  65 }
  66
  67 void Module::add_behavior(PProcess*b)
  68 {
  69       behaviors_.push_back(b);
  70 }
  71
  72 unsigned Module::port_count() const
  73 {
  74       return ports.count();
  75 }
  76
  77 /*
  78  * Return the array of PEIdent object that are at this port of the
  79  * module. If the port is internally unconnected, return an empty
  80  * array.
  81  */
  82 const svector<PEIdent*>& Module::get_port(unsigned idx) const
  83 {
  84       assert(idx < ports.count());
  85       static svector<PEIdent*> zero;
  86
  87       if (ports[idx])
  88             return ports[idx]->expr;
  89       else
  90             return zero;
  91 }
  92
  93 unsigned Module::find_port(const char*name) const
  94 {
  95       assert(name != "");
  96       for (unsigned idx = 0 ;  idx < ports.count() ;  idx += 1) {
  97             if (ports[idx] == 0) {
  98                     /* It is possible to have undeclared ports. These
  99                        are ports that are skipped in the declaration,
 100                        for example like so: module foo(x ,, y); The
 101                        port between x and y is unnamed and thus
 102                        inaccessible to binding by name. */
 103                   continue;
 104             }
 105             assert(ports[idx]);
 106             if (ports[idx]->name == name)
 107                   return idx;
 108       }
 109
 110       return ports.count();
 111 }
 112
 113
 114 PWire* Module::get_wire(const pform_name_t&name) const
 115 {
 116       map<pform_name_t,PWire*>::const_iterator obj = wires_.find(name);
 117       if (obj == wires_.end())
 118             return 0;
 119       else
 120             return (*obj).second;
 121 }
 122
 123 PGate* Module::get_gate(perm_string name)
 124 {
 125       for (list<PGate*>::iterator cur = gates_.begin()
 126                  ; cur != gates_.end()
 127                  ; cur ++ ) {
 128
 129             if ((*cur)->get_name() == name)
 130                   return *cur;
 131       }
 132
 133       return 0;
 134 }
 135
 136 const list<PGate*>& Module::get_gates() const
 137 {
 138       return gates_;
 139 }
 140
 141 const list<PProcess*>& Module::get_behaviors() const
 142 {
 143       return behaviors_;
 144 }
 145
 146
 147 /*
 148  * $Log: Module.cc,v $
 149  * Revision 1.27  2007/05/24 04:07:11  steve
 150  *  Rework the heirarchical identifier parse syntax and pform
 151  *  to handle more general combinations of heirarch and bit selects.
 152  *
 153  * Revision 1.26  2007/04/19 02:52:53  steve
 154  *  Add support for -v flag in command file.
 155  *
 156  * Revision 1.25  2004/10/04 01:10:51  steve
 157  *  Clean up spurious trailing white space.
 158  *
 159  * Revision 1.24  2004/06/13 04:56:53  steve
 160  *  Add support for the default_nettype directive.
 161  *
 162  * Revision 1.23  2004/02/20 06:22:56  steve
 163  *  parameter keys are per_strings.
 164  *
 165  * Revision 1.22  2004/02/18 17:11:54  steve
 166  *  Use perm_strings for named langiage items.
 167  *
 168  * Revision 1.21  2003/04/02 03:00:14  steve
 169  *  Cope with empty module ports while binding by name.
 170  *
 171  * Revision 1.20  2003/03/06 04:37:12  steve
 172  *  lex_strings.add module names earlier.
 173  *
 174  * Revision 1.19  2002/08/12 01:34:58  steve
 175  *  conditional ident string using autoconfig.
 176  *
 177  * Revision 1.18  2002/05/19 23:37:28  steve
 178  *  Parse port_declaration_lists from the 2001 Standard.
 179  *
 180  * Revision 1.17  2001/12/03 04:47:14  steve
 181  *  Parser and pform use hierarchical names as hname_t
 182  *  objects instead of encoded strings.
 183  *
 184  * Revision 1.16  2001/10/20 05:21:51  steve
 185  *  Scope/module names are char* instead of string.
 186  *
 187  * Revision 1.15  2001/07/25 03:10:48  steve
 188  *  Create a config.h.in file to hold all the config
 189  *  junk, and support gcc 3.0. (Stephan Boettcher)
 190  *
 191  * Revision 1.14  2000/11/15 20:31:05  steve
 192  *  Fix warning about temporaries.
 193  *
 194  * Revision 1.13  2000/11/05 06:05:59  steve
 195  *  Handle connectsion to internally unconnected modules (PR#38)
 196  *
 197  * Revision 1.12  2000/05/16 04:05:15  steve
 198  *  Module ports are really special PEIdent
 199  *  expressions, because a name can be used
 200  *  many places in the port list.
 201  *
 202  * Revision 1.11  2000/03/12 17:09:40  steve
 203  *  Support localparam.
 204  *
 205  * Revision 1.10  2000/02/23 02:56:53  steve
 206  *  Macintosh compilers do not support ident.
 207  *
 208  * Revision 1.9  2000/01/09 20:37:57  steve
 209  *  Careful with wires connected to multiple ports.
 210  *
 211  * Revision 1.8  1999/12/11 05:45:41  steve
 212  *  Fix support for attaching attributes to primitive gates.
 213  *
 214  * Revision 1.7  1999/09/17 02:06:25  steve
 215  *  Handle unconnected module ports.
 216  *
 217  * Revision 1.6  1999/08/04 02:13:02  steve
 218  *  Elaborate module ports that are concatenations of
 219  *  module signals.
 220  *
 221  * Revision 1.5  1999/08/03 04:14:49  steve
 222  *  Parse into pform arbitrarily complex module
 223  *  port declarations.
 224  *
 225  * Revision 1.4  1999/07/31 19:14:47  steve
 226  *  Add functions up to elaboration (Ed Carter)
 227  *
 228  * Revision 1.3  1999/07/03 02:12:51  steve
 229  *  Elaborate user defined tasks.
 230  *
 231  * Revision 1.2  1999/06/17 05:34:42  steve
 232  *  Clean up interface of the PWire class,
 233  *  Properly match wire ranges.
 234  *
 235  * Revision 1.1  1998/11/03 23:28:51  steve
 236  *  Introduce verilog to CVS.
 237  *
 238  */
 239