PWire.h

   1 #ifndef __PWire_H
   2 #define __PWire_H
   3 /*
   4  * Copyright (c) 1998-2007 Stephen Williams (steve@icarus.com)
   5  *
   6  *    This source code is free software; you can redistribute it
   7  *    and/or modify it in source code form under the terms of the GNU
   8  *    General Public License as published by the Free Software
   9  *    Foundation; either version 2 of the License, or (at your option)
  10  *    any later version.
  11  *
  12  *    This program is distributed in the hope that it will be useful,
  13  *    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *    GNU General Public License for more details.
  16  *
  17  *    You should have received a copy of the GNU General Public License
  18  *    along with this program; if not, write to the Free Software
  19  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  20  */
  21 #ifdef HAVE_CVS_IDENT
  22 #ident "$Id: PWire.h,v 1.21 2007/05/24 04:07:11 steve Exp $"
  23 #endif
  24
  25 # include  "netlist.h"
  26 # include  "LineInfo.h"
  27 # include  <map>
  28 # include  "svector.h"
  29 # include  "StringHeap.h"
  30
  31 #ifdef HAVE_IOSFWD
  32 # include  <iosfwd>
  33 #else
  34 class ostream;
  35 #endif
  36
  37 class PExpr;
  38 class Design;
  39
  40 /*
  41  * Wires include nets, registers and ports. A net or register becomes
  42  * a port by declaration, so ports are not separate. The module
  43  * identifies a port by keeping it in its port list.
  44  *
  45  * The hname parameter to the constructor is a hierarchical name. It
  46  * is the name of the wire within a module, so does not include the
  47  * current scope or any instances. Modules contain all the wires, so
  48  * from that perspective, sub-scopes within the module are a part of
  49  * the wire name.
  50  */
  51 class PWire : public LineInfo {
  52
  53     public:
  54       PWire(const pform_name_t&hname,
  55             NetNet::Type t,
  56             NetNet::PortType pt,
  57             ivl_variable_type_t dt);
  58
  59         // Return a hierarchical name.
  60       const pform_name_t&path() const;
  61
  62       NetNet::Type get_wire_type() const;
  63       bool set_wire_type(NetNet::Type);
  64
  65       NetNet::PortType get_port_type() const;
  66       bool set_port_type(NetNet::PortType);
  67
  68       void set_signed(bool flag);
  69       bool get_signed() const;
  70       bool get_isint() const;
  71
  72       bool set_data_type(ivl_variable_type_t dt);
  73       ivl_variable_type_t get_data_type() const;
  74
  75       void set_range(PExpr*msb, PExpr*lsb);
  76
  77       void set_memory_idx(PExpr*ldx, PExpr*rdx);
  78
  79       map<perm_string,PExpr*> attributes;
  80
  81         // Write myself to the specified stream.
  82       void dump(ostream&out, unsigned ind=4) const;
  83
  84       NetNet* elaborate_sig(Design*, NetScope*scope) const;
  85
  86     private:
  87       pform_name_t hname_;
  88       NetNet::Type type_;
  89       NetNet::PortType port_type_;
  90       ivl_variable_type_t data_type_;
  91       bool signed_;
  92       bool isint_;              // original type of integer
  93
  94         // These members hold expressions for the bit width of the
  95         // wire. If they do not exist, the wire is 1 bit wide.
  96       svector<PExpr*>msb_;
  97       svector<PExpr*>lsb_;
  98
  99         // If this wire is actually a memory, these indices will give
 100         // me the size and address range of the memory.
 101       PExpr*lidx_;
 102       PExpr*ridx_;
 103
 104     private: // not implemented
 105       PWire(const PWire&);
 106       PWire& operator= (const PWire&);
 107 };
 108
 109 /*
 110  * $Log: PWire.h,v $
 111  * Revision 1.21  2007/05/24 04:07:11  steve
 112  *  Rework the heirarchical identifier parse syntax and pform
 113  *  to handle more general combinations of heirarch and bit selects.
 114  *
 115  * Revision 1.20  2007/04/26 03:06:22  steve
 116  *  Rework hname_t to use perm_strings.
 117  *
 118  * Revision 1.19  2006/04/10 00:37:42  steve
 119  *  Add support for generate loops w/ wires and gates.
 120  *
 121  * Revision 1.18  2005/07/07 16:22:49  steve
 122  *  Generalize signals to carry types.
 123  *
 124  * Revision 1.17  2004/02/20 18:53:33  steve
 125  *  Addtrbute keys are perm_strings.
 126  *
 127  * Revision 1.16  2003/01/30 16:23:07  steve
 128  *  Spelling fixes.
 129  *
 130  * Revision 1.15  2003/01/26 21:15:58  steve
 131  *  Rework expression parsing and elaboration to
 132  *  accommodate real/realtime values and expressions.
 133  *
 134  * Revision 1.14  2002/08/12 01:34:58  steve
 135  *  conditional ident string using autoconfig.
 136  *
 137  * Revision 1.13  2002/06/21 04:59:35  steve
 138  *  Carry integerness throughout the compilation.
 139  *
 140  * Revision 1.12  2002/05/23 03:08:51  steve
 141  *  Add language support for Verilog-2001 attribute
 142  *  syntax. Hook this support into existing $attribute
 143  *  handling, and add number and void value types.
 144  *
 145  *  Add to the ivl_target API new functions for access
 146  *  of complex attributes attached to gates.
 147  *
 148  * Revision 1.11  2001/12/03 04:47:14  steve
 149  *  Parser and pform use hierarchical names as hname_t
 150  *  objects instead of encoded strings.
 151  *
 152  * Revision 1.10  2001/01/16 02:44:18  steve
 153  *  Use the iosfwd header if available.
 154  */
 155 #endif