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[iverilog.git] / tgt-fpga / d-virtex2.c
blobb59144f917d4d265028f4912a9e11792ddc39168
1 /*
2 * Copyright (c) 2001 Stephen Williams (steve@icarus.com)
4 * This source code is free software; you can redistribute it
5 * and/or modify it in source code form under the terms of the GNU
6 * General Public License as published by the Free Software
7 * Foundation; either version 2 of the License, or (at your option)
8 * any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
19 #ifdef HAVE_CVS_IDENT
20 #ident "$Id: d-virtex2.c,v 1.20 2004/10/04 01:10:57 steve Exp $"
21 #endif
23 # include "device.h"
24 # include "fpga_priv.h"
25 # include "edif.h"
26 # include "generic.h"
27 # include "xilinx.h"
28 # include <stdlib.h>
29 # include <string.h>
30 #ifdef HAVE_MALLOC_H
31 # include <malloc.h>
32 #endif
33 # include <assert.h>
37 * This is a table of cell types that are accessible via the cellref
38 * attribute to a gate.
40 const static struct edif_xlib_celltable virtex2_celltable[] = {
41 { "BUFG", xilinx_cell_bufg },
42 { "MULT_AND", xilinx_cell_mult_and },
43 { 0, 0}
47 * The show_header function is called before any of the devices of the
48 * netlist are scanned.
50 * In this function, we look at the ports of the root module to decide
51 * if they are to be made into ports. Modules that have PAD attributes
52 * are *not* to be used as ports, they will be connected to special
53 * PAD devices instead.
55 static void virtex2_show_header(ivl_design_t des)
57 const char*part_str = 0;
59 xilinx_common_header(des);
61 xlib = edif_xlibrary_create(edf, "VIRTEX2");
62 edif_xlibrary_set_celltable(xlib, virtex2_celltable);
65 if ( (part_str = ivl_design_flag(des, "part")) && (part_str[0] != 0) ) {
66 edif_pstring(edf, "PART", part_str);
69 cell_0 = edif_xcell_create(xlib, "GND", 1);
70 edif_cell_portconfig(cell_0, 0, "GROUND", IVL_SIP_OUTPUT);
72 cell_1 = edif_xcell_create(xlib, "VCC", 1);
73 edif_cell_portconfig(cell_1, 0, "VCC", IVL_SIP_OUTPUT);
77 const struct device_s d_virtex2_edif = {
78 virtex2_show_header,
79 xilinx_show_footer,
80 xilinx_show_scope,
81 xilinx_pad,
82 virtex_logic,
83 virtex_generic_dff,
84 virtex_eq,
85 virtex_eq,
86 virtex_ge,
87 0, /* show_cmp_gt */
88 virtex_mux,
89 virtex_add,
90 virtex_add,
91 xilinx_shiftl, /* show_shiftl */
92 0 /* show_shiftr */
97 * $Log: d-virtex2.c,v $
98 * Revision 1.20 2004/10/04 01:10:57 steve
99 * Clean up spurious trailing white space.
101 * Revision 1.19 2003/11/12 03:20:14 steve
102 * devices need show_cmp_gt
104 * Revision 1.18 2003/07/04 00:10:09 steve
105 * Generate MUXF5 based 4-input N-wide muxes.
107 * Revision 1.17 2003/07/02 03:02:15 steve
108 * More xilinx common code.
110 * Revision 1.16 2003/06/28 04:18:47 steve
111 * Add support for wide OR/NOR gates.
113 * Revision 1.15 2003/06/26 03:57:05 steve
114 * Add Xilinx support for A/B MUX devices.
116 * Revision 1.14 2003/06/25 02:55:57 steve
117 * Virtex and Virtex2 share much code.
119 * Revision 1.13 2003/06/25 01:49:06 steve
120 * Spelling fixes.
122 * Revision 1.12 2003/06/25 01:46:44 steve
123 * Virtex support for NOT gates.
125 * Revision 1.11 2003/06/24 03:55:00 steve
126 * Add ivl_synthesis_cell support for virtex2.