PGate.h

   1 #ifndef __PGate_H
   2 #define __PGate_H
   3 /*
   4  * Copyright (c) 1998-2004 Stephen Williams (steve@icarus.com)
   5  *
   6  *    This source code is free software; you can redistribute it
   7  *    and/or modify it in source code form under the terms of the GNU
   8  *    General Public License as published by the Free Software
   9  *    Foundation; either version 2 of the License, or (at your option)
  10  *    any later version.
  11  *
  12  *    This program is distributed in the hope that it will be useful,
  13  *    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *    GNU General Public License for more details.
  16  *
  17  *    You should have received a copy of the GNU General Public License
  18  *    along with this program; if not, write to the Free Software
  19  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  20  */
  21 #ifdef HAVE_CVS_IDENT
  22 #ident "$Id: PGate.h,v 1.32 2006/04/10 00:37:42 steve Exp $"
  23 #endif
  24
  25 # include  "svector.h"
  26 # include  "StringHeap.h"
  27 # include  "named.h"
  28 # include  "LineInfo.h"
  29 # include  "PDelays.h"
  30 # include  <map>
  31 # include  <string>
  32 class PExpr;
  33 class PUdp;
  34 class Design;
  35 class NetScope;
  36 class Module;
  37
  38 /*
  39  * A PGate represents a Verilog gate. The gate has a name and other
  40  * properties, and a set of pins that connect to wires. It is known at
  41  * the time a gate is constructed how many pins the gate has.
  42  *
  43  * This pins of a gate are connected to expressions. The elaboration
  44  * step will need to convert expressions to a network of gates in
  45  * order to elaborate expression inputs, but that can easily be done.
  46  *
  47  * The PGate base class also carries the strength0 and strength1
  48  * strengths for those gates where the driver[s] can be described by a
  49  * single strength pair. There is a strength of the 0 drive, and a
  50  * strength of the 1 drive.
  51  */
  52 class PGate : public LineInfo {
  53
  54     public:
  55       enum strength_t { HIGHZ, WEAK, PULL, STRONG, SUPPLY };
  56
  57       explicit PGate(perm_string name, svector<PExpr*>*pins,
  58                      const svector<PExpr*>*del);
  59
  60       explicit PGate(perm_string name, svector<PExpr*>*pins,
  61                      PExpr*del);
  62
  63       explicit PGate(perm_string name, svector<PExpr*>*pins);
  64
  65       virtual ~PGate();
  66
  67       perm_string get_name() const { return name_; }
  68
  69         // This method evaluates the delays all the way to an
  70         // integer. If the delay is non-constant, then set the times
  71         // to 0, print an error message and mark an error to the
  72         // design.
  73       void eval_delays(Design*des, NetScope*scope,
  74                        unsigned long&rise_time,
  75                        unsigned long&fall_time,
  76                        unsigned long&decay_time) const;
  77
  78         // This evaluates the delays as far as possible, but returns
  79         // an expression, and do not signal errors.
  80       void eval_delays(Design*des, NetScope*scope,
  81                        NetExpr*&rise_time,
  82                        NetExpr*&fall_time,
  83                        NetExpr*&decay_time,
  84                        bool as_net_flag =false) const;
  85
  86       unsigned pin_count() const { return pins_? pins_->count() : 0; }
  87       const PExpr*pin(unsigned idx) const { return (*pins_)[idx]; }
  88
  89       strength_t strength0() const;
  90       strength_t strength1() const;
  91
  92       void strength0(strength_t);
  93       void strength1(strength_t);
  94
  95       map<perm_string,PExpr*> attributes;
  96
  97       virtual void dump(ostream&out, unsigned ind =4) const;
  98       virtual void elaborate(Design*des, NetScope*scope) const;
  99       virtual void elaborate_scope(Design*des, NetScope*sc) const;
 100       virtual bool elaborate_sig(Design*des, NetScope*scope) const;
 101
 102     protected:
 103       const svector<PExpr*>& get_pins() const { return *pins_; }
 104
 105       void dump_pins(ostream&out) const;
 106       void dump_delays(ostream&out) const;
 107
 108     private:
 109       perm_string name_;
 110       PDelays delay_;
 111       svector<PExpr*>*pins_;
 112
 113       strength_t str0_, str1_;
 114
 115     private: // not implemented
 116       PGate(const PGate&);
 117       PGate& operator= (const PGate&);
 118 };
 119
 120 /* A continuous assignment has a single output and a single input. The
 121    input is passed directly to the output. This is different from a
 122    BUF because elaboration may need to turn this into a vector of
 123    gates. */
 124 class PGAssign  : public PGate {
 125
 126     public:
 127       explicit PGAssign(svector<PExpr*>*pins);
 128       explicit PGAssign(svector<PExpr*>*pins, svector<PExpr*>*dels);
 129       ~PGAssign();
 130
 131       void dump(ostream&out, unsigned ind =4) const;
 132       virtual void elaborate(Design*des, NetScope*scope) const;
 133
 134     private:
 135 };
 136
 137
 138 /*
 139  * The Builtin class is specifically a gate with one of the builtin
 140  * types. The parser recognizes these types during parse. These types
 141  * have special properties that allow them to be treated specially.
 142  *
 143  * A PGBuiltin can be grouped into an array of devices. If this is
 144  * done, the msb_ and lsb_ are set to the indices of the array
 145  * range. Elaboration causes a gate to be created for each element of
 146  * the array, and a name will be generated for each gate.
 147  */
 148 class PGBuiltin  : public PGate {
 149
 150     public:
 151       enum Type { AND, NAND, OR, NOR, XOR, XNOR, BUF, BUFIF0, BUFIF1,
 152                   NOT, NOTIF0, NOTIF1, PULLDOWN, PULLUP, NMOS, RNMOS,
 153                   PMOS, RPMOS, CMOS, RCMOS, TRAN, RTRAN, TRANIF0,
 154                   TRANIF1, RTRANIF0, RTRANIF1 };
 155
 156     public:
 157       explicit PGBuiltin(Type t, perm_string name,
 158                          svector<PExpr*>*pins,
 159                          svector<PExpr*>*del);
 160       explicit PGBuiltin(Type t, perm_string name,
 161                          svector<PExpr*>*pins,
 162                          PExpr*del);
 163       ~PGBuiltin();
 164
 165       Type type() const { return type_; }
 166       void set_range(PExpr*msb, PExpr*lsb);
 167
 168       virtual void dump(ostream&out, unsigned ind =4) const;
 169       virtual void elaborate(Design*, NetScope*scope) const;
 170
 171     private:
 172       Type type_;
 173
 174       PExpr*msb_;
 175       PExpr*lsb_;
 176 };
 177
 178 /*
 179  * This kind of gate is an instantiation of a module. The stored type
 180  * is the name of a module definition somewhere in the pform. This
 181  * type also handles UDP devices, because it is generally not known at
 182  * parse time whether a name belongs to a module or a UDP.
 183  */
 184 class PGModule  : public PGate {
 185
 186     public:
 187         // The name is the *instance* name of the gate.
 188
 189         // If the binding of ports is by position, this constructor
 190         // builds everything all at once.
 191       explicit PGModule(perm_string type, perm_string name,
 192                         svector<PExpr*>*pins);
 193
 194         // If the binding of ports is by name, this constructor takes
 195         // the bindings and stores them for later elaboration.
 196       explicit PGModule(perm_string type, perm_string name,
 197                         named<PExpr*>*pins, unsigned npins);
 198
 199
 200       ~PGModule();
 201
 202         // Parameter overrides can come as an ordered list, or a set
 203         // of named expressions.
 204       void set_parameters(svector<PExpr*>*o);
 205       void set_parameters(named<PExpr*>*pa, unsigned npa);
 206
 207         // Modules can be instantiated in ranges. The parser uses this
 208         // method to pass the range to the pform.
 209       void set_range(PExpr*msb, PExpr*lsb);
 210
 211       virtual void dump(ostream&out, unsigned ind =4) const;
 212       virtual void elaborate(Design*, NetScope*scope) const;
 213       virtual void elaborate_scope(Design*des, NetScope*sc) const;
 214       virtual bool elaborate_sig(Design*des, NetScope*scope) const;
 215
 216         // This returns the module name of this module. It is a
 217         // permallocated string.
 218       perm_string get_type();
 219
 220     private:
 221       perm_string type_;
 222       svector<PExpr*>*overrides_;
 223       named<PExpr*>*pins_;
 224       unsigned npins_;
 225
 226         // These members support parameter override by name
 227       named<PExpr*>*parms_;
 228       unsigned nparms_;
 229
 230         // Arrays of modules are give if these are set.
 231       PExpr*msb_;
 232       PExpr*lsb_;
 233
 234       void elaborate_mod_(Design*, Module*mod, NetScope*scope) const;
 235       void elaborate_udp_(Design*, PUdp  *udp, NetScope*scope) const;
 236       void elaborate_scope_mod_(Design*des, Module*mod, NetScope*sc) const;
 237       bool elaborate_sig_mod_(Design*des, NetScope*scope, Module*mod) const;
 238 };
 239
 240 /*
 241  * $Log: PGate.h,v $
 242  * Revision 1.32  2006/04/10 00:37:42  steve
 243  *  Add support for generate loops w/ wires and gates.
 244  *
 245  * Revision 1.31  2006/01/03 05:22:14  steve
 246  *  Handle complex net node delays.
 247  *
 248  * Revision 1.30  2006/01/02 05:33:19  steve
 249  *  Node delays can be more general expressions in structural contexts.
 250  *
 251  * Revision 1.29  2004/10/04 01:10:52  steve
 252  *  Clean up spurious trailing white space.
 253  *
 254  * Revision 1.28  2004/03/08 00:47:44  steve
 255  *  primitive ports can bind bi name.
 256  *
 257  * Revision 1.27  2004/02/20 18:53:33  steve
 258  *  Addtrbute keys are perm_strings.
 259  *
 260  * Revision 1.26  2004/02/18 17:11:54  steve
 261  *  Use perm_strings for named langiage items.
 262  *
 263  * Revision 1.25  2003/03/06 04:37:12  steve
 264  *  lex_strings.add module names earlier.
 265  *
 266  * Revision 1.24  2002/08/12 01:34:58  steve
 267  *  conditional ident string using autoconfig.
 268  *
 269  * Revision 1.23  2002/05/23 03:08:51  steve
 270  *  Add language support for Verilog-2001 attribute
 271  *  syntax. Hook this support into existing $attribute
 272  *  handling, and add number and void value types.
 273  *
 274  *  Add to the ivl_target API new functions for access
 275  *  of complex attributes attached to gates.
 276  *
 277  * Revision 1.22  2001/11/22 06:20:59  steve
 278  *  Use NetScope instead of string for scope path.
 279  *
 280  * Revision 1.21  2001/10/21 00:42:47  steve
 281  *  Module types in pform are char* instead of string.
 282  *
 283  * Revision 1.20  2001/10/19 01:55:32  steve
 284  *  Method to get the type_ member
 285  *
 286  * Revision 1.19  2001/04/22 23:09:45  steve
 287  *  More UDP consolidation from Stephan Boettcher.
 288  *
 289  * Revision 1.18  2000/05/06 15:41:56  steve
 290  *  Carry assignment strength to pform.
 291  *
 292  * Revision 1.17  2000/05/02 16:27:38  steve
 293  *  Move signal elaboration to a seperate pass.
 294  *
 295  * Revision 1.16  2000/03/29 04:37:10  steve
 296  *  New and improved combinational primitives.
 297  *
 298  * Revision 1.15  2000/03/08 04:36:53  steve
 299  *  Redesign the implementation of scopes and parameters.
 300  *  I now generate the scopes and notice the parameters
 301  *  in a separate pass over the pform. Once the scopes
 302  *  are generated, I can process overrides and evalutate
 303  *  paremeters before elaboration begins.
 304  *
 305  * Revision 1.14  2000/02/23 02:56:53  steve
 306  *  Macintosh compilers do not support ident.
 307  *
 308  * Revision 1.13  2000/02/18 05:15:02  steve
 309  *  Catch module instantiation arrays.
 310  *
 311  * Revision 1.12  2000/01/09 05:50:48  steve
 312  *  Support named parameter override lists.
 313  *
 314  * Revision 1.11  1999/12/11 05:45:41  steve
 315  *  Fix support for attaching attributes to primitive gates.
 316  *
 317  * Revision 1.10  1999/09/04 19:11:46  steve
 318  *  Add support for delayed non-blocking assignments.
 319  *
 320  * Revision 1.9  1999/08/23 16:48:39  steve
 321  *  Parameter overrides support from Peter Monta
 322  *  AND and XOR support wide expressions.
 323  *
 324  * Revision 1.8  1999/08/01 21:18:55  steve
 325  *  elaborate rise/fall/decay for continuous assign.
 326  *
 327  * Revision 1.7  1999/08/01 16:34:50  steve
 328  *  Parse and elaborate rise/fall/decay times
 329  *  for gates, and handle the rules for partial
 330  *  lists of times.
 331  *
 332  * Revision 1.6  1999/05/29 02:36:17  steve
 333  *  module parameter bind by name.
 334  *
 335  * Revision 1.5  1999/05/10 00:16:58  steve
 336  *  Parse and elaborate the concatenate operator
 337  *  in structural contexts, Replace vector<PExpr*>
 338  *  and list<PExpr*> with svector<PExpr*>, evaluate
 339  *  constant expressions with parameters, handle
 340  *  memories as lvalues.
 341  *
 342  *  Parse task declarations, integer types.
 343  *
 344  * Revision 1.4  1999/02/15 02:06:15  steve
 345  *  Elaborate gate ranges.
 346  *
 347  * Revision 1.3  1999/01/25 05:45:56  steve
 348  *  Add the LineInfo class to carry the source file
 349  *  location of things. PGate, Statement and PProcess.
 350  *
 351  *  elaborate handles module parameter mismatches,
 352  *  missing or incorrect lvalues for procedural
 353  *  assignment, and errors are propogated to the
 354  *  top of the elaboration call tree.
 355  *
 356  *  Attach line numbers to processes, gates and
 357  *  assignment statements.
 358  *
 359  * Revision 1.2  1998/12/01 00:42:13  steve
 360  *  Elaborate UDP devices,
 361  *  Support UDP type attributes, and
 362  *  pass those attributes to nodes that
 363  *  are instantiated by elaboration,
 364  *  Put modules into a map instead of
 365  *  a simple list.
 366  *
 367  * Revision 1.1  1998/11/03 23:28:54  steve
 368  *  Introduce verilog to CVS.
 369  *
 370  */
 371 #endif