Support for wide modulus operations.
[iverilog.git] / PUdp.h
blobea623d62bef3c71147605a14d1cdcaf59f9d3935
1 #ifndef __PUdp_H
2 #define __PUdp_H
3 /*
4 * Copyright (c) 1998-2004 Stephen Williams (steve@picturel.com)
6 * This source code is free software; you can redistribute it
7 * and/or modify it in source code form under the terms of the GNU
8 * General Public License as published by the Free Software
9 * Foundation; either version 2 of the License, or (at your option)
10 * any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
21 #ifdef HAVE_CVS_IDENT
22 #ident "$Id: PUdp.h,v 1.12 2004/03/08 00:47:44 steve Exp $"
23 #endif
25 # include <map>
26 # include "StringHeap.h"
27 # include "svector.h"
28 # include "verinum.h"
30 class PExpr;
33 * This class represents a parsed UDP. This is a much simpler object
34 * then a module or macromodule.
36 * - all ports are scalar,
37 * - pin 0 (the first port) is always output,
38 * and the remaining pins are input.
40 * Thus, the ports can be represented as an ordered list of pin names.
41 * If the output port is declared as a register in the Verilog source,
42 * then this is a sequential UDP and the sequential flag is set to true.
44 * STATE TABLE
45 * Each entry in the state table is given as a string with the same
46 * number of characters as inputs. If the UDP is sequential, a
47 * character is also included at the end of the string to represent
48 * the current output.
50 * If the UDP is sequential, the "initial" member is taken to be the
51 * initial value assigned in the source, or 'x' if none is given.
53 class PUdp {
55 public:
56 explicit PUdp(perm_string n, unsigned nports);
58 svector<string>ports;
59 unsigned find_port(const char*name);
61 bool sequential;
63 svector<string>tinput;
64 svector<char> tcurrent;
65 svector<char> toutput;
67 verinum::V initial;
69 map<string,PExpr*> attributes;
71 void dump(ostream&out) const;
73 perm_string name_;
74 private:
76 private: // Not implemented
77 PUdp(const PUdp&);
78 PUdp& operator= (const PUdp&);
82 * $Log: PUdp.h,v $
83 * Revision 1.12 2004/03/08 00:47:44 steve
84 * primitive ports can bind bi name.
86 * Revision 1.11 2004/02/18 17:11:54 steve
87 * Use perm_strings for named langiage items.
89 * Revision 1.10 2003/07/15 05:07:13 steve
90 * Move PUdp constructor into compiled file.
92 * Revision 1.9 2003/07/15 03:49:22 steve
93 * Spelling fixes.
95 * Revision 1.8 2003/01/30 16:23:07 steve
96 * Spelling fixes.
98 * Revision 1.7 2002/08/12 01:34:58 steve
99 * conditional ident string using autoconfig.
101 * Revision 1.6 2002/05/23 03:08:51 steve
102 * Add language support for Verilog-2001 attribute
103 * syntax. Hook this support into existing $attribute
104 * handling, and add number and void value types.
106 * Add to the ivl_target API new functions for access
107 * of complex attributes attached to gates.
109 * Revision 1.5 2001/04/22 23:09:45 steve
110 * More UDP consolidation from Stephan Boettcher.
112 * Revision 1.4 2000/02/23 02:56:53 steve
113 * Macintosh compilers do not support ident.
115 * Revision 1.3 1999/06/15 03:44:53 steve
116 * Get rid of the STL vector template.
118 * Revision 1.2 1998/12/01 00:42:13 steve
119 * Elaborate UDP devices,
120 * Support UDP type attributes, and
121 * pass those attributes to nodes that
122 * are instantiated by elaboration,
123 * Put modules into a map instead of
124 * a simple list.
126 * Revision 1.1 1998/11/25 02:35:53 steve
127 * Parse UDP primitives all the way to pform.
130 #endif