First effort to revive BasicBlock and Function classes and
[jitcs.git] / include / jitcs_cpu.h
blobef94ddba2919a9e955483fc8a1dbfba80f9fd057
1 //===-- jitcs_cpu.h - CPU feature detection ---------------------*- C++ -*-===//
2 //
3 // Helper object allowing the detecting of instruction set features of the
4 // host cpu.
5 // TODO: Think of a way to handle cross compilation!
6 //
7 //===----------------------------------------------------------------------===//
9 #ifndef _JITCS_CPU_H_
10 #define _JITCS_CPU_H_
12 #include "jitcs_base.h"
13 #include "jitcs_adt_bitstore.h"
15 namespace jitcs {
16 struct CPUInfo {
17 public:
18 enum ArchitectureId {
19 A_Host,
20 A_X86_32 = 0,
21 A_X86_64,
22 A_Count,
24 enum FeatId {
25 // only for 32bit x86
26 F_X86CMOV = 0, F_X86SSE, F_X86SSE2,
27 // only for 64bit x86
28 F_X86LSAHF64,
29 // all x86
30 F_X86RDTSC,
31 F_X86RDTSCP, F_X86CLFLUSH,
32 F_X86SSE3, F_X86SSSE3, F_X86SSE41, F_X86SSE42,
33 F_X86AVX, F_X86AVX2,
34 F_X86AES, F_X86PCLMULQDQ,
35 F_X86POPCNT, F_X86LZCNT,
36 F_X86BMI1, F_X86BMI2,
37 F_X86TSX, F_X86FMA3, F_X86F16C, // intel features
38 //F_MONITOR, <- only ring 0
39 F_X86CMPXCHG8B, F_X86CMPXCHG16B,
40 //F_MISALIGNEDSSE <- all avx allow unaligned access (except movapX),
41 F_X86RDRAND,
43 F_COUNT
46 public:
47 CPUInfo(ArchitectureId);
48 CPUInfo() = delete;
49 CPUInfo(const CPUInfo&) = default;
50 CPUInfo& operator =(const CPUInfo&) = default;
52 public:
53 inline uint getPrefAlign() const { return _sizeOfPreferredAlignment; }
54 inline uint getCachelineSize() const { return _sizeOfCacheline; }
55 inline uint getCoreCount() const { return _countOfLogCores; }
56 inline uint getPhysCoreCount() const { return _countOfPhysCores; }
57 inline uint getLogCoreCount() const { return _countOfLogCores; }
59 inline bool isX86() const { return (_arch == A_X86_32) || (_arch == A_X86_64); }
60 inline bool isX86_32() const { return (_arch == A_X86_32); }
61 inline bool isX86_64() const { return (_arch == A_X86_64); }
63 inline bool hasX86CMOV() const { return _testFeat(F_X86CMOV); }
64 inline bool hasX86SSE() const { return _testFeat(F_X86SSE); }
65 inline bool hasX86SSE2() const { return _testFeat(F_X86SSE2); }
66 inline bool hasX86LSAHF() const { return _testFeat(F_X86LSAHF64); }
67 inline bool hasX86SSE3() const { return _testFeat(F_X86SSE3); }
68 inline bool hasX86SSSE3() const { return _testFeat(F_X86SSSE3); }
69 inline bool hasX86SSE41() const { return _testFeat(F_X86SSE41); }
70 inline bool hasX86SSE42() const { return _testFeat(F_X86SSE42); }
71 inline bool hasX86AVX() const { return _testFeat(F_X86AVX); }
72 inline bool hasX86AVX2() const { return _testFeat(F_X86AVX2); }
73 inline bool hasX86FMA3() const { return _testFeat(F_X86FMA3); }
74 inline bool hasX86F16C() const { return _testFeat(F_X86F16C); }
75 inline bool hasX86AES() const { return _testFeat(F_X86AES); }
76 inline bool hasX86PCLMULQDQ()const { return _testFeat(F_X86PCLMULQDQ); }
77 inline bool hasX86POPCNT() const { return _testFeat(F_X86POPCNT); }
78 inline bool hasX86LZCNT() const { return _testFeat(F_X86LZCNT); }
79 inline bool hasX86BMI1() const { return _testFeat(F_X86BMI1); }
80 inline bool hasX86BMI2() const { return _testFeat(F_X86BMI2); }
81 inline bool hasX86TSX() const { return _testFeat(F_X86TSX); }
82 inline bool hasX86RDTSC() const { return _testFeat(F_X86RDTSC); }
83 inline bool hasX86RDTSCP() const { return _testFeat(F_X86RDTSCP); }
84 inline bool hasX86CLFLUSH()const { return _testFeat(F_X86CLFLUSH); }
85 inline bool hasX86CMPXCHG8B()const { return _testFeat(F_X86CMPXCHG8B); }
86 inline bool hasX86CMPXCHG16B()const { return _testFeat(F_X86CMPXCHG16B); }
87 inline bool hasX86RDRAND() const { return _testFeat(F_X86RDRAND); }
89 public:
90 static const CPUInfo& GetHost() { return _hostCPUInfo; }
92 void enableFeat(FeatId f);
93 void disableFeat(FeatId f);
94 void setPreferredAlignment(uint);
95 void setCachelineSize(uint);
96 void setCoreCount(uint phys, uint log);
98 private:
99 inline bool _testFeat(FeatId f) const { return _setOfFeats.testBit(f); }
100 void _initializeFromHost();
101 void _setFeat(FeatId f, bool b);
103 private:
104 ArchitectureId _arch;
105 BitStore<F_COUNT> _setOfFeats;
106 unsigned _sizeOfPreferredAlignment;
107 unsigned _sizeOfCacheline;
108 unsigned _countOfPhysCores, _countOfLogCores;
109 static CPUInfo _hostCPUInfo;
112 } // end namespace jitcs
114 #endif
115 // _JITCS_CPU_H_