src/jitcs_int_machine.h

   1 //===-- jitcs_machine.h - Machine info --------------------------*- C++ -*-===//
   2 //
   3 // IMachineInfo holds the complete state necessary for the compiler component
   4 // to handle machine instructions for a particular machine. Particular
   5 // architectures (e.g. x86) are defined in different header files and will fill
   6 // in all fields with the relevant values.
   7 //
   8 //===----------------------------------------------------------------------===//
   9
  10 #ifndef _JITCS_INT_MACHINE_H_
  11 #define _JITCS_INT_MACHINE_H_
  12
  13 #include "jitcs_adt_ref.h"
  14 #include "jitcs_adt_refcounter.h"
  15 #include "jitcs_adt_slice.h"
  16 #include "jitcs_base.h"
  17 #include "jitcs_cpu.h"
  18 #include "jitcs_machine.h"
  19 #include "jitcs_ids.h"
  20 #include <memory>
  21
  22 namespace jitcs {
  23 struct Instruction;
  24 struct VirtualRegister;
  25 //class BBlock;
  26 //struct CCInfo;
  27 class BasicBlockImpl;
  28 class CallingConvention;
  29 class CodeGenerator;
  30 class Function;
  31 class IDumper;
  32 class TempAllocator;
  33 class SetupBlockResourceInfo;
  34
  35 class IMachineDetails {
  36 protected:
  37   IMachineDetails() = default;
  38   virtual ~IMachineDetails() = default;
  39 private:
  40   IMachineDetails(const IMachineDetails&) = delete;
  41   IMachineDetails& operator =(const IMachineDetails&) = delete;
  42 public:
  43   virtual Ref<const VirtualRegister> stackFrameRegister() const = 0;
  44
  45   virtual ResId getResOfReg(RegId r) const = 0;
  46   virtual RegClassId getRegClassOfReg(RegId r) const = 0;
  47   virtual ResClassId getResClassOfReg(RegId r) const = 0;
  48   //
  49   virtual RegClassId getRegClassCount() const = 0;
  50   virtual ResClassId getResClassOfRegClass(RegClassId rc) const = 0;
  51   virtual u32 getLogSizeOfRegClass(RegClassId rc) const = 0;
  52   virtual u32 getDontAllocOfRegClass(RegClassId rc) const = 0;
  53   //
  54   virtual ResId getResCount() const = 0;
  55   virtual ResClassId getResClassOfRes(ResId r) const = 0;
  56   virtual RegId getRegIdForRes(RegClassId rc, ResId res) const = 0;
  57   //
  58   virtual ResClassId getResClassCount() const = 0;
  59   virtual u32 getResIndexOfResClass(ResClassId r) const = 0;
  60
  61   //
  62   virtual size_t getInsIdInfo(InsId) const;
  63
  64   virtual void buildCtrlFlow(Ref<Instruction> ins, Ref<BasicBlockImpl> src) const;
  65
  66   virtual void extractDefUse(Slice<const Instruction*> insns,
  67                              Ref<const BasicBlockImpl> bb,
  68                              SetupBlockResourceInfo& dfh) const = 0;
  69
  70   virtual size_t estimateCodeSize(Slice<const Instruction*> insns,
  71                                   Ref<const BasicBlockImpl> bb,
  72                                   CodeGenerator& cg) const = 0;
  73   virtual Slice<u8> generateCode(Slice<u8> space,
  74                                  Slice<const Instruction*> insns,
  75                                  Ref<const BasicBlockImpl> bb,
  76                                  CodeGenerator& cg) const = 0;
  77
  78
  79   //u32 numRes;
  80   //u8 numRegClass, numResClass;
  81
  82   //virtual bool hasCtrlFlowIns(Slice<Instruction*>) = 0;
  83   //virtual bool isRetIns(Ref<Instruction>) = 0;
  84   //virtual void updateCtrlFlow(Ref<Instruction>, BBlock* src, Function& b);
  85
  86   //inline u32 GetInsNextSize(InsPtr ip, Function& b) {
  87   //inline void AnalyzePreDefUse(InsPtr ip, PreDefUseData& ud, u32 idx) {
  88   //inline void AnalyzeDefUse(InsPtr ip, DefUseData& ud, u32& idx, NextData* next) {
  89
  90   //inline void RegAlloc1P(InsPtr ip, RegAlloc1PData& ra, Function& b, NextData* next) {
  91   //inline void ReserveRegisters(BitmapRef res, bool requireSuperAlignment) {
  92   //inline void CreatePrologueAndEpilogue(PrologueEpilogueData & ped) {
  93   //inline void CreateMove(RegAlloc1PData &ra, VRegRef dest, VRegRef src) {
  94   //inline void CreateMove(RegAlloc1PData &ra, VRegRef dest, MemRef src) {
  95   //inline void CreateMove(RegAlloc1PData &ra, MemRef dest, VRegRef src) {
  96   //inline VRegRef GetRRefForRes(RegClassId rc, ResId res) {
  97   //inline ResId evm::DefUseData::reg2resV(RegId r) const { return evm::platform::GetResOfReg(r); }
  98   //inline bool IsHWReg(RegId r) { return r.id < R_HardwareLimit; }
  99   //inline bool  IsHWRes(ResId r) { return r.id < evm::platform::GetResCount(); }
 100
 101   //void DumpMem(evm::IDumper& o, evm::MemPtr mp, bool vsib);
 102 };
 103
 104 } // end namespace jitcs
 105
 106 #endif
 107 // _JITCS_INT_MACHINE_H_