drivers/net/jz_eth.h

   1 /*
   2  *  linux/drivers/net/jz_eth.h
   3  *
   4  *  Jz4730/Jz5730 On-Chip ethernet driver.
   5  *
   6  *  Copyright (C) 2005 - 2007  Ingenic Semiconductor Inc.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  */
  13 #ifndef __JZ_ETH_H__
  14 #define __JZ_ETH_H__
  15
  16 /* DMA control and status registers */
  17 #define DMA_BMR                (ETH_BASE + 0x1000) // Bus mode
  18 #define DMA_TPD                (ETH_BASE + 0x1004) // Transmit poll demand register
  19 #define DMA_RPD                (ETH_BASE + 0x1008) // Receieve poll demand register
  20 #define DMA_RRBA               (ETH_BASE + 0x100C) // Receieve descriptor base address
  21 #define DMA_TRBA               (ETH_BASE + 0x1010) // Transmit descriptor base address
  22 #define DMA_STS                (ETH_BASE + 0x1014) // Status register
  23 #define DMA_OMR                (ETH_BASE + 0x1018) // Command register
  24 #define DMA_IMR                (ETH_BASE + 0x101C)
  25 #define DMA_MFC                (ETH_BASE + 0x1020)
  26
  27 /* DMA CSR8-CSR19 reserved */
  28 #define DMA_CTA                (ETH_BASE + 0x1050)
  29 #define DMA_CRA                (ETH_BASE + 0x1054)
  30
  31 /* Mac control and status registers */
  32 #define MAC_MCR                (ETH_BASE + 0x0000)
  33 #define MAC_MAH                (ETH_BASE + 0x0004)
  34 #define MAC_MAL                (ETH_BASE + 0x0008)
  35 #define MAC_HTH                (ETH_BASE + 0x000C)
  36 #define MAC_HTL                (ETH_BASE + 0x0010)
  37 #define MAC_MIIA               (ETH_BASE + 0x0014)
  38 #define MAC_MIID               (ETH_BASE + 0x0018)
  39 #define MAC_FCR                (ETH_BASE + 0x001C)
  40 #define MAC_VTR1               (ETH_BASE + 0x0020)
  41 #define MAC_VTR2               (ETH_BASE + 0x0024)
  42
  43 /*
  44  * Bus Mode Register (DMA_BMR)
  45  */
  46 #define BMR_PBL    0x00003f00       /* Programmable Burst Length */
  47 #define BMR_DSL    0x0000007c       /* Descriptor Skip Length */
  48 #define BMR_BAR    0x00000002       /* Bus ARbitration */
  49 #define BMR_SWR    0x00000001       /* Software Reset */
  50
  51 #define PBL_0      0x00000000       /*  DMA burst length = amount in RX FIFO */
  52 #define PBL_1      0x00000100       /*  1 longword  DMA burst length */
  53 #define PBL_2      0x00000200       /*  2 longwords DMA burst length */
  54 #define PBL_4      0x00000400       /*  4 longwords DMA burst length */
  55 #define PBL_8      0x00000800       /*  8 longwords DMA burst length */
  56 #define PBL_16     0x00001000       /* 16 longwords DMA burst length */
  57 #define PBL_32     0x00002000       /* 32 longwords DMA burst length */
  58
  59 #define DSL_0      0x00000000       /*  0 longword  / descriptor */
  60 #define DSL_1      0x00000004       /*  1 longword  / descriptor */
  61 #define DSL_2      0x00000008       /*  2 longwords / descriptor */
  62 #define DSL_4      0x00000010       /*  4 longwords / descriptor */
  63 #define DSL_8      0x00000020       /*  8 longwords / descriptor */
  64 #define DSL_16     0x00000040       /* 16 longwords / descriptor */
  65 #define DSL_32     0x00000080       /* 32 longwords / descriptor */
  66
  67 /*
  68  * Status Register (DMA_STS)
  69  */
  70 #define STS_BE     0x03800000       /* Bus Error Bits */
  71 #define STS_TS     0x00700000       /* Transmit Process State */
  72 #define STS_RS     0x000e0000       /* Receive Process State */
  73
  74 #define TS_STOP    0x00000000       /* Stopped */
  75 #define TS_FTD     0x00100000       /* Running Fetch Transmit Descriptor */
  76 #define TS_WEOT    0x00200000       /* Running Wait for End Of Transmission */
  77 #define TS_QDAT    0x00300000       /* Running Queue skb data into TX FIFO */
  78 #define TS_RES     0x00400000       /* Reserved */
  79 #define TS_SPKT    0x00500000       /* Reserved */
  80 #define TS_SUSP    0x00600000       /* Suspended */
  81 #define TS_CLTD    0x00700000       /* Running Close Transmit Descriptor */
  82
  83 #define RS_STOP    0x00000000       /* Stopped */
  84 #define RS_FRD     0x00020000       /* Running Fetch Receive Descriptor */
  85 #define RS_CEOR    0x00040000       /* Running Check for End of Receive Packet */
  86 #define RS_WFRP    0x00060000       /* Running Wait for Receive Packet */
  87 #define RS_SUSP    0x00080000       /* Suspended */
  88 #define RS_CLRD    0x000a0000       /* Running Close Receive Descriptor */
  89 #define RS_FLUSH   0x000c0000       /* Running Flush RX FIFO */
  90 #define RS_QRFS    0x000e0000       /* Running Queue RX FIFO into RX Skb */
  91
  92 /*
  93  * Operation Mode Register (DMA_OMR)
  94  */
  95 #define OMR_TTM    0x00400000       /* Transmit Threshold Mode */
  96 #define OMR_SF     0x00200000       /* Store and Forward */
  97 #define OMR_TR     0x0000c000       /* Threshold Control Bits */
  98 #define OMR_ST     0x00002000       /* Start/Stop Transmission Command */
  99 #define OMR_OSF    0x00000004       /* Operate on Second Frame */
 100 #define OMR_SR     0x00000002       /* Start/Stop Receive */
 101
 102 #define TR_18      0x00000000       /* Threshold set to 18 (32) bytes */
 103 #define TR_24      0x00004000       /* Threshold set to 24 (64) bytes */
 104 #define TR_32      0x00008000       /* Threshold set to 32 (128) bytes */
 105 #define TR_40      0x0000c000       /* Threshold set to 40 (256) bytes */
 106
 107 /*
 108  * Missed Frames Counters (DMA_MFC)
 109  */
 110 //#define MFC_CNT1   0xffff0000       /* Missed Frames Counter Bits by application */
 111 #define MFC_CNT1   0x0ffe0000       /* Missed Frames Counter Bits by application */
 112 #define MFC_CNT2   0x0000ffff       /* Missed Frames Counter Bits by controller */
 113
 114 /*
 115  * Mac control  Register (MAC_MCR)
 116  */
 117 #define MCR_RA     0x80000000       /* Receive All */
 118 #define MCR_HBD    0x10000000       /* HeartBeat Disable */
 119 #define MCR_PS     0x08000000       /* Port Select */
 120 #define MCR_OWD    0x00800000       /* Receive own Disable */
 121 #define MCR_OM     0x00600000       /* Operating(loopback) Mode */
 122 #define MCR_FDX    0x00100000       /* Full Duplex Mode */
 123 #define MCR_PM     0x00080000       /* Pass All Multicast */
 124 #define MCR_PR     0x00040000       /* Promiscuous Mode */
 125 #define MCR_IF     0x00020000       /* Inverse Filtering */
 126 #define MCR_PB     0x00010000       /* Pass Bad Frames */
 127 #define MCR_HO     0x00008000       /* Hash Only Filtering Mode */
 128 #define MCR_HP     0x00002000       /* Hash/Perfect Receive Filtering Mode */
 129 #define MCR_FC     0x00001000       /* Late Collision control */
 130 #define MCR_BFD    0x00000800       /* Boardcast frame Disable */
 131 #define MCR_RED    0x00000400       /* Retry Disable */
 132 #define MCR_APS    0x00000100       /* Automatic pad stripping */
 133 #define MCR_BL     0x000000c0       /* Back off Limit */
 134 #define MCR_DC     0x00000020       /* Deferral check */
 135 #define MCR_TE     0x00000008       /* Transmitter enable */
 136 #define MCR_RE     0x00000004       /* Receiver enable */
 137
 138 #define MCR_MII_10  ( OMR_TTM | MCR_PS)
 139 #define MCR_MII_100 ( MCR_HBD | MCR_PS)
 140
 141 /* Flow control Register (MAC_FCR) */
 142 #define FCR_PT     0xffff0000       /* Pause time */
 143 #define FCR_PCF    0x00000004       /* Pass control frames */
 144 #define FCR_FCE    0x00000002       /* Flow control enable */
 145 #define FCR_FCB    0x00000001       /* Flow control busy */
 146
 147
 148 /* Constants for the interrupt mask and
 149  * interrupt status registers. (DMA_SIS and DMA_IMR)
 150  */
 151 #define DMA_INT_NI             0x00010000       // Normal interrupt summary
 152 #define DMA_INT_AI             0x00008000       // Abnormal interrupt summary
 153 #define DMA_INT_ER             0x00004000       // Early receive interrupt
 154 #define DMA_INT_FB             0x00002000       // Fatal bus error
 155 #define DMA_INT_ET             0x00000400       // Early transmit interrupt
 156 #define DMA_INT_RW             0x00000200       // Receive watchdog timeout
 157 #define DMA_INT_RS             0x00000100       // Receive stop
 158 #define DMA_INT_RU             0x00000080       // Receive buffer unavailble
 159 #define DMA_INT_RI             0x00000040       // Receive interrupt
 160 #define DMA_INT_UN             0x00000020       // Underflow
 161 #define DMA_INT_TJ             0x00000008       // Transmit jabber timeout
 162 #define DMA_INT_TU             0x00000004       // Transmit buffer unavailble
 163 #define DMA_INT_TS             0x00000002       // Transmit stop
 164 #define DMA_INT_TI             0x00000001       // Transmit interrupt
 165
 166 /*
 167  * Receive Descriptor Bit Summary
 168  */
 169 #define R_OWN      0x80000000       /* Own Bit */
 170 #define RD_FF      0x40000000       /* Filtering Fail */
 171 #define RD_FL      0x3fff0000       /* Frame Length */
 172 #define RD_ES      0x00008000       /* Error Summary */
 173 #define RD_DE      0x00004000       /* Descriptor Error */
 174 #define RD_LE      0x00001000       /* Length Error */
 175 #define RD_RF      0x00000800       /* Runt Frame */
 176 #define RD_MF      0x00000400       /* Multicast Frame */
 177 #define RD_FS      0x00000200       /* First Descriptor */
 178 #define RD_LS      0x00000100       /* Last Descriptor */
 179 #define RD_TL      0x00000080       /* Frame Too Long */
 180 #define RD_CS      0x00000040       /* Collision Seen */
 181 #define RD_FT      0x00000020       /* Frame Type */
 182 #define RD_RJ      0x00000010       /* Receive Watchdog timeout*/
 183 #define RD_RE      0x00000008       /* Report on MII Error */
 184 #define RD_DB      0x00000004       /* Dribbling Bit */
 185 #define RD_CE      0x00000002       /* CRC Error */
 186
 187 #define RD_RER     0x02000000       /* Receive End Of Ring */
 188 #define RD_RCH     0x01000000       /* Second Address Chained */
 189 #define RD_RBS2    0x003ff800       /* Buffer 2 Size */
 190 #define RD_RBS1    0x000007ff       /* Buffer 1 Size */
 191
 192 /*
 193  * Transmit Descriptor Bit Summary
 194  */
 195 #define T_OWN      0x80000000       /* Own Bit */
 196 #define TD_ES      0x00008000       /* Frame Aborted (error summary)*/
 197 #define TD_LO      0x00000800       /* Loss Of Carrier */
 198 #define TD_NC      0x00000400       /* No Carrier */
 199 #define TD_LC      0x00000200       /* Late Collision */
 200 #define TD_EC      0x00000100       /* Excessive Collisions */
 201 #define TD_HF      0x00000080       /* Heartbeat Fail */
 202 #define TD_CC      0x0000003c       /* Collision Counter */
 203 #define TD_UF      0x00000002       /* Underflow Error */
 204 #define TD_DE      0x00000001       /* Deferred */
 205
 206 #define TD_IC      0x80000000       /* Interrupt On Completion */
 207 #define TD_LS      0x40000000       /* Last Segment */
 208 #define TD_FS      0x20000000       /* First Segment */
 209 #define TD_FT1     0x10000000       /* Filtering Type */
 210 #define TD_SET     0x08000000       /* Setup Packet */
 211 #define TD_AC      0x04000000       /* Add CRC Disable */
 212 #define TD_TER     0x02000000       /* Transmit End Of Ring */
 213 #define TD_TCH     0x01000000       /* Second Address Chained */
 214 #define TD_DPD     0x00800000       /* Disabled Padding */
 215 #define TD_FT0     0x00400000       /* Filtering Type */
 216 #define TD_TBS2    0x003ff800       /* Buffer 2 Size */
 217 #define TD_TBS1    0x000007ff       /* Buffer 1 Size */
 218
 219 #define PERFECT_F  0x00000000
 220 #define HASH_F     TD_FT0
 221 #define INVERSE_F  TD_FT1
 222 #define HASH_O_F   (TD_FT1 | TD_F0)
 223
 224 /*
 225  * Constant setting
 226  */
 227
 228 #define IMR_DEFAULT    ( DMA_INT_TI | DMA_INT_RI |      \
 229                          DMA_INT_TS | DMA_INT_RS |      \
 230                          DMA_INT_TU | DMA_INT_RU |      \
 231                          DMA_INT_FB )
 232
 233 #define IMR_ENABLE     (DMA_INT_NI | DMA_INT_AI)
 234
 235 #define CRC_POLYNOMIAL_BE 0x04c11db7UL  /* Ethernet CRC, big endian */
 236 #define CRC_POLYNOMIAL_LE 0xedb88320UL  /* Ethernet CRC, little endian */
 237
 238 #define HASH_TABLE_LEN   512       /* Bits */
 239 #define HASH_BITS        0x01ff    /* 9 LS bits */
 240
 241 #define SETUP_FRAME_LEN  192       /* Bytes */
 242 #define IMPERF_PA_OFFSET 156       /* Bytes */
 243
 244 /*
 245  * Address Filtering Modes
 246  */
 247 #define PERFECT              0     /* 16 perfect physical addresses */
 248 #define HASH_PERF            1     /* 1 perfect, 512 multicast addresses */
 249 #define PERFECT_REJ          2     /* Reject 16 perfect physical addresses */
 250 #define ALL_HASH             3     /* Hashes all physical & multicast addrs */
 251
 252 #define ALL                  0     /* Clear out all the setup frame */
 253 #define PHYS_ADDR_ONLY       1     /* Update the physical address only */
 254
 255 /* MII register */
 256 #define MII_BMCR       0x00          /* MII Basic Mode Control Register */
 257 #define MII_BMSR       0x01          /* MII Basic Mode Status Register */
 258 #define MII_ID1        0x02          /* PHY Identifier Register 1 */
 259 #define MII_ID2        0x03          /* PHY Identifier Register 2 */
 260 #define MII_ANAR       0x04          /* Auto Negotiation Advertisement Register */
 261 #define MII_ANLPAR     0x05          /* Auto Negotiation Link Partner Ability */
 262 #define MII_ANER       0x06          /* Auto Negotiation Expansion */
 263 #define MII_DSCR       0x10          /* Davicom Specified Configration Register */
 264 #define MII_DSCSR      0x11          /* Davicom Specified Configration/Status Register */
 265 #define MII_10BTCSR    0x12          /* 10base-T Specified Configration/Status Register */
 266
 267
 268 #define MII_PREAMBLE 0xffffffff    /* MII Management Preamble */
 269 #define MII_TEST     0xaaaaaaaa    /* MII Test Signal */
 270 #define MII_STRD     0x06          /* Start of Frame+Op Code: use low nibble */
 271 #define MII_STWR     0x0a          /* Start of Frame+Op Code: use low nibble */
 272
 273 /*
 274  * MII Management Control Register
 275  */
 276 #define MII_CR_RST  0x8000         /* RESET the PHY chip */
 277 #define MII_CR_LPBK 0x4000         /* Loopback enable */
 278 #define MII_CR_SPD  0x2000         /* 0: 10Mb/s; 1: 100Mb/s */
 279 #define MII_CR_ASSE 0x1000         /* Auto Speed Select Enable */
 280 #define MII_CR_PD   0x0800         /* Power Down */
 281 #define MII_CR_ISOL 0x0400         /* Isolate Mode */
 282 #define MII_CR_RAN  0x0200         /* Restart Auto Negotiation */
 283 #define MII_CR_FDM  0x0100         /* Full Duplex Mode */
 284 #define MII_CR_CTE  0x0080         /* Collision Test Enable */
 285
 286 /*
 287  * MII Management Status Register
 288  */
 289 #define MII_SR_T4C  0x8000         /* 100BASE-T4 capable */
 290 #define MII_SR_TXFD 0x4000         /* 100BASE-TX Full Duplex capable */
 291 #define MII_SR_TXHD 0x2000         /* 100BASE-TX Half Duplex capable */
 292 #define MII_SR_TFD  0x1000         /* 10BASE-T Full Duplex capable */
 293 #define MII_SR_THD  0x0800         /* 10BASE-T Half Duplex capable */
 294 #define MII_SR_ASSC 0x0020         /* Auto Speed Selection Complete*/
 295 #define MII_SR_RFD  0x0010         /* Remote Fault Detected */
 296 #define MII_SR_ANC  0x0008         /* Auto Negotiation capable */
 297 #define MII_SR_LKS  0x0004         /* Link Status */
 298 #define MII_SR_JABD 0x0002         /* Jabber Detect */
 299 #define MII_SR_XC   0x0001         /* Extended Capabilities */
 300
 301 /*
 302  * MII Management Auto Negotiation Advertisement Register
 303  */
 304 #define MII_ANA_TAF  0x03e0        /* Technology Ability Field */
 305 #define MII_ANA_T4AM 0x0200        /* T4 Technology Ability Mask */
 306 #define MII_ANA_TXAM 0x0180        /* TX Technology Ability Mask */
 307 #define MII_ANA_FDAM 0x0140        /* Full Duplex Technology Ability Mask */
 308 #define MII_ANA_HDAM 0x02a0        /* Half Duplex Technology Ability Mask */
 309 #define MII_ANA_100M 0x0380        /* 100Mb Technology Ability Mask */
 310 #define MII_ANA_10M  0x0060        /* 10Mb Technology Ability Mask */
 311 #define MII_ANA_CSMA 0x0001        /* CSMA-CD Capable */
 312
 313 /*
 314  * MII Management Auto Negotiation Remote End Register
 315  */
 316 #define MII_ANLPA_NP   0x8000      /* Next Page (Enable) */
 317 #define MII_ANLPA_ACK  0x4000      /* Remote Acknowledge */
 318 #define MII_ANLPA_RF   0x2000      /* Remote Fault */
 319 #define MII_ANLPA_TAF  0x03e0      /* Technology Ability Field */
 320 #define MII_ANLPA_T4AM 0x0200      /* T4 Technology Ability Mask */
 321 #define MII_ANLPA_TXAM 0x0180      /* TX Technology Ability Mask */
 322 #define MII_ANLPA_FDAM 0x0140      /* Full Duplex Technology Ability Mask */
 323 #define MII_ANLPA_HDAM 0x02a0      /* Half Duplex Technology Ability Mask */
 324 #define MII_ANLPA_100M 0x0380      /* 100Mb Technology Ability Mask */
 325 #define MII_ANLPA_10M  0x0060      /* 10Mb Technology Ability Mask */
 326 #define MII_ANLPA_CSMA 0x0001      /* CSMA-CD Capable */
 327
 328 /*
 329  * MII Management DAVICOM Specified Configuration And Status Register
 330  */
 331 #define MII_DSCSR_100FDX       0x8000  /* 100M Full Duplex Operation Mode */
 332 #define MII_DSCSR_100HDX       0x4000  /* 100M Half Duplex Operation Mode */
 333 #define MII_DSCSR_10FDX        0x2000  /* 10M  Full Duplex Operation Mode */
 334 #define MII_DSCSR_10HDX        0x1000  /* 10M  Half Duplex Operation Mode */
 335 #define MII_DSCSR_ANMB         0x000f  /* Auto-Negotiation Monitor Bits   */
 336
 337
 338 /*
 339  * Used by IOCTL
 340  */
 341 #define READ_COMMAND            (SIOCDEVPRIVATE+4)
 342 #define WRITE_COMMAND           (SIOCDEVPRIVATE+5)
 343 #define GETDRIVERINFO           (SIOCDEVPRIVATE+6)
 344
 345 /*
 346  * Device data and structure
 347  */
 348
 349 #define ETH_TX_TIMEOUT          (6*HZ)
 350
 351 #define RX_BUF_SIZE             1536
 352
 353 #define NUM_RX_DESCS            32
 354 #define NUM_TX_DESCS            16
 355
 356 static const char *media_types[] = {
 357         "10BaseT-HD ", "10BaseT-FD ","100baseTx-HD ",
 358         "100baseTx-FD", "100baseT4", 0
 359 };
 360
 361 typedef struct {
 362         unsigned int status;
 363         unsigned int desc1;
 364         unsigned int buf1_addr;
 365         unsigned int next_addr;
 366 } jz_desc_t;
 367
 368 struct jz_eth_private {
 369         jz_desc_t tx_ring[NUM_TX_DESCS];        /* transmit descriptors */
 370         jz_desc_t rx_ring[NUM_RX_DESCS];        /* receive descriptors */
 371         dma_addr_t dma_tx_ring;                 /* bus address of tx ring */
 372         dma_addr_t dma_rx_ring;                 /* bus address of rx ring */
 373         dma_addr_t dma_rx_buf;                  /* DMA address of rx buffer  */
 374         unsigned int vaddr_rx_buf;              /* virtual address of rx buffer  */
 375
 376         unsigned int rx_head;                   /* first rx descriptor */
 377         unsigned int tx_head;                   /* first tx descriptor */
 378         unsigned int tx_tail;                   /* last unacked transmit packet */
 379         unsigned int tx_full;                   /* transmit buffers are full */
 380         struct sk_buff *tx_skb[NUM_TX_DESCS];   /* skbuffs for packets to transmit */
 381
 382         struct net_device_stats stats;
 383         spinlock_t lock;
 384
 385         int media;                              /* Media (eg TP), mode (eg 100B)*/
 386         int full_duplex;                        /* Current duplex setting. */
 387         int link_state;
 388         char phys[32];                          /* List of attached PHY devices */
 389         char valid_phy;                         /* Current linked phy-id with MAC */
 390         int mii_phy_cnt;
 391         int phy_type;                           /* 1-RTL8309,0-DVCOM */
 392         struct ethtool_cmd ecmds[32];
 393         u16 advertising;                        /* NWay media advertisement */
 394
 395         pid_t thr_pid;                          /* Link cheak thread ID   */
 396         int thread_die;
 397         struct completion thr_exited;
 398         wait_queue_head_t thr_wait;
 399
 400         struct pm_dev *pmdev;
 401 };
 402
 403 #endif /* __JZ_ETH_H__ */