board/cpu87/cpu87.c

   1 /*
   2  * (C) Copyright 2001-2005
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <ioports.h>
  26 #include <mpc8260.h>
  27 #include "cpu87.h"
  28 #include <pci.h>
  29
  30 /*
  31  * I/O Port configuration table
  32  *
  33  * if conf is 1, then that port pin will be configured at boot time
  34  * according to the five values podr/pdir/ppar/psor/pdat for that entry
  35  */
  36
  37 const iop_conf_t iop_conf_tab[4][32] = {
  38
  39     /* Port A configuration */
  40     {   /*            conf ppar psor pdir podr pdat */
  41         /* PA31 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 MII COL */
  42         /* PA30 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 MII CRS */
  43         /* PA29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC1 MII TX_ER */
  44         /* PA28 */ {   1,   1,   1,   1,   0,   0   }, /* FCC1 MII TX_EN */
  45         /* PA27 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 MII RX_DV */
  46         /* PA26 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 MII RX_ER */
  47         /* PA25 */ {   1,   0,   0,   1,   0,   0   }, /* FCC2 MII MDIO */
  48         /* PA24 */ {   1,   0,   0,   1,   0,   0   }, /* FCC2 MII MDC */
  49         /* PA23 */ {   1,   0,   0,   1,   0,   0   }, /* FCC1 MII MDIO */
  50         /* PA22 */ {   1,   0,   0,   1,   0,   0   }, /* FCC1 MII MDC */
  51         /* PA21 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 MII TxD[3] */
  52         /* PA20 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 MII TxD[2] */
  53         /* PA19 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 MII TxD[1] */
  54         /* PA18 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 MII TxD[0] */
  55         /* PA17 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RxD[0] */
  56         /* PA16 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RxD[1] */
  57         /* PA15 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RxD[2] */
  58         /* PA14 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RxD[3] */
  59         /* PA13 */ {   1,   0,   0,   1,   0,   0   }, /* FCC2 MII TXSL1 */
  60         /* PA12 */ {   1,   0,   0,   1,   0,   1   }, /* FCC2 MII TXSL0 */
  61         /* PA11 */ {   1,   0,   0,   1,   0,   0   }, /* FCC1 MII TXSL1 */
  62         /* PA10 */ {   1,   0,   0,   1,   0,   1   }, /* FCC1 MII TXSL0 */
  63         /* PA9  */ {   0,   1,   0,   1,   0,   0   }, /* SMC2 TXD */
  64         /* PA8  */ {   0,   1,   0,   0,   0,   0   }, /* SMC2 RXD */
  65         /* PA7  */ {   0,   0,   0,   0,   0,   0   }, /* PA7 */
  66         /* PA6  */ {   1,   0,   0,   1,   0,   1   }, /* FCC2 MII PAUSE */
  67         /* PA5  */ {   1,   0,   0,   1,   0,   1   }, /* FCC1 MII PAUSE */
  68         /* PA4  */ {   1,   0,   0,   1,   0,   0   }, /* FCC2 MII PWRDN */
  69         /* PA3  */ {   1,   0,   0,   1,   0,   0   }, /* FCC1 MII PWRDN */
  70         /* PA2  */ {   0,   0,   0,   0,   0,   0   }, /* PA2 */
  71         /* PA1  */ {   1,   0,   0,   0,   0,   0   }, /* FCC2 MII MDINT */
  72         /* PA0  */ {   1,   0,   0,   1,   0,   0   }  /* FCC1 MII MDINT */
  73     },
  74
  75     /* Port B configuration */
  76     {   /*            conf ppar psor pdir podr pdat */
  77         /* PB31 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TX_ER */
  78         /* PB30 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_DV */
  79         /* PB29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC2 MII TX_EN */
  80         /* PB28 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_ER */
  81         /* PB27 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII COL */
  82         /* PB26 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII CRS */
  83         /* PB25 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[3] */
  84         /* PB24 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[2] */
  85         /* PB23 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[1] */
  86         /* PB22 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[0] */
  87         /* PB21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[0] */
  88         /* PB20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[1] */
  89         /* PB19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[2] */
  90         /* PB18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[3] */
  91         /* PB17 */ {   0,   0,   0,   0,   0,   0   }, /* PB17 */
  92         /* PB16 */ {   0,   0,   0,   0,   0,   0   }, /* PB16 */
  93         /* PB15 */ {   0,   0,   0,   0,   0,   0   }, /* PB15 */
  94         /* PB14 */ {   0,   0,   0,   0,   0,   0   }, /* PB14 */
  95         /* PB13 */ {   0,   0,   0,   0,   0,   0   }, /* PB13 */
  96         /* PB12 */ {   0,   0,   0,   0,   0,   0   }, /* PB12 */
  97         /* PB11 */ {   0,   0,   0,   0,   0,   0   }, /* PB11 */
  98         /* PB10 */ {   0,   0,   0,   0,   0,   0   }, /* PB10 */
  99         /* PB9  */ {   0,   0,   0,   0,   0,   0   }, /* PB9 */
 100         /* PB8  */ {   0,   0,   0,   0,   0,   0   }, /* PB8 */
 101         /* PB7  */ {   0,   0,   0,   0,   0,   0   }, /* PB7 */
 102         /* PB6  */ {   0,   0,   0,   0,   0,   0   }, /* PB6 */
 103         /* PB5  */ {   0,   0,   0,   0,   0,   0   }, /* PB5 */
 104         /* PB4  */ {   0,   0,   0,   0,   0,   0   }, /* PB4 */
 105         /* PB3  */ {   0,   0,   0,   0,   0,   0   }, /* PB3 */
 106         /* PB2  */ {   0,   0,   0,   0,   0,   0   }, /* PB2 */
 107         /* PB1  */ {   0,   0,   0,   0,   0,   0   }, /* PB1 */
 108         /* PB0  */ {   0,   0,   0,   0,   0,   0   }  /* PB0 */
 109     },
 110
 111     /* Port C */
 112     {   /*            conf ppar psor pdir podr pdat */
 113         /* PC31 */ {   0,   0,   0,   0,   0,   0   }, /* PC31 */
 114         /* PC30 */ {   0,   0,   0,   0,   0,   0   }, /* PC30 */
 115         /* PC29 */ {   1,   0,   0,   0,   0,   0   }, /* SCC1 CTS */
 116         /* PC28 */ {   1,   0,   0,   0,   0,   0   }, /* SCC2 CTS */
 117         /* PC27 */ {   0,   0,   0,   0,   0,   0   }, /* PC27 */
 118         /* PC26 */ {   0,   0,   0,   0,   0,   0   }, /* PC26 */
 119         /* PC25 */ {   0,   0,   0,   0,   0,   0   }, /* PC25 */
 120         /* PC24 */ {   0,   0,   0,   0,   0,   0   }, /* PC24 */
 121         /* PC23 */ {   0,   0,   0,   0,   0,   0   }, /* FDC37C78 DACFD */
 122         /* PC22 */ {   0,   0,   0,   0,   0,   0   }, /* FDC37C78 DNFD */
 123         /* PC21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RX_CLK */
 124         /* PC20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII TX_CLK */
 125         /* PC19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_CLK */
 126         /* PC18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII TX_CLK */
 127         /* PC17 */ {   0,   0,   0,   0,   0,   0   }, /* PC17 */
 128         /* PC16 */ {   0,   0,   0,   0,   0,   0   }, /* PC16 */
 129         /* PC15 */ {   0,   0,   0,   0,   0,   0   }, /* PC15 */
 130         /* PC14 */ {   0,   0,   0,   0,   0,   0   }, /* PC14 */
 131         /* PC13 */ {   0,   0,   0,   0,   0,   0   }, /* PC13 */
 132         /* PC12 */ {   0,   0,   0,   0,   0,   0   }, /* PC12 */
 133         /* PC11 */ {   0,   0,   0,   0,   0,   0   }, /* PC11 */
 134         /* PC10 */ {   0,   0,   0,   0,   0,   0   }, /* PC10 */
 135         /* PC9  */ {   0,   0,   0,   0,   0,   0   }, /* FC9 */
 136         /* PC8  */ {   0,   0,   0,   0,   0,   0   }, /* PC8 */
 137         /* PC7  */ {   0,   0,   0,   0,   0,   0   }, /* PC7 */
 138         /* PC6  */ {   0,   0,   0,   0,   0,   0   }, /* PC6 */
 139         /* PC5  */ {   0,   0,   0,   0,   0,   0   }, /* PC5 */
 140         /* PC4  */ {   0,   0,   0,   0,   0,   0   }, /* PC4 */
 141         /* PC3  */ {   0,   0,   0,   0,   0,   0   }, /* PC3 */
 142         /* PC2  */ {   0,   0,   0,   0,   0,   0   }, /* PC2 */
 143         /* PC1  */ {   0,   0,   0,   0,   0,   0   }, /* PC1 */
 144         /* PC0  */ {   0,   0,   0,   0,   0,   0   }, /* FDC37C78 DRQFD */
 145     },
 146
 147     /* Port D */
 148     {   /*            conf ppar psor pdir podr pdat */
 149         /* PD31 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 RXD */
 150         /* PD30 */ {   1,   1,   1,   1,   0,   0   }, /* SCC1 TXD */
 151         /* PD29 */ {   1,   0,   0,   1,   0,   0   }, /* SCC1 RTS */
 152         /* PD28 */ {   1,   1,   0,   0,   0,   0   }, /* SCC2 RXD */
 153         /* PD27 */ {   1,   1,   0,   1,   0,   0   }, /* SCC2 TXD */
 154         /* PD26 */ {   1,   0,   0,   1,   0,   0   }, /* SCC2 RTS */
 155         /* PD25 */ {   0,   0,   0,   0,   0,   0   }, /* PD25 */
 156         /* PD24 */ {   0,   0,   0,   0,   0,   0   }, /* PD24 */
 157         /* PD23 */ {   0,   0,   0,   0,   0,   0   }, /* PD23 */
 158         /* PD22 */ {   0,   0,   0,   0,   0,   0   }, /* PD22 */
 159         /* PD21 */ {   0,   0,   0,   0,   0,   0   }, /* PD21 */
 160         /* PD20 */ {   0,   0,   0,   0,   0,   0   }, /* PD20 */
 161         /* PD19 */ {   0,   0,   0,   0,   0,   0   }, /* PD19 */
 162         /* PD18 */ {   0,   0,   0,   0,   0,   0   }, /* PD18 */
 163         /* PD17 */ {   0,   0,   0,   0,   0,   0   }, /* PD17 */
 164         /* PD16 */ {   0,   0,   0,   0,   0,   0   }, /* PD16 */
 165 #if defined(CONFIG_SOFT_I2C)
 166         /* PD15 */ {   1,   0,   0,   1,   1,   1   }, /* I2C SDA */
 167         /* PD14 */ {   1,   0,   0,   1,   1,   1   }, /* I2C SCL */
 168 #else
 169 #if defined(CONFIG_HARD_I2C)
 170         /* PD15 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SDA */
 171         /* PD14 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SCL */
 172 #else /* normal I/O port pins */
 173         /* PD15 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SDA */
 174         /* PD14 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SCL */
 175 #endif
 176 #endif
 177         /* PD13 */ {   0,   0,   0,   0,   0,   0   }, /* PD13 */
 178         /* PD12 */ {   0,   0,   0,   0,   0,   0   }, /* PD12 */
 179         /* PD11 */ {   0,   0,   0,   0,   0,   0   }, /* PD11 */
 180         /* PD10 */ {   0,   0,   0,   0,   0,   0   }, /* PD10 */
 181         /* PD9  */ {   1,   1,   0,   1,   0,   0   }, /* SMC1 TXD */
 182         /* PD8  */ {   1,   1,   0,   0,   0,   0   }, /* SMC1 RXD */
 183         /* PD7  */ {   0,   0,   0,   0,   0,   0   }, /* PD7 */
 184         /* PD6  */ {   0,   0,   0,   0,   0,   0   }, /* PD6 */
 185         /* PD5  */ {   0,   0,   0,   0,   0,   0   }, /* PD5 */
 186         /* PD4  */ {   0,   0,   0,   0,   0,   0   }, /* PD4 */
 187         /* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* PD3 */
 188         /* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* PD2 */
 189         /* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* PD1 */
 190         /* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* PD0 */
 191     }
 192 };
 193
 194 /* ------------------------------------------------------------------------- */
 195
 196 /* Check Board Identity:
 197  */
 198 int checkboard (void)
 199 {
 200         printf ("Board: CPU87 (Rev %02x)\n", CPU86_REV & 0x7f);
 201         return 0;
 202 }
 203
 204 /* ------------------------------------------------------------------------- */
 205
 206 /* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
 207  *
 208  * This routine performs standard 8260 initialization sequence
 209  * and calculates the available memory size. It may be called
 210  * several times to try different SDRAM configurations on both
 211  * 60x and local buses.
 212  */
 213 static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
 214                           ulong orx, volatile uchar * base)
 215 {
 216         volatile uchar c = 0xff;
 217         volatile uint *sdmr_ptr;
 218         volatile uint *orx_ptr;
 219         ulong maxsize, size;
 220         int i;
 221
 222         /* We must be able to test a location outsize the maximum legal size
 223          * to find out THAT we are outside; but this address still has to be
 224          * mapped by the controller. That means, that the initial mapping has
 225          * to be (at least) twice as large as the maximum expected size.
 226          */
 227         maxsize = (1 + (~orx | 0x7fff)) / 2;
 228
 229         /* Since CFG_SDRAM_BASE is always 0 (??), we assume that
 230          * we are configuring CS1 if base != 0
 231          */
 232         sdmr_ptr = &memctl->memc_psdmr;
 233         orx_ptr = &memctl->memc_or2;
 234
 235         *orx_ptr = orx;
 236
 237         /*
 238          * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
 239          *
 240          * "At system reset, initialization software must set up the
 241          *  programmable parameters in the memory controller banks registers
 242          *  (ORx, BRx, P/LSDMR). After all memory parameters are configured,
 243          *  system software should execute the following initialization sequence
 244          *  for each SDRAM device.
 245          *
 246          *  1. Issue a PRECHARGE-ALL-BANKS command
 247          *  2. Issue eight CBR REFRESH commands
 248          *  3. Issue a MODE-SET command to initialize the mode register
 249          *
 250          *  The initial commands are executed by setting P/LSDMR[OP] and
 251          *  accessing the SDRAM with a single-byte transaction."
 252          *
 253          * The appropriate BRx/ORx registers have already been set when we
 254          * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.
 255          */
 256
 257         *sdmr_ptr = sdmr | PSDMR_OP_PREA;
 258         *base = c;
 259
 260         *sdmr_ptr = sdmr | PSDMR_OP_CBRR;
 261         for (i = 0; i < 8; i++)
 262                 *base = c;
 263
 264         *sdmr_ptr = sdmr | PSDMR_OP_MRW;
 265         *(base + CFG_MRS_OFFS) = c;     /* setting MR on address lines */
 266
 267         *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
 268         *base = c;
 269
 270         size = get_ram_size((long *)base, maxsize);
 271
 272         *orx_ptr = orx | ~(size - 1);
 273
 274         return (size);
 275 }
 276
 277 long int initdram (int board_type)
 278 {
 279         volatile immap_t *immap = (immap_t *) CFG_IMMR;
 280         volatile memctl8260_t *memctl = &immap->im_memctl;
 281
 282 #ifndef CFG_RAMBOOT
 283         ulong size8, size9, size10;
 284 #endif
 285         long psize;
 286
 287         psize = 32 * 1024 * 1024;
 288
 289         memctl->memc_mptpr = CFG_MPTPR;
 290         memctl->memc_psrt = CFG_PSRT;
 291
 292 #ifndef CFG_RAMBOOT
 293         /* 60x SDRAM setup:
 294          */
 295         size8 = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL,
 296                           (uchar *) CFG_SDRAM_BASE);
 297
 298         size9 = try_init (memctl, CFG_PSDMR_9COL, CFG_OR2_9COL,
 299                           (uchar *) CFG_SDRAM_BASE);
 300
 301         size10 = try_init (memctl, CFG_PSDMR_10COL, CFG_OR2_10COL,
 302                           (uchar *) CFG_SDRAM_BASE);
 303
 304         psize = max(size8,max(size9,size10));
 305
 306         if (psize == size8) {
 307                 psize = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL,
 308                                   (uchar *) CFG_SDRAM_BASE);
 309                 printf ("(60x:8COL) ");
 310         } else if (psize == size9){
 311                 psize = try_init (memctl, CFG_PSDMR_9COL, CFG_OR2_9COL,
 312                                   (uchar *) CFG_SDRAM_BASE);
 313                 printf ("(60x:9COL) ");
 314         } else
 315                 printf ("(60x:10COL) ");
 316
 317 #endif  /* CFG_RAMBOOT */
 318
 319         icache_enable ();
 320
 321         return (psize);
 322 }
 323
 324 #if (CONFIG_COMMANDS & CFG_CMD_DOC)
 325 extern void doc_probe (ulong physadr);
 326 void doc_init (void)
 327 {
 328         doc_probe (CFG_DOC_BASE);
 329 }
 330 #endif
 331
 332 #ifdef  CONFIG_PCI
 333 struct pci_controller hose;
 334
 335 extern void pci_mpc8250_init(struct pci_controller *);
 336
 337 void pci_init_board(void)
 338 {
 339         pci_mpc8250_init(&hose);
 340 }
 341 #endif