board/exbitgen/exbitgen.c

   1 #include <asm/u-boot.h>
   2 #include <asm/processor.h>
   3 #include <common.h>
   4 #include "exbitgen.h"
   5
   6 /* ************************************************************************ */
   7 int board_early_init_f (void)
   8 /* ------------------------------------------------------------------------ --
   9  * Purpose     :
  10  * Remarks     :
  11  * Restrictions:
  12  * See also    :
  13  * Example     :
  14  * ************************************************************************ */
  15 {
  16         unsigned long i;
  17
  18    /*-------------------------------------------------------------------------+
  19    | Interrupt controller setup for the Walnut board.
  20    | Note: IRQ 0-15  405GP internally generated; active high; level sensitive
  21    |       IRQ 16    405GP internally generated; active low; level sensitive
  22    |       IRQ 17-24 RESERVED
  23    |       IRQ 25 (EXT IRQ 0) FPGA; active high; level sensitive
  24    |       IRQ 26 (EXT IRQ 1) SMI; active high; level sensitive
  25    |       IRQ 27 (EXT IRQ 2) Not Used
  26    |       IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive
  27    |       IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
  28    |       IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive
  29    |       IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive
  30    | Note for Walnut board:
  31    |       An interrupt taken for the FPGA (IRQ 25) indicates that either
  32    |       the Mouse, Keyboard, IRDA, or External Expansion caused the
  33    |       interrupt. The FPGA must be read to determine which device
  34    |       caused the interrupt. The default setting of the FPGA clears
  35    |
  36    +-------------------------------------------------------------------------*/
  37
  38         mtdcr (uicsr, 0xFFFFFFFF);      /* clear all ints */
  39         mtdcr (uicer, 0x00000000);      /* disable all ints */
  40         mtdcr (uiccr, 0x00000020);      /* set all but FPGA SMI to be non-critical */
  41         mtdcr (uicpr, 0xFFFFFF90);      /* set int polarities */
  42         mtdcr (uictr, 0x10000000);      /* set int trigger levels */
  43         mtdcr (uicvcr, 0x00000001);     /* set vect base=0,INT0 highest priority */
  44         mtdcr (uicsr, 0xFFFFFFFF);      /* clear all ints */
  45
  46         /* Perform reset of PHY connected to PPC via register in CPLD */
  47         out8 (PHY_CTRL_ADDR, 0x2e);     /* activate nRESET,FDX,F100,ANEN, enable output */
  48         for (i = 0; i < 10000000; i++) {
  49                 ;
  50         }
  51         out8 (PHY_CTRL_ADDR, 0x2f);     /* deactivate nRESET */
  52
  53         return 0;
  54 }
  55
  56
  57 /* ************************************************************************ */
  58 int checkboard (void)
  59 /* ------------------------------------------------------------------------ --
  60  * Purpose     :
  61  * Remarks     :
  62  * Restrictions:
  63  * See also    :
  64  * Example     :
  65  * ************************************************************************ */
  66 {
  67         printf ("Exbit H/W id: %d\n", in8 (HW_ID_ADDR));
  68         return (0);
  69 }
  70
  71 /* ************************************************************************ */
  72 long int initdram (int board_type)
  73 /* ------------------------------------------------------------------------ --
  74  * Purpose     : Determines size of mounted DRAM.
  75  * Remarks     : Size is determined by reading SDRAM configuration registers as
  76  *               set up by sdram_init.
  77  * Restrictions:
  78  * See also    :
  79  * Example     :
  80  * ************************************************************************ */
  81 {
  82         ulong tot_size;
  83         ulong bank_size;
  84         ulong tmp;
  85
  86         tot_size = 0;
  87
  88         mtdcr (memcfga, mem_mb0cf);
  89         tmp = mfdcr (memcfgd);
  90         if (tmp & 0x00000001) {
  91                 bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
  92                 tot_size += bank_size;
  93         }
  94
  95         mtdcr (memcfga, mem_mb1cf);
  96         tmp = mfdcr (memcfgd);
  97         if (tmp & 0x00000001) {
  98                 bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
  99                 tot_size += bank_size;
 100         }
 101
 102         mtdcr (memcfga, mem_mb2cf);
 103         tmp = mfdcr (memcfgd);
 104         if (tmp & 0x00000001) {
 105                 bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
 106                 tot_size += bank_size;
 107         }
 108
 109         mtdcr (memcfga, mem_mb3cf);
 110         tmp = mfdcr (memcfgd);
 111         if (tmp & 0x00000001) {
 112                 bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
 113                 tot_size += bank_size;
 114         }
 115
 116         return tot_size;
 117 }