board/mcc200/mcc200.c

   1 /*
   2  * (C) Copyright 2003-2006
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * (C) Copyright 2004
   6  * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27 #include <common.h>
  28 #include <mpc5xxx.h>
  29 #include <pci.h>
  30
  31 /* Two MT48LC8M32B2 for 32 MB */
  32 /* #include "mt48lc8m32b2-6-7.h" */
  33
  34 /* One MT48LC16M32S2 for 64 MB */
  35 /* #include "mt48lc16m32s2-75.h" */
  36 #if defined (CONFIG_MCC200_SDRAM)
  37 #include "mt48lc16m16a2-75.h"
  38 #else
  39 #include "mt46v16m16-75.h"
  40 #endif
  41
  42 DECLARE_GLOBAL_DATA_PTR;
  43
  44 extern flash_info_t flash_info[];       /* FLASH chips info */
  45
  46 ulong flash_get_size (ulong base, int banknum);
  47
  48 #ifndef CFG_RAMBOOT
  49 static void sdram_start (int hi_addr)
  50 {
  51         long hi_addr_bit = hi_addr ? 0x01000000 : 0;
  52
  53         /* unlock mode register */
  54         *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
  55         __asm__ volatile ("sync");
  56
  57         /* precharge all banks */
  58         *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
  59         __asm__ volatile ("sync");
  60
  61 #if SDRAM_DDR
  62         /* set mode register: extended mode */
  63         *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
  64         __asm__ volatile ("sync");
  65
  66         /* set mode register: reset DLL */
  67         *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
  68         __asm__ volatile ("sync");
  69 #endif
  70
  71         /* precharge all banks */
  72         *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
  73         __asm__ volatile ("sync");
  74
  75         /* auto refresh */
  76         *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
  77         __asm__ volatile ("sync");
  78
  79         /* set mode register */
  80         *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
  81         __asm__ volatile ("sync");
  82
  83         /* normal operation */
  84         *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
  85         __asm__ volatile ("sync");
  86
  87         udelay(10);
  88 }
  89 #endif
  90
  91 /*
  92  * ATTENTION: Although partially referenced initdram does NOT make real use
  93  *            use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
  94  *            is something else than 0x00000000.
  95  */
  96
  97 long int initdram (int board_type)
  98 {
  99         ulong dramsize = 0;
 100         ulong dramsize2 = 0;
 101 #ifndef CFG_RAMBOOT
 102         ulong test1, test2;
 103
 104         /* setup SDRAM chip selects */
 105         *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
 106         *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
 107         __asm__ volatile ("sync");
 108
 109         /* setup config registers */
 110         *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
 111         *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
 112         __asm__ volatile ("sync");
 113
 114 #if SDRAM_DDR
 115         /* set tap delay */
 116         *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
 117         __asm__ volatile ("sync");
 118 #endif
 119
 120         /* find RAM size using SDRAM CS0 only */
 121         sdram_start(0);
 122         test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
 123         sdram_start(1);
 124         test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
 125         if (test1 > test2) {
 126                 sdram_start(0);
 127                 dramsize = test1;
 128         } else {
 129                 dramsize = test2;
 130         }
 131
 132         /* memory smaller than 1MB is impossible */
 133         if (dramsize < (1 << 20)) {
 134                 dramsize = 0;
 135         }
 136
 137         /* set SDRAM CS0 size according to the amount of RAM found */
 138         if (dramsize > 0) {
 139                 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
 140         } else {
 141                 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
 142         }
 143
 144         /* let SDRAM CS1 start right after CS0 */
 145         *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
 146
 147         /* find RAM size using SDRAM CS1 only */
 148         if (!dramsize)
 149                 sdram_start(0);
 150         test2 = test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
 151         if (!dramsize) {
 152                 sdram_start(1);
 153                 test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
 154         }
 155         if (test1 > test2) {
 156                 sdram_start(0);
 157                 dramsize2 = test1;
 158         } else {
 159                 dramsize2 = test2;
 160         }
 161
 162         /* memory smaller than 1MB is impossible */
 163         if (dramsize2 < (1 << 20)) {
 164                 dramsize2 = 0;
 165         }
 166
 167         /* set SDRAM CS1 size according to the amount of RAM found */
 168         if (dramsize2 > 0) {
 169                 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
 170                         | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
 171         } else {
 172                 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
 173         }
 174
 175 #else /* CFG_RAMBOOT */
 176
 177         /* retrieve size of memory connected to SDRAM CS0 */
 178         dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
 179         if (dramsize >= 0x13) {
 180                 dramsize = (1 << (dramsize - 0x13)) << 20;
 181         } else {
 182                 dramsize = 0;
 183         }
 184
 185         /* retrieve size of memory connected to SDRAM CS1 */
 186         dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
 187         if (dramsize2 >= 0x13) {
 188                 dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
 189         } else {
 190                 dramsize2 = 0;
 191         }
 192
 193 #endif /* CFG_RAMBOOT */
 194
 195         return dramsize + dramsize2;
 196 }
 197
 198 int checkboard (void)
 199 {
 200 #if defined(CONFIG_PRS200)
 201         puts ("Board: PRS200\n");
 202 #else
 203         puts ("Board: MCC200\n");
 204 #endif
 205         return 0;
 206 }
 207
 208 int misc_init_r (void)
 209 {
 210         ulong flash_sup_end, snum;
 211
 212         /*
 213          * Adjust flash start and offset to detected values
 214          */
 215         gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
 216         gd->bd->bi_flashoffset = 0;
 217
 218         /*
 219          * Check if boot FLASH isn't max size
 220          */
 221         if (gd->bd->bi_flashsize < (0 - CFG_FLASH_BASE)) {
 222                 /* adjust mapping */
 223                 *(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START =
 224                         START_REG(gd->bd->bi_flashstart);
 225                 *(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP =
 226                         STOP_REG(gd->bd->bi_flashstart, gd->bd->bi_flashsize);
 227
 228                 /*
 229                  * Re-check to get correct base address
 230                  */
 231                 flash_get_size(gd->bd->bi_flashstart, CFG_MAX_FLASH_BANKS - 1);
 232
 233                 /*
 234                  * Re-do flash protection upon new addresses
 235                  */
 236                 flash_protect (FLAG_PROTECT_CLEAR,
 237                                gd->bd->bi_flashstart, 0xffffffff,
 238                                &flash_info[CFG_MAX_FLASH_BANKS - 1]);
 239
 240                 /* Monitor protection ON by default */
 241                 flash_protect (FLAG_PROTECT_SET,
 242                                CFG_MONITOR_BASE, CFG_MONITOR_BASE + monitor_flash_len - 1,
 243                                &flash_info[CFG_MAX_FLASH_BANKS - 1]);
 244
 245                 /* Environment protection ON by default */
 246                 flash_protect (FLAG_PROTECT_SET,
 247                                CFG_ENV_ADDR,
 248                                CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
 249                                &flash_info[CFG_MAX_FLASH_BANKS - 1]);
 250
 251                 /* Redundant environment protection ON by default */
 252                 flash_protect (FLAG_PROTECT_SET,
 253                                CFG_ENV_ADDR_REDUND,
 254                                CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1,
 255                                &flash_info[CFG_MAX_FLASH_BANKS - 1]);
 256         }
 257
 258         if (gd->bd->bi_flashsize > (32 << 20)) {
 259                 /* Unprotect the upper bank of the Flash */
 260                 *(volatile int*)MPC5XXX_CS0_CFG |= (1 << 6);
 261                 flash_protect (FLAG_PROTECT_CLEAR,
 262                                flash_info[0].start[0] + flash_info[0].size / 2,
 263                                (flash_info[0].start[0] - 1) + flash_info[0].size,
 264                                &flash_info[0]);
 265                 *(volatile int*)MPC5XXX_CS0_CFG &= ~(1 << 6);
 266                 printf ("Warning: Only 32 of 64 MB of Flash are accessible from U-Boot\n");
 267                 flash_info[0].size = 32 << 20;
 268                 for (snum = 0, flash_sup_end = gd->bd->bi_flashstart + (32<<20);
 269                         flash_info[0].start[snum] < flash_sup_end;
 270                         snum++);
 271                 flash_info[0].sector_count = snum;
 272         }
 273
 274         return (0);
 275 }
 276
 277 #ifdef  CONFIG_PCI
 278 static struct pci_controller hose;
 279
 280 extern void pci_mpc5xxx_init(struct pci_controller *);
 281
 282 void pci_init_board(void)
 283 {
 284         pci_mpc5xxx_init(&hose);
 285 }
 286 #endif
 287
 288 #if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET)
 289
 290 void init_ide_reset (void)
 291 {
 292         debug ("init_ide_reset\n");
 293
 294 }
 295
 296 void ide_set_reset (int idereset)
 297 {
 298         debug ("ide_reset(%d)\n", idereset);
 299
 300 }
 301 #endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */
 302
 303 #if (CONFIG_COMMANDS & CFG_CMD_DOC)
 304 extern void doc_probe (ulong physadr);
 305 void doc_init (void)
 306 {
 307         doc_probe (CFG_DOC_BASE);
 308 }
 309 #endif