?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
to make u-boot work for fat32 filesystem
[jz_uboot.git] / board / mpc8260ads / mpc8260ads.c
blob93550e2ad01be9730f7e4f2cd4ea51ba433afef7
1 /*
2 * (C) Copyright 2001-2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * Modified during 2001 by
6 * Advanced Communications Technologies (Australia) Pty. Ltd.
7 * Howard Walker, Tuong Vu-Dinh
8 *
9 * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com
10 * Added support for the 16M dram simm on the 8260ads boards
11 *
12 * (C) Copyright 2003-2004 Arabella Software Ltd.
13 * Yuli Barcohen <yuli@arabellasw.com>
14 * Added support for SDRAM DIMMs SPD EEPROM, MII, Ethernet PHY init.
15 *
16 * Copyright (c) 2005 MontaVista Software, Inc.
17 * Vitaly Bordug <vbordug@ru.mvista.com>
18 * Added support for PCI.
19 *
20 * See file CREDITS for list of people who contributed to this
21 * project.
22 *
23 * This program is free software; you can redistribute it and/or
24 * modify it under the terms of the GNU General Public License as
25 * published by the Free Software Foundation; either version 2 of
26 * the License, or (at your option) any later version.
27 *
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU General Public License for more details.
32 *
33 * You should have received a copy of the GNU General Public License
34 * along with this program; if not, write to the Free Software
35 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
36 * MA 02111-1307 USA
37 */
38
39 #include <common.h>
40 #include <ioports.h>
41 #include <mpc8260.h>
42 #include <asm/m8260_pci.h>
43 #include <i2c.h>
44 #include <spd.h>
45 #include <miiphy.h>
46 #ifdef CONFIG_PCI
47 #include <pci.h>
48 #endif
49
50 /*
51 * I/O Port configuration table
52 *
53 * if conf is 1, then that port pin will be configured at boot time
54 * according to the five values podr/pdir/ppar/psor/pdat for that entry
55 */
56
57 #define CFG_FCC1 (CONFIG_ETHER_INDEX == 1)
58 #define CFG_FCC2 (CONFIG_ETHER_INDEX == 2)
59 #define CFG_FCC3 (CONFIG_ETHER_INDEX == 3)
60
61 const iop_conf_t iop_conf_tab[4][32] = {
62
63 /* Port A configuration */
64 { /* conf ppar psor pdir podr pdat */
65 /* PA31 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */
66 /* PA30 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */
67 /* PA29 */ { CFG_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */
68 /* PA28 */ { CFG_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */
69 /* PA27 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */
70 /* PA26 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */
71 /* PA25 */ { 0, 0, 0, 0, 0, 0 }, /* PA25 */
72 /* PA24 */ { 0, 0, 0, 0, 0, 0 }, /* PA24 */
73 /* PA23 */ { 0, 0, 0, 0, 0, 0 }, /* PA23 */
74 /* PA22 */ { 0, 0, 0, 0, 0, 0 }, /* PA22 */
75 /* PA21 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */
76 /* PA20 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */
77 /* PA19 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */
78 /* PA18 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */
79 /* PA17 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */
80 /* PA16 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1] */
81 /* PA15 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */
82 /* PA14 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */
83 /* PA13 */ { 0, 0, 0, 0, 0, 0 }, /* PA13 */
84 /* PA12 */ { 0, 0, 0, 0, 0, 0 }, /* PA12 */
85 /* PA11 */ { 0, 0, 0, 0, 0, 0 }, /* PA11 */
86 /* PA10 */ { 0, 0, 0, 0, 0, 0 }, /* PA10 */
87 /* PA9 */ { 0, 0, 0, 0, 0, 0 }, /* PA9 */
88 /* PA8 */ { 0, 0, 0, 0, 0, 0 }, /* PA8 */
89 /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
90 /* PA6 */ { 0, 0, 0, 0, 0, 0 }, /* PA6 */
91 /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
92 /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
93 /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
94 /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
95 /* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* PA1 */
96 /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
97 },
98
99 /* Port B configuration */
100 { /* conf ppar psor pdir podr pdat */
101 /* PB31 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
102 /* PB30 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
103 /* PB29 */ { CFG_FCC2, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
104 /* PB28 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
105 /* PB27 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
106 /* PB26 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
107 /* PB25 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
108 /* PB24 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
109 /* PB23 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
110 /* PB22 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
111 /* PB21 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
112 /* PB20 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
113 /* PB19 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
114 /* PB18 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
115 /* PB17 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
116 /* PB16 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
117 /* PB15 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
118 /* PB14 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
119 /* PB13 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:COL */
120 /* PB12 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
121 /* PB11 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
122 /* PB10 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
123 /* PB9 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
124 /* PB8 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
125 /* PB7 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
126 /* PB6 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
127 /* PB5 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
128 /* PB4 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
129 /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
130 /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
131 /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
132 /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
133 },
134
135 /* Port C */
136 { /* conf ppar psor pdir podr pdat */
137 /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */
138 /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */
139 /* PC29 */ { 0, 0, 0, 0, 0, 0 }, /* PC29 */
140 /* PC28 */ { 0, 0, 0, 0, 0, 0 }, /* PC28 */
141 /* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */
142 /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */
143 /* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* PC25 */
144 /* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */
145 /* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* PC23 */
146 /* PC22 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII Tx Clock (CLK10) */
147 /* PC21 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII Rx Clock (CLK11) */
148 /* PC20 */ { 0, 0, 0, 0, 0, 0 }, /* PC20 */
149 #if CONFIG_ADSTYPE == CFG_8272ADS
150 /* PC19 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */
151 /* PC18 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */
152 /* PC17 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII Rx Clock (CLK15) */
153 /* PC16 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII Tx Clock (CLK16) */
154 #else
155 /* PC19 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII Rx Clock (CLK13) */
156 /* PC18 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII Tx Clock (CLK14) */
157 /* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* PC17 */
158 /* PC16 */ { 0, 0, 0, 0, 0, 0 }, /* PC16 */
159 #endif /* CONFIG_ADSTYPE == CFG_8272ADS */
160 /* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */
161 /* PC14 */ { 0, 0, 0, 0, 0, 0 }, /* PC14 */
162 /* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */
163 /* PC12 */ { 0, 0, 0, 0, 0, 0 }, /* PC12 */
164 /* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */
165 #if CONFIG_ADSTYPE == CFG_8272ADS
166 /* PC10 */ { 0, 0, 0, 0, 0, 0 }, /* PC10 */
167 /* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* PC9 */
168 #else
169 /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */
170 /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */
171 #endif /* CONFIG_ADSTYPE == CFG_8272ADS */
172 /* PC8 */ { 0, 0, 0, 0, 0, 0 }, /* PC8 */
173 /* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */
174 /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */
175 /* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* PC5 */
176 /* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* PC4 */
177 /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */
178 /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */
179 /* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */
180 /* PC0 */ { 0, 0, 0, 0, 0, 0 }, /* PC0 */
181 },
182
183 /* Port D */
184 { /* conf ppar psor pdir podr pdat */
185 /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 UART RxD */
186 /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 UART TxD */
187 /* PD29 */ { 0, 0, 0, 0, 0, 0 }, /* PD29 */
188 /* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */
189 /* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */
190 /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
191 /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
192 /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
193 /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
194 /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
195 /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
196 /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
197 /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
198 /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
199 /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
200 /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
201 /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
202 /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
203 /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
204 /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
205 /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
206 /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
207 /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
208 /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
209 /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
210 /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
211 /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
212 /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
213 /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
214 /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
215 /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
216 /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
217 }
218 };
219
220 void reset_phy (void)
221 {
222 vu_long *bcsr = (vu_long *)CFG_BCSR;
223
224 /* Reset the PHY */
225 #if CFG_PHY_ADDR == 0
226 bcsr[1] &= ~(FETHIEN1 | FETH1_RST);
227 udelay(2);
228 bcsr[1] |= FETH1_RST;
229 #else
230 bcsr[3] &= ~(FETHIEN2 | FETH2_RST);
231 udelay(2);
232 bcsr[3] |= FETH2_RST;
233 #endif /* CFG_PHY_ADDR == 0 */
234 udelay(1000);
235 #ifdef CONFIG_MII
236 #if CONFIG_ADSTYPE >= CFG_PQ2FADS
237 /*
238 * Do not bypass Rx/Tx (de)scrambler (fix configuration error)
239 * Enable autonegotiation.
240 */
241 bb_miiphy_write(NULL, CFG_PHY_ADDR, 16, 0x610);
242 bb_miiphy_write(NULL, CFG_PHY_ADDR, PHY_BMCR,
243 PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
244 #else
245 /*
246 * Ethernet PHY is configured (by means of configuration pins)
247 * to work at 10Mb/s only. We reconfigure it using MII
248 * to advertise all capabilities, including 100Mb/s, and
249 * restart autonegotiation.
250 */
251
252 /* Advertise all capabilities */
253 bb_miiphy_write(NULL, CFG_PHY_ADDR, PHY_ANAR, 0x01E1);
254
255 /* Do not bypass Rx/Tx (de)scrambler */
256 bb_miiphy_write(NULL, CFG_PHY_ADDR, PHY_DCR, 0x0000);
257
258 bb_miiphy_write(NULL, CFG_PHY_ADDR, PHY_BMCR,
259 PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
260 #endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */
261 #endif /* CONFIG_MII */
262 }
263
264 #ifdef CONFIG_PCI
265 typedef struct pci_ic_s {
266 unsigned long pci_int_stat;
267 unsigned long pci_int_mask;
268 }pci_ic_t;
269 #endif
270
271 int board_early_init_f (void)
272 {
273 vu_long *bcsr = (vu_long *)CFG_BCSR;
274
275 #ifdef CONFIG_PCI
276 volatile pci_ic_t* pci_ic = (pci_ic_t *) CFG_PCI_INT;
277
278 /* mask alll the PCI interrupts */
279 pci_ic->pci_int_mask |= 0xfff00000;
280 #endif
281 #if (CONFIG_CONS_INDEX == 1) || (CONFIG_KGDB_INDEX == 1)
282 bcsr[1] &= ~RS232EN_1;
283 #endif
284 #if (CONFIG_CONS_INDEX > 1) || (CONFIG_KGDB_INDEX > 1)
285 bcsr[1] &= ~RS232EN_2;
286 #endif
287
288 #if CONFIG_ADSTYPE != CFG_8260ADS /* PCI mode can be selected */
289 #if CONFIG_ADSTYPE == CFG_PQ2FADS
290 if ((bcsr[3] & BCSR_PCI_MODE) == 0) /* PCI mode selected by JP9 */
291 #endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */
292 {
293 volatile immap_t *immap = (immap_t *) CFG_IMMR;
294
295 immap->im_clkrst.car_sccr |= M826X_SCCR_PCI_MODE_EN;
296 immap->im_siu_conf.sc_siumcr =
297 (immap->im_siu_conf.sc_siumcr & ~SIUMCR_LBPC11)
298 | SIUMCR_LBPC01;
299 }
300 #endif /* CONFIG_ADSTYPE != CFG_8260ADS */
301
302 return 0;
303 }
304
305 #define ns2clk(ns) (ns / (1000000000 / CONFIG_8260_CLKIN) + 1)
306
307 long int initdram (int board_type)
308 {
309 #if CONFIG_ADSTYPE == CFG_PQ2FADS
310 long int msize = 32;
311 #elif CONFIG_ADSTYPE == CFG_8272ADS
312 long int msize = 64;
313 #else
314 long int msize = 16;
315 #endif
316
317 #ifndef CFG_RAMBOOT
318 volatile immap_t *immap = (immap_t *) CFG_IMMR;
319 volatile memctl8260_t *memctl = &immap->im_memctl;
320 volatile uchar *ramaddr, c = 0xff;
321 uint or;
322 uint psdmr;
323 uint psrt;
324
325 int i;
326
327 immap->im_siu_conf.sc_ppc_acr = 0x00000002;
328 immap->im_siu_conf.sc_ppc_alrh = 0x01267893;
329 immap->im_siu_conf.sc_tescr1 = 0x00004000;
330
331 memctl->memc_mptpr = CFG_MPTPR;
332 #ifdef CFG_LSDRAM_BASE
333 /*
334 Initialise local bus SDRAM only if the pins
335 are configured as local bus pins and not as PCI.
336 The configuration is determined by the HRCW.
337 */
338 if ((immap->im_siu_conf.sc_siumcr & SIUMCR_LBPC11) == SIUMCR_LBPC00) {
339 memctl->memc_lsrt = CFG_LSRT;
340 #if CONFIG_ADSTYPE == CFG_PQ2FADS /* CS3 */
341 memctl->memc_or3 = 0xFF803280;
342 memctl->memc_br3 = CFG_LSDRAM_BASE | 0x00001861;
343 #else /* CS4 */
344 memctl->memc_or4 = 0xFFC01480;
345 memctl->memc_br4 = CFG_LSDRAM_BASE | 0x00001861;
346 #endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */
347 memctl->memc_lsdmr = CFG_LSDMR | 0x28000000;
348 ramaddr = (uchar *) CFG_LSDRAM_BASE;
349 *ramaddr = c;
350 memctl->memc_lsdmr = CFG_LSDMR | 0x08000000;
351 for (i = 0; i < 8; i++)
352 *ramaddr = c;
353 memctl->memc_lsdmr = CFG_LSDMR | 0x18000000;
354 *ramaddr = c;
355 memctl->memc_lsdmr = CFG_LSDMR | 0x40000000;
356 }
357 #endif /* CFG_LSDRAM_BASE */
358
359 /* Init 60x bus SDRAM */
360 #ifdef CONFIG_SPD_EEPROM
361 {
362 spd_eeprom_t spd;
363 uint pbi, bsel, rowst, lsb, tmp;
364
365 i2c_read (CONFIG_SPD_ADDR, 0, 1, (uchar *) & spd, sizeof (spd));
366
367 /* Bank-based interleaving is not supported for physical bank
368 sizes greater than 128MB which is encoded as 0x20 in SPD
369 */
370 pbi = (spd.row_dens > 32) ? 1 : CONFIG_SDRAM_PBI;
371 msize = spd.nrows * (4 * spd.row_dens); /* Mixed size not supported */
372 or = ~(msize - 1) << 20; /* SDAM */
373 switch (spd.nbanks) { /* BPD */
374 case 2:
375 bsel = 1;
376 break;
377 case 4:
378 bsel = 2;
379 or |= 0x00002000;
380 break;
381 case 8:
382 bsel = 3;
383 or |= 0x00004000;
384 break;
385 }
386 lsb = 3; /* For 64-bit port, lsb is 3 bits */
387
388 if (pbi) { /* Bus partition depends on interleaving */
389 rowst = 32 - (spd.nrow_addr + spd.ncol_addr + bsel + lsb);
390 or |= (rowst << 9); /* ROWST */
391 } else {
392 rowst = 32 - (spd.nrow_addr + spd.ncol_addr + lsb);
393 or |= ((rowst * 2 - 12) << 9); /* ROWST */
394 }
395 or |= ((spd.nrow_addr - 9) << 6); /* NUMR */
396
397 psdmr = (pbi << 31); /* PBI */
398 /* Bus multiplexing parameters */
399 tmp = 32 - (lsb + spd.nrow_addr); /* Tables 10-19 and 10-20 */
400 psdmr |= ((tmp - (rowst - 5) - 13) << 24); /* SDAM */
401 psdmr |= ((tmp - 3 - 12) << 21); /* BSMA */
402
403 tmp = (31 - lsb - 10) - tmp;
404 /* Pin connected to SDA10 is (31 - lsb - 10).
405 rowst is multiplexed over (32 - (lsb + spd.nrow_addr)),
406 so (rowst + tmp) alternates with AP.
407 */
408 if (pbi) /* Table 10-7 */
409 psdmr |= ((10 - (rowst + tmp)) << 18); /* SDA10 */
410 else
411 psdmr |= ((12 - (rowst + tmp)) << 18); /* SDA10 */
412
413 /* SDRAM device-specific parameters */
414 tmp = ns2clk (70); /* Refresh recovery is not in SPD, so assume 70ns */
415 switch (tmp) { /* RFRC */
416 case 1:
417 case 2:
418 psdmr |= (1 << 15);
419 break;
420 case 3:
421 case 4:
422 case 5:
423 case 6:
424 case 7:
425 case 8:
426 psdmr |= ((tmp - 2) << 15);
427 break;
428 default:
429 psdmr |= (7 << 15);
430 }
431 psdmr |= (ns2clk (spd.trp) % 8 << 12); /* PRETOACT */
432 psdmr |= (ns2clk (spd.trcd) % 8 << 9); /* ACTTORW */
433 /* BL=0 because for 64-bit SDRAM burst length must be 4 */
434 /* LDOTOPRE ??? */
435 for (i = 0, tmp = spd.write_lat; (i < 4) && ((tmp & 1) == 0); i++)
436 tmp >>= 1;
437 switch (i) { /* WRC */
438 case 0:
439 case 1:
440 psdmr |= (1 << 4);
441 break;
442 case 2:
443 case 3:
444 psdmr |= (i << 4);
445 break;
446 }
447 /* EAMUX=0 - no external address multiplexing */
448 /* BUFCMD=0 - no external buffers */
449 for (i = 1, tmp = spd.cas_lat; (i < 3) && ((tmp & 1) == 0); i++)
450 tmp >>= 1;
451 psdmr |= i; /* CL */
452
453 switch (spd.refresh & 0x7F) {
454 case 1:
455 tmp = 3900;
456 break;
457 case 2:
458 tmp = 7800;
459 break;
460 case 3:
461 tmp = 31300;
462 break;
463 case 4:
464 tmp = 62500;
465 break;
466 case 5:
467 tmp = 125000;
468 break;
469 default:
470 tmp = 15625;
471 }
472 psrt = tmp / (1000000000 / CONFIG_8260_CLKIN *
473 ((memctl->memc_mptpr >> 8) + 1)) - 1;
474 #ifdef SPD_DEBUG
475 printf ("\nDIMM type: %-18.18s\n", spd.mpart);
476 printf ("SPD size: %d\n", spd.info_size);
477 printf ("EEPROM size: %d\n", 1 << spd.chip_size);
478 printf ("Memory type: %d\n", spd.mem_type);
479 printf ("Row addr: %d\n", spd.nrow_addr);
480 printf ("Column addr: %d\n", spd.ncol_addr);
481 printf ("# of rows: %d\n", spd.nrows);
482 printf ("Row density: %d\n", spd.row_dens);
483 printf ("# of banks: %d\n", spd.nbanks);
484 printf ("Data width: %d\n",
485 256 * spd.dataw_msb + spd.dataw_lsb);
486 printf ("Chip width: %d\n", spd.primw);
487 printf ("Refresh rate: %02X\n", spd.refresh);
488 printf ("CAS latencies: %02X\n", spd.cas_lat);
489 printf ("Write latencies: %02X\n", spd.write_lat);
490 printf ("tRP: %d\n", spd.trp);
491 printf ("tRCD: %d\n", spd.trcd);
492
493 printf ("OR=%X, PSDMR=%08X, PSRT=%0X\n", or, psdmr, psrt);
494 #endif /* SPD_DEBUG */
495 }
496 #else /* !CONFIG_SPD_EEPROM */
497 or = CFG_OR2;
498 psdmr = CFG_PSDMR;
499 psrt = CFG_PSRT;
500 #endif /* CONFIG_SPD_EEPROM */
501 memctl->memc_psrt = psrt;
502 memctl->memc_or2 = or;
503 memctl->memc_br2 = CFG_SDRAM_BASE | 0x00000041;
504 ramaddr = (uchar *) CFG_SDRAM_BASE;
505 memctl->memc_psdmr = psdmr | 0x28000000; /* Precharge all banks */
506 *ramaddr = c;
507 memctl->memc_psdmr = psdmr | 0x08000000; /* CBR refresh */
508 for (i = 0; i < 8; i++)
509 *ramaddr = c;
510
511 memctl->memc_psdmr = psdmr | 0x18000000; /* Mode Register write */
512 *ramaddr = c;
513 memctl->memc_psdmr = psdmr | 0x40000000; /* Refresh enable */
514 *ramaddr = c;
515 #endif /* CFG_RAMBOOT */
516
517 /* return total 60x bus SDRAM size */
518 return (msize * 1024 * 1024);
519 }
520
521 int checkboard (void)
522 {
523 #if CONFIG_ADSTYPE == CFG_8260ADS
524 puts ("Board: Motorola MPC8260ADS\n");
525 #elif CONFIG_ADSTYPE == CFG_8266ADS
526 puts ("Board: Motorola MPC8266ADS\n");
527 #elif CONFIG_ADSTYPE == CFG_PQ2FADS
528 puts ("Board: Motorola PQ2FADS-ZU\n");
529 #elif CONFIG_ADSTYPE == CFG_8272ADS
530 puts ("Board: Motorola MPC8272ADS\n");
531 #else
532 puts ("Board: unknown\n");
533 #endif
534 return 0;
535 }
536
537 #ifdef CONFIG_PCI
538 struct pci_controller hose;
539
540 extern void pci_mpc8250_init(struct pci_controller *);
541
542 void pci_init_board(void)
543 {
544 pci_mpc8250_init(&hose);
545 }
546 #endif
uboot for JZ soc