board/mpc8349emds/pci.c

   1 /*
   2  * See file CREDITS for list of people who contributed to this
   3  * project.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License as
   7  * published by the Free Software Foundation; either version 2 of
   8  * the License, or (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  18  * MA 02111-1307 USA
  19  *
  20  */
  21
  22 #include <asm/mmu.h>
  23 #include <common.h>
  24 #include <asm/global_data.h>
  25 #include <pci.h>
  26 #include <asm/mpc8349_pci.h>
  27 #include <i2c.h>
  28
  29 DECLARE_GLOBAL_DATA_PTR;
  30
  31 #ifdef CONFIG_PCI
  32
  33 /* System RAM mapped to PCI space */
  34 #define CONFIG_PCI_SYS_MEM_BUS  CFG_SDRAM_BASE
  35 #define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE
  36
  37 #ifndef CONFIG_PCI_PNP
  38 static struct pci_config_table pci_mpc8349emds_config_table[] = {
  39         {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
  40          PCI_IDSEL_NUMBER, PCI_ANY_ID,
  41          pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
  42                                      PCI_ENET0_MEMADDR,
  43                                      PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
  44                 }
  45         },
  46         {}
  47 };
  48 #endif
  49
  50 static struct pci_controller pci_hose[] = {
  51        {
  52 #ifndef CONFIG_PCI_PNP
  53        config_table:pci_mpc8349emds_config_table,
  54 #endif
  55        },
  56        {
  57 #ifndef CONFIG_PCI_PNP
  58        config_table:pci_mpc8349emds_config_table,
  59 #endif
  60        }
  61 };
  62
  63 /**************************************************************************
  64  *
  65  * pib_init() -- initialize the PCA9555PW IO expander on the PIB board
  66  *
  67  */
  68 void
  69 pib_init(void)
  70 {
  71         u8 val8;
  72         /*
  73          * Assign PIB PMC slot to desired PCI bus
  74          */
  75         mpc8349_i2c = (i2c_t*)(CFG_IMMRBAR + CFG_I2C2_OFFSET);
  76         i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
  77
  78         val8 = 0;
  79         i2c_write(0x23, 0x6, 1, &val8, 1);
  80         i2c_write(0x23, 0x7, 1, &val8, 1);
  81         val8 = 0xff;
  82         i2c_write(0x23, 0x2, 1, &val8, 1);
  83         i2c_write(0x23, 0x3, 1, &val8, 1);
  84
  85         val8 = 0;
  86         i2c_write(0x26, 0x6, 1, &val8, 1);
  87         val8 = 0x34;
  88         i2c_write(0x26, 0x7, 1, &val8, 1);
  89 #if defined(PCI_64BIT)
  90         val8 = 0xf4;    /* PMC2:PCI1/64-bit */
  91 #elif defined(PCI_ALL_PCI1)
  92         val8 = 0xf3;    /* PMC1:PCI1 PMC2:PCI1 PMC3:PCI1 */
  93 #elif defined(PCI_ONE_PCI1)
  94         val8 = 0xf9;    /* PMC1:PCI1 PMC2:PCI2 PMC3:PCI2 */
  95 #else
  96         val8 = 0xf5;    /* PMC1:PCI1 PMC2:PCI1 PMC3:PCI2 */
  97 #endif
  98         i2c_write(0x26, 0x2, 1, &val8, 1);
  99         val8 = 0xff;
 100         i2c_write(0x26, 0x3, 1, &val8, 1);
 101         val8 = 0;
 102         i2c_write(0x27, 0x6, 1, &val8, 1);
 103         i2c_write(0x27, 0x7, 1, &val8, 1);
 104         val8 = 0xff;
 105         i2c_write(0x27, 0x2, 1, &val8, 1);
 106         val8 = 0xef;
 107         i2c_write(0x27, 0x3, 1, &val8, 1);
 108         asm("eieio");
 109
 110 #if defined(PCI_64BIT)
 111         printf("PCI1: 64-bit on PMC2\n");
 112 #elif defined(PCI_ALL_PCI1)
 113         printf("PCI1: 32-bit on PMC1, PMC2, PMC3\n");
 114 #elif defined(PCI_ONE_PCI1)
 115         printf("PCI1: 32-bit on PMC1\n");
 116         printf("PCI2: 32-bit on PMC2, PMC3\n");
 117 #else
 118         printf("PCI1: 32-bit on PMC1, PMC2\n");
 119         printf("PCI2: 32-bit on PMC3\n");
 120 #endif
 121 }
 122
 123 /**************************************************************************
 124  * pci_init_board()
 125  *
 126  * NOTICE: PCI2 is not currently supported
 127  *
 128  */
 129 void
 130 pci_init_board(void)
 131 {
 132         volatile immap_t *      immr;
 133         volatile clk8349_t *    clk;
 134         volatile law8349_t *    pci_law;
 135         volatile pot8349_t *    pci_pot;
 136         volatile pcictrl8349_t *        pci_ctrl;
 137         volatile pciconf8349_t *        pci_conf;
 138         u16 reg16;
 139         u32 reg32;
 140         u32 dev;
 141         struct  pci_controller * hose;
 142
 143         immr = (immap_t *)CFG_IMMRBAR;
 144         clk = (clk8349_t *)&immr->clk;
 145         pci_law = immr->sysconf.pcilaw;
 146         pci_pot = immr->ios.pot;
 147         pci_ctrl = immr->pci_ctrl;
 148         pci_conf = immr->pci_conf;
 149
 150         hose = &pci_hose[0];
 151
 152         pib_init();
 153
 154         /*
 155          * Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode
 156          */
 157
 158         reg32 = clk->occr;
 159         udelay(2000);
 160         clk->occr = 0xff000000;
 161         udelay(2000);
 162
 163         /*
 164          * Release PCI RST Output signal
 165          */
 166         pci_ctrl[0].gcr = 0;
 167         udelay(2000);
 168         pci_ctrl[0].gcr = 1;
 169
 170 #ifdef CONFIG_MPC83XX_PCI2
 171         pci_ctrl[1].gcr = 0;
 172         udelay(2000);
 173         pci_ctrl[1].gcr = 1;
 174 #endif
 175
 176         /* We need to wait at least a 1sec based on PCI specs */
 177         {
 178                 int i;
 179
 180                 for (i = 0; i < 1000; ++i)
 181                         udelay (1000);
 182         }
 183
 184         /*
 185          * Configure PCI Local Access Windows
 186          */
 187         pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR;
 188         pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
 189
 190         pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR;
 191         pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
 192
 193         /*
 194          * Configure PCI Outbound Translation Windows
 195          */
 196
 197         /* PCI1 mem space - prefetch */
 198         pci_pot[0].potar = (CFG_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK;
 199         pci_pot[0].pobar = (CFG_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK;
 200         pci_pot[0].pocmr = POCMR_EN | POCMR_PREFETCH_EN | (POCMR_CM_256M & POCMR_CM_MASK);
 201
 202         /* PCI1 IO space */
 203         pci_pot[1].potar = (CFG_PCI1_IO_BASE >> 12) & POTAR_TA_MASK;
 204         pci_pot[1].pobar = (CFG_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK;
 205         pci_pot[1].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK);
 206
 207         /* PCI1 mmio - non-prefetch mem space */
 208         pci_pot[2].potar = (CFG_PCI1_MMIO_BASE >> 12) & POTAR_TA_MASK;
 209         pci_pot[2].pobar = (CFG_PCI1_MMIO_PHYS >> 12) & POBAR_BA_MASK;
 210         pci_pot[2].pocmr = POCMR_EN | (POCMR_CM_256M & POCMR_CM_MASK);
 211
 212         /*
 213          * Configure PCI Inbound Translation Windows
 214          */
 215
 216         /* we need RAM mapped to PCI space for the devices to
 217          * access main memory */
 218         pci_ctrl[0].pitar1 = 0x0;
 219         pci_ctrl[0].pibar1 = 0x0;
 220         pci_ctrl[0].piebar1 = 0x0;
 221         pci_ctrl[0].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1);
 222
 223         hose->first_busno = 0;
 224         hose->last_busno = 0xff;
 225
 226         /* PCI memory prefetch space */
 227         pci_set_region(hose->regions + 0,
 228                        CFG_PCI1_MEM_BASE,
 229                        CFG_PCI1_MEM_PHYS,
 230                        CFG_PCI1_MEM_SIZE,
 231                        PCI_REGION_MEM|PCI_REGION_PREFETCH);
 232
 233         /* PCI memory space */
 234         pci_set_region(hose->regions + 1,
 235                        CFG_PCI1_MMIO_BASE,
 236                        CFG_PCI1_MMIO_PHYS,
 237                        CFG_PCI1_MMIO_SIZE,
 238                        PCI_REGION_MEM);
 239
 240         /* PCI IO space */
 241         pci_set_region(hose->regions + 2,
 242                        CFG_PCI1_IO_BASE,
 243                        CFG_PCI1_IO_PHYS,
 244                        CFG_PCI1_IO_SIZE,
 245                        PCI_REGION_IO);
 246
 247         /* System memory space */
 248         pci_set_region(hose->regions + 3,
 249                        CONFIG_PCI_SYS_MEM_BUS,
 250                        CONFIG_PCI_SYS_MEM_PHYS,
 251                        gd->ram_size,
 252                        PCI_REGION_MEM | PCI_REGION_MEMORY);
 253
 254         hose->region_count = 4;
 255
 256         pci_setup_indirect(hose,
 257                            (CFG_IMMRBAR+0x8300),
 258                            (CFG_IMMRBAR+0x8304));
 259
 260         pci_register_hose(hose);
 261
 262         /*
 263          * Write to Command register
 264          */
 265         reg16 = 0xff;
 266         dev = PCI_BDF(hose->first_busno, 0, 0);
 267         pci_hose_read_config_word (hose, dev, PCI_COMMAND, &reg16);
 268         reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
 269         pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
 270
 271         /*
 272          * Clear non-reserved bits in status register.
 273          */
 274         pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
 275         pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
 276         pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
 277
 278 #ifdef CONFIG_PCI_SCAN_SHOW
 279         printf("PCI:   Bus Dev VenId DevId Class Int\n");
 280 #endif
 281         /*
 282          * Hose scan.
 283          */
 284         hose->last_busno = pci_hose_scan(hose);
 285
 286 #ifdef CONFIG_MPC83XX_PCI2
 287         hose = &pci_hose[1];
 288
 289         /*
 290          * Configure PCI Outbound Translation Windows
 291          */
 292
 293         /* PCI2 mem space - prefetch */
 294         pci_pot[3].potar = (CFG_PCI2_MEM_BASE >> 12) & POTAR_TA_MASK;
 295         pci_pot[3].pobar = (CFG_PCI2_MEM_PHYS >> 12) & POBAR_BA_MASK;
 296         pci_pot[3].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_PREFETCH_EN | (POCMR_CM_256M & POCMR_CM_MASK);
 297
 298         /* PCI2 IO space */
 299         pci_pot[4].potar = (CFG_PCI2_IO_BASE >> 12) & POTAR_TA_MASK;
 300         pci_pot[4].pobar = (CFG_PCI2_IO_PHYS >> 12) & POBAR_BA_MASK;
 301         pci_pot[4].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK);
 302
 303         /* PCI2 mmio - non-prefetch mem space */
 304         pci_pot[5].potar = (CFG_PCI2_MMIO_BASE >> 12) & POTAR_TA_MASK;
 305         pci_pot[5].pobar = (CFG_PCI2_MMIO_PHYS >> 12) & POBAR_BA_MASK;
 306         pci_pot[5].pocmr = POCMR_EN | POCMR_PCI2 | (POCMR_CM_256M & POCMR_CM_MASK);
 307
 308         /*
 309          * Configure PCI Inbound Translation Windows
 310          */
 311
 312         /* we need RAM mapped to PCI space for the devices to
 313          * access main memory */
 314         pci_ctrl[1].pitar1 = 0x0;
 315         pci_ctrl[1].pibar1 = 0x0;
 316         pci_ctrl[1].piebar1 = 0x0;
 317         pci_ctrl[1].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1);
 318
 319         hose->first_busno = pci_hose[0].last_busno + 1;
 320         hose->last_busno = 0xff;
 321
 322         /* PCI memory prefetch space */
 323         pci_set_region(hose->regions + 0,
 324                        CFG_PCI2_MEM_BASE,
 325                        CFG_PCI2_MEM_PHYS,
 326                        CFG_PCI2_MEM_SIZE,
 327                        PCI_REGION_MEM|PCI_REGION_PREFETCH);
 328
 329         /* PCI memory space */
 330         pci_set_region(hose->regions + 1,
 331                        CFG_PCI2_MMIO_BASE,
 332                        CFG_PCI2_MMIO_PHYS,
 333                        CFG_PCI2_MMIO_SIZE,
 334                        PCI_REGION_MEM);
 335
 336         /* PCI IO space */
 337         pci_set_region(hose->regions + 2,
 338                        CFG_PCI2_IO_BASE,
 339                        CFG_PCI2_IO_PHYS,
 340                        CFG_PCI2_IO_SIZE,
 341                        PCI_REGION_IO);
 342
 343         /* System memory space */
 344         pci_set_region(hose->regions + 3,
 345                        CONFIG_PCI_SYS_MEM_BUS,
 346                        CONFIG_PCI_SYS_MEM_PHYS,
 347                        gd->ram_size,
 348                        PCI_REGION_MEM | PCI_REGION_MEMORY);
 349
 350         hose->region_count = 4;
 351
 352         pci_setup_indirect(hose,
 353                            (CFG_IMMRBAR+0x8380),
 354                            (CFG_IMMRBAR+0x8384));
 355
 356         pci_register_hose(hose);
 357
 358         /*
 359          * Write to Command register
 360          */
 361         reg16 = 0xff;
 362         dev = PCI_BDF(hose->first_busno, 0, 0);
 363         pci_hose_read_config_word (hose, dev, PCI_COMMAND, &reg16);
 364         reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
 365         pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
 366
 367         /*
 368          * Clear non-reserved bits in status register.
 369          */
 370         pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
 371         pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
 372         pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
 373
 374         /*
 375          * Hose scan.
 376          */
 377         hose->last_busno = pci_hose_scan(hose);
 378 #endif
 379
 380 }
 381
 382 #endif /* CONFIG_PCI */