board/o2dnt/o2dnt.c

   1 /*
   2  * (C) Copyright 2005
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * (C) Copyright 2004
   6  * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27 #include <common.h>
  28 #include <mpc5xxx.h>
  29 #include <pci.h>
  30
  31 #define SDRAM_MODE      0x00CD0000
  32 #define SDRAM_CONTROL   0x504F0000
  33 #define SDRAM_CONFIG1   0xD2322800
  34 #define SDRAM_CONFIG2   0x8AD70000
  35
  36 static void sdram_start (int hi_addr)
  37 {
  38         long hi_addr_bit = hi_addr ? 0x01000000 : 0;
  39
  40         /* unlock mode register */
  41         *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
  42         __asm__ volatile ("sync");
  43
  44         /* precharge all banks */
  45         *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
  46         __asm__ volatile ("sync");
  47
  48         /* precharge all banks */
  49         *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
  50         __asm__ volatile ("sync");
  51
  52         /* auto refresh */
  53         *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
  54         __asm__ volatile ("sync");
  55
  56         /* set mode register */
  57         *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
  58         __asm__ volatile ("sync");
  59
  60         /* normal operation */
  61         *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
  62         __asm__ volatile ("sync");
  63 }
  64
  65 /*
  66  * ATTENTION: Although partially referenced initdram does NOT make real use
  67  *            use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
  68  *            is something else than 0x00000000.
  69  */
  70 long int initdram (int board_type)
  71 {
  72         ulong dramsize = 0;
  73         ulong dramsize2 = 0;
  74         ulong test1, test2;
  75
  76         /* setup SDRAM chip selects */
  77         *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
  78         *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
  79         __asm__ volatile ("sync");
  80
  81         /* setup config registers */
  82         *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
  83         *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
  84         __asm__ volatile ("sync");
  85
  86         /* find RAM size using SDRAM CS0 only */
  87         sdram_start(0);
  88         test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
  89         sdram_start(1);
  90         test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
  91         if (test1 > test2) {
  92                 sdram_start(0);
  93                 dramsize = test1;
  94         } else {
  95                 dramsize = test2;
  96         }
  97
  98         /* memory smaller than 1MB is impossible */
  99         if (dramsize < (1 << 20)) {
 100                 dramsize = 0;
 101         }
 102
 103         /* set SDRAM CS0 size according to the amount of RAM found */
 104         if (dramsize > 0)
 105                 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
 106         else
 107                 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
 108
 109         /* let SDRAM CS1 start right after CS0 */
 110         *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
 111
 112         /* find RAM size using SDRAM CS1 only */
 113         if (!dramsize)
 114                 sdram_start(0);
 115
 116         test2 = test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
 117
 118         if (!dramsize) {
 119                 sdram_start(1);
 120                 test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
 121         }
 122
 123         if (test1 > test2) {
 124                 sdram_start(0);
 125                 dramsize2 = test1;
 126         } else {
 127                 dramsize2 = test2;
 128         }
 129
 130         /* memory smaller than 1MB is impossible */
 131         if (dramsize2 < (1 << 20))
 132                 dramsize2 = 0;
 133
 134         /* set SDRAM CS1 size according to the amount of RAM found */
 135         if (dramsize2 > 0) {
 136                 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
 137                         | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
 138         } else {
 139                 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
 140         }
 141
 142         return dramsize + dramsize2;
 143 }
 144
 145 int checkboard (void)
 146 {
 147         puts ("Board: O2DNT\n");
 148         return 0;
 149 }
 150
 151 void flash_preinit(void)
 152 {
 153         /*
 154          * Now, when we are in RAM, enable flash write
 155          * access for detection process.
 156          * Note that CS_BOOT cannot be cleared when
 157          * executing in flash.
 158          */
 159         *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
 160 }
 161
 162 void flash_afterinit(ulong size)
 163 {
 164         if (size == 0x800000) { /* adjust mapping */
 165                 *(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START =
 166                         START_REG(CFG_BOOTCS_START | size);
 167
 168                 *(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP =
 169                         STOP_REG(CFG_BOOTCS_START | size, size);
 170         }
 171 }
 172
 173 #ifdef  CONFIG_PCI
 174 static struct pci_controller hose;
 175
 176 extern void pci_mpc5xxx_init(struct pci_controller *);
 177
 178 void pci_init_board(void)
 179 {
 180         pci_mpc5xxx_init(&hose);
 181 }
 182 #endif