board/r5200/r5200.c

   1 /*
   2  * (C) Copyright 2000-2003
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <asm/m5271.h>
  26 #include <asm/immap_5271.h>
  27
  28
  29 int checkboard (void) {
  30         puts ("Board: R5200 Ethernet Module\n");
  31         return 0;
  32 };
  33
  34 long int initdram (int board_type) {
  35         int i;
  36
  37         /*
  38          *  Set CS2 pin to be SD_CS0
  39          */
  40         mbar_writeByte(MCF_GPIO_PAR_CS, mbar_readByte(MCF_GPIO_PAR_CS)
  41                         | MCF_GPIO_PAR_CS_PAR_CS2);
  42
  43         mbar_writeByte(MCF_GPIO_PAR_SDRAM, mbar_readByte(MCF_GPIO_PAR_SDRAM)
  44                         | MCF_GPIO_PAR_SDRAM_PAR_CSSDCS(0x01));
  45
  46         /*
  47          * Check to see if the SDRAM has already been initialized
  48          * by a run control tool
  49          */
  50         if (!(mbar_readLong(MCF_SDRAMC_DACR0) & MCF_SDRAMC_DACRn_RE)) {
  51                 /*
  52                  * Initialize DRAM Control Register: DCR
  53                  */
  54                 mbar_writeShort(MCF_SDRAMC_DCR, MCF_SDRAMC_DCR_RTIM(0x01)
  55                                 | MCF_SDRAMC_DCR_RC(0x30));
  56
  57                 /*
  58                  * Initialize DACR0
  59                  */
  60                 mbar_writeLong(MCF_SDRAMC_DACR0,
  61                                 MCF_SDRAMC_DACRn_BA(CFG_SDRAM_BASE>>18)
  62                                 | MCF_SDRAMC_DACRn_CASL(0)
  63                                 | MCF_SDRAMC_DACRn_CBM(3)
  64                                 | MCF_SDRAMC_DACRn_PS(2));
  65
  66                 /*
  67                  * Initialize DMR0
  68                  */
  69                 mbar_writeLong(MCF_SDRAMC_DMR0,
  70                                 MCF_SDRAMC_DMRn_BAM_8M
  71                                 | MCF_SDRAMC_DMRn_V);
  72
  73                 /*
  74                  * Set IP bit in DACR
  75                  */
  76                 mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0)
  77                                 | MCF_SDRAMC_DACRn_IP);
  78
  79                 /*
  80                  * Wait at least 20ns to allow banks to precharge
  81                  */
  82                 for (i = 0; i < 5; i++)
  83                         asm(" nop");
  84
  85                 /*
  86                  * Write to this block to initiate precharge
  87                  */
  88                 *(u16 *)(CFG_SDRAM_BASE) = 0x9696;
  89
  90                 /*
  91                  * Set RE bit in DACR
  92                  */
  93                 mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0)
  94                                 | MCF_SDRAMC_DACRn_RE);
  95
  96
  97                 /*
  98                  * Wait for at least 8 auto refresh cycles to occur
  99                  */
 100                 for (i = 0; i < 2000; i++)
 101                         asm(" nop");
 102
 103                 /*
 104                  * Finish the configuration by issuing the MRS.
 105                  */
 106                 mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0)
 107                                 | MCF_SDRAMC_DACRn_MRS);
 108
 109
 110                 /*
 111                  * Write to the SDRAM Mode Register
 112                  */
 113                 *(u16 *)(CFG_SDRAM_BASE + 0x1000) = 0x9696;
 114         }
 115
 116         return CFG_SDRAM_SIZE * 1024 * 1024;
 117 };
 118
 119 int testdram (void) {
 120         /* TODO: XXX XXX XXX */
 121         printf ("DRAM test not implemented!\n");
 122
 123         return (0);
 124 }