board/siemens/IAD210/atm.h

   1 typedef unsigned char uint8;
   2 typedef unsigned short uint16;
   3 typedef unsigned int uint32;
   4 typedef volatile unsigned char vuint8;
   5 typedef volatile unsigned short vuint16;
   6 typedef volatile unsigned int vuint32;
   7
   8
   9 #define DPRAM_ATM CFG_IMMR + 0x3000
  10
  11 #define ATM_DPRAM_BEGIN  (DPRAM_ATM - CFG_IMMR - 0x2000)
  12 #define NUM_CONNECTIONS  1
  13 #define SAR_RXB_SIZE     1584
  14 #define AM_HMASK         0x0FFFFFF0
  15
  16 #define NUM_CT_ENTRIES           (NUM_CONNECTIONS)
  17 #define NUM_TCTE_ENTRIES         (NUM_CONNECTIONS)
  18 #define NUM_AM_ENTRIES           (NUM_CONNECTIONS+1)
  19 #define NUM_AP_ENTRIES           (NUM_CONNECTIONS+1)
  20 #define NUM_MPHYPT_ENTRIES       1
  21 #define NUM_APCP_ENTRIES         1
  22 #define NUM_APCT_PRIO_1_ENTRIES  146    /* Determines minimum rate */
  23 #define NUM_TQ_ENTRIES           12
  24
  25 #define SIZE_OF_CT_ENTRY         64
  26 #define SIZE_OF_TCTE_ENTRY       32
  27 #define SIZE_OF_AM_ENTRY         4
  28 #define SIZE_OF_AP_ENTRY         2
  29 #define SIZE_OF_MPHYPT_ENTRY     2
  30 #define SIZE_OF_APCP_ENTRY       32
  31 #define SIZE_OF_APCT_ENTRY       2
  32 #define SIZE_OF_TQ_ENTRY         2
  33
  34 #define CT_BASE           ((ATM_DPRAM_BEGIN + 63) & 0xFFC0)     /*64 */
  35 #define TCTE_BASE         (CT_BASE + NUM_CT_ENTRIES * SIZE_OF_CT_ENTRY) /*32 */
  36 #define APCP_BASE         (TCTE_BASE + NUM_TCTE_ENTRIES * SIZE_OF_TCTE_ENTRY)   /*32 */
  37 #define AM_BEGIN          (APCP_BASE + NUM_APCP_ENTRIES * SIZE_OF_APCP_ENTRY)   /*4 */
  38 #define AM_BASE           (AM_BEGIN + (NUM_AM_ENTRIES - 1) * SIZE_OF_AM_ENTRY)
  39 #define AP_BEGIN          (AM_BEGIN + NUM_AM_ENTRIES * SIZE_OF_AM_ENTRY)        /*2 */
  40 #define AP_BASE           (AP_BEGIN + (NUM_AP_ENTRIES - 1) * SIZE_OF_AP_ENTRY)
  41 #define MPHYPT_BASE       (AP_BEGIN + NUM_AP_ENTRIES * SIZE_OF_AP_ENTRY)        /*2 */
  42 #define APCT_PRIO_1_BASE  (MPHYPT_BASE + NUM_MPHYPT_ENTRIES * SIZE_OF_MPHYPT_ENTRY)     /*2 */
  43 #define TQ_BASE           (APCT_PRIO_1_BASE + NUM_APCT_PRIO_1_ENTRIES * SIZE_OF_APCT_ENTRY)     /*2 */
  44 #define ATM_DPRAM_SIZE    ((TQ_BASE + NUM_TQ_ENTRIES * SIZE_OF_TQ_ENTRY) - ATM_DPRAM_BEGIN)
  45
  46 #define CT_PTR(base)      ((struct ct_entry_t *)((char *)(base) + 0x2000 + CT_BASE))
  47 #define TCTE_PTR(base)    ((struct tcte_entry_t *)((char *)(base) + 0x2000 + TCTE_BASE))
  48 #define AM_PTR(base)      ((uint32 *)((char *)(base) + 0x2000 + AM_BASE))
  49 #define AP_PTR(base)      ((uint16 *)((char *)(base) + 0x2000 + AP_BASE))
  50 #define MPHYPT_PTR(base)  ((uint16 *)((char *)(base) + 0x2000 + MPHYPT_BASE))
  51 #define APCP_PTR(base)    ((struct apc_params_t *)((char*)(base) + 0x2000 + APCP_BASE))
  52 #define APCT1_PTR(base)   ((uint16 *)((char *)(base) + 0x2000 + APCT_PRIO_1_BASE))
  53 #define APCT2_PTR(base)   ((uint16 *)((char *)(base) + 0x2000 + APCT_PRIO_2_BASE))
  54 #define APCT3_PTR(base)   ((uint16 *)((char *)(base) + 0x2000 + APCT_PRIO_3_BASE))
  55 #define TQ_PTR(base)      ((uint16 *)((char *)(base) + 0x2000 + TQ_BASE))
  56
  57 /* SAR registers */
  58 #define RBDBASE(base)     ((vuint32 *)(base + 0x3F00))  /* Base address of RxBD-List */
  59 #define SRFCR(base)       ((vuint8 *)(base + 0x3F04))   /* DMA Receive function code */
  60 #define SRSTATE(base)     ((vuint8 *)(base + 0x3F05))   /* DMA Receive status */
  61 #define MRBLR(base)       ((vuint16 *)(base + 0x3F06))  /* Init to 0 for ATM */
  62 #define RSTATE(base)      ((vuint32 *)(base + 0x3F08))  /* Do not write to */
  63 #define R_CNT(base)       ((vuint16 *)(base + 0x3F10))  /* Do not write to */
  64 #define STFCR(base)       ((vuint8 *)(base + 0x3F12))   /* DMA Transmit function code */
  65 #define STSTATE(base)     ((vuint8 *)(base + 0x3F13))   /* DMA Transmit status */
  66 #define TBDBASE(base)     ((vuint32 *)(base + 0x3F14))  /* Base address of TxBD-List */
  67 #define TSTATE(base)      ((vuint32 *)(base + 0x3F18))  /* Do not write to */
  68 #define COMM_CH(base)     ((vuint16 *)(base + 0x3F1C))  /* Command channel */
  69 #define STCHNUM(base)     ((vuint16 *)(base + 0x3F1E))  /* Do not write to */
  70 #define T_CNT(base)       ((vuint16 *)(base + 0x3F20))  /* Do not write to */
  71 #define CTBASE(base)      ((vuint16 *)(base + 0x3F22))  /* Base address of Connection-table */
  72 #define ECTBASE(base)     ((vuint32 *)(base + 0x3F24))  /* Valid only for external Conn.-table */
  73 #define INTBASE(base)     ((vuint32 *)(base + 0x3F28))  /* Base address of Interrupt-table */
  74 #define INTPTR(base)      ((vuint32 *)(base + 0x3F2C))  /* Pointer to Interrupt-queue */
  75 #define C_MASK(base)      ((vuint32 *)(base + 0x3F30))  /* CRC-mask */
  76 #define SRCHNUM(base)     ((vuint16 *)(base + 0x3F34))  /* Do not write to */
  77 #define INT_CNT(base)     ((vuint16 *)(base + 0x3F36))  /* Interrupt-Counter */
  78 #define INT_ICNT(base)    ((vuint16 *)(base + 0x3F38))  /* Interrupt threshold */
  79 #define TSTA(base)        ((vuint16 *)(base + 0x3F3A))  /* Time-stamp-address */
  80 #define OLDLEN(base)      ((vuint16 *)(base + 0x3F3C))  /* Do not write to */
  81 #define SMRBLR(base)      ((vuint16 *)(base + 0x3F3E))  /* SAR max RXBuffer length */
  82 #define EHEAD(base)       ((vuint32 *)(base + 0x3F40))  /* Valid for serial mode */
  83 #define EPAYLOAD(base)    ((vuint32 *)(base + 0x3F44))  /* Valid for serial mode */
  84 #define TQBASE(base)      ((vuint16 *)(base + 0x3F48))  /* Base address of Tx queue */
  85 #define TQEND(base)       ((vuint16 *)(base + 0x3F4A))  /* End address of Tx queue */
  86 #define TQAPTR(base)      ((vuint16 *)(base + 0x3F4C))  /* TQ APC pointer */
  87 #define TQTPTR(base)      ((vuint16 *)(base + 0x3F4E))  /* TQ Tx pointer */
  88 #define APCST(base)       ((vuint16 *)(base + 0x3F50))  /* APC status */
  89 #define APCPTR(base)      ((vuint16 *)(base + 0x3F52))  /* APC parameter pointer */
  90 #define HMASK(base)       ((vuint32 *)(base + 0x3F54))  /* Header mask */
  91 #define AMBASE(base)      ((vuint16 *)(base + 0x3F58))  /* Address match table base */
  92 #define AMEND(base)       ((vuint16 *)(base + 0x3F5A))  /* Address match table end */
  93 #define APBASE(base)      ((vuint16 *)(base + 0x3F5C))  /* Address match parameter */
  94 #define FLBASE(base)      ((vuint32 *)(base + 0x3F54))  /* First-level table base */
  95 #define SLBASE(base)      ((vuint32 *)(base + 0x3F58))  /* Second-level table base */
  96 #define FLMASK(base)      ((vuint16 *)(base + 0x3F5C))  /* First-level mask */
  97 #define ECSIZE(base)      ((vuint16 *)(base + 0x3F5E))  /* Valid for extended mode */
  98 #define APCT_REAL(base)   ((vuint32 *)(base + 0x3F60))  /* APC 32 bit counter */
  99 #define R_PTR(base)       ((vuint32 *)(base + 0x3F64))  /* Do not write to */
 100 #define RTEMP(base)       ((vuint32 *)(base + 0x3F68))  /* Do not write to */
 101 #define T_PTR(base)       ((vuint32 *)(base + 0x3F6C))  /* Do not write to */
 102 #define TTEMP(base)       ((vuint32 *)(base + 0x3F70))  /* Do not write to */
 103
 104 /* ESAR registers */
 105 #define FMCTIMESTMP(base) ((vuint32 *)(base + 0x3F80))  /* Perf.Mon.Timestamp */
 106 #define FMCTEMPLATE(base) ((vuint32 *)(base + 0x3F84))  /* Perf.Mon.Template */
 107 #define PMPTR(base)       ((vuint16 *)(base + 0x3F88))  /* Perf.Mon.Table */
 108 #define PMCHANNEL(base)   ((vuint16 *)(base + 0x3F8A))  /* Perf.Mon.Channel */
 109 #define MPHYST(base)      ((vuint16 *)(base + 0x3F90))  /* Multi-PHY Status */
 110 #define TCTEBASE(base)    ((vuint16 *)(base + 0x3F92))  /* Internal TCT Extension Base */
 111 #define ETCTEBASE(base)   ((vuint32 *)(base + 0x3F94))  /* External TCT Extension Base */
 112 #define COMM_CH2(base)    ((vuint32 *)(base + 0x3F98))  /* 2nd command channel word */
 113 #define STATBASE(base)    ((vuint16 *)(base + 0x3F9C))  /* Statistics table pointer */
 114
 115 /* UTOPIA Mode Register */
 116 #define UTMODE(base)      (CAST(vuint32 *)(base + 0x0978))
 117
 118 /* SAR commands */
 119 #define TRANSMIT_CHANNEL_ACTIVATE_CMD   0x0FC1
 120 #define TRANSMIT_CHANNEL_DEACTIVATE_CMD 0x1FC1
 121 #define STOP_TRANSMIT_CMD               0x2FC1
 122 #define RESTART_TRANSMIT_CMD            0x3FC1
 123 #define STOP_RECEIVE_CMD                0x4FC1
 124 #define RESTART_RECEIVE_CMD             0x5FC1
 125 #define APC_BYPASS_CMD                  0x6FC1
 126 #define MEM_WRITE_CMD                   0x7FC1
 127 #define CPCR_FLG                        0x0001
 128
 129 /* INT flags */
 130 #define INT_VALID       0x80000000
 131 #define INT_WRAP        0x40000000
 132 #define INT_APCO        0x00800000
 133 #define INT_TQF         0x00200000
 134 #define INT_RXF         0x00080000
 135 #define INT_BSY         0x00040000
 136 #define INT_TXB         0x00020000
 137 #define INT_RXB         0x00010000
 138
 139 #define NUM_INT_ENTRIES   80
 140 #define SIZE_OF_INT_ENTRY 4
 141
 142 struct apc_params_t {
 143         vuint16 apct_base1;     /* APC Table - First Priority Base pointer */
 144         vuint16 apct_end1;      /* First APC Table - Length */
 145         vuint16 apct_ptr1;      /* First APC Table Pointer */
 146         vuint16 apct_sptr1;     /* APC Table First Priority Service pointer */
 147         vuint16 etqbase;        /* Enhanced Transmit Queue Base pointer */
 148         vuint16 etqend;         /* Enhanced Transmit Queue End pointer */
 149         vuint16 etqaptr;        /* Enhanced Transmit Queue APC pointer */
 150         vuint16 etqtptr;        /* Enhanced Transmit Queue Transmitter pointer */
 151         vuint16 apc_mi;         /* APC - Max Iteration */
 152         vuint16 ncits;          /* Number of Cells In TimeSlot  */
 153         vuint16 apcnt;          /* APC - N Timer */
 154         vuint16 reserved1;      /* reserved */
 155         vuint16 eapcst;         /* APC status */
 156         vuint16 ptp_counter;    /* PTP queue length */
 157         vuint16 ptp_txch;       /* PTP channel */
 158         vuint16 reserved2;      /* reserved */
 159 };
 160
 161 struct ct_entry_t {
 162         /* RCT */
 163         unsigned fhnt:1;
 164         unsigned pm_rct:1;
 165         unsigned reserved0:6;
 166         unsigned hec:1;
 167         unsigned clp:1;
 168         unsigned cng_ncrc:1;
 169         unsigned inf_rct:1;
 170         unsigned cngi_ptp:1;
 171         unsigned cdis_rct:1;
 172         unsigned aal_rct:2;
 173         uint16 rbalen;
 174         uint32 rcrc;
 175         uint32 rb_ptr;
 176         uint16 rtmlen;
 177         uint16 rbd_ptr;
 178         uint16 rbase;
 179         uint16 tstamp;
 180         uint16 imask;
 181         unsigned ft:2;
 182         unsigned nim:1;
 183         unsigned reserved1:2;
 184         unsigned rpmt:6;
 185         unsigned reserved2:5;
 186         uint8 reserved3[8];
 187         /* TCT */
 188         unsigned reserved4:1;
 189         unsigned pm_tct:1;
 190         unsigned reserved5:6;
 191         unsigned pc:1;
 192         unsigned reserved6:2;
 193         unsigned inf_tct:1;
 194         unsigned cr10:1;
 195         unsigned cdis_tct:1;
 196         unsigned aal_tct:2;
 197         uint16 tbalen;
 198         uint32 tcrc;
 199         uint32 tb_ptr;
 200         uint16 ttmlen;
 201         uint16 tbd_ptr;
 202         uint16 tbase;
 203         unsigned reserved7:5;
 204         unsigned tpmt:6;
 205         unsigned reserved8:3;
 206         unsigned avcf:1;
 207         unsigned act:1;
 208         uint32 chead;
 209         uint16 apcl;
 210         uint16 apcpr;
 211         unsigned out:1;
 212         unsigned bnr:1;
 213         unsigned tservice:2;
 214         unsigned apcp:12;
 215         uint16 apcpf;
 216 };
 217
 218 struct tcte_entry_t {
 219         unsigned res1:4;
 220         unsigned scr:12;
 221         uint16 scrf;
 222         uint16 bt;
 223         uint16 buptrh;
 224         uint32 buptrl;
 225         unsigned vbr2:1;
 226         unsigned res2:15;
 227         uint16 oobr;
 228         uint16 res3[8];
 229 };
 230
 231 #define SIZE_OF_RBD  12
 232 #define SIZE_OF_TBD  12
 233
 234 struct atm_bd_t {
 235         vuint16 flags;
 236         vuint16 length;
 237         unsigned char *buffer_ptr;
 238         vuint16 cpcs_uu_cpi;
 239         vuint16 reserved;
 240 };
 241
 242 /* BD flags */
 243 #define EMPTY           0x8000
 244 #define READY           0x8000
 245 #define WRAP            0x2000
 246 #define INTERRUPT       0x1000
 247 #define LAST            0x0800
 248 #define FIRST           0x0400
 249 #define OAM             0x0400
 250 #define CONTINUOUS      0x0200
 251 #define HEC_ERROR       0x0080
 252 #define CELL_LOSS       0x0040
 253 #define CONGESTION      0x0020
 254 #define ABORT           0x0010
 255 #define LEN_ERROR       0x0002
 256 #define CRC_ERROR       0x0001
 257
 258 struct atm_connection_t {
 259         struct atm_bd_t *rbd_ptr;
 260         int num_rbd;
 261         struct atm_bd_t *tbd_ptr;
 262         int num_tbd;
 263         struct ct_entry_t *ct_ptr;
 264         struct tcte_entry_t *tcte_ptr;
 265         void *drv;
 266         void (*notify) (void *drv, int event);
 267 };
 268
 269 struct atm_driver_t {
 270         int loaded;
 271         int started;
 272         char *csram;
 273         int csram_size;
 274         uint32 *am_top;
 275         uint16 *ap_top;
 276         uint32 *int_reload_ptr;
 277         uint32 *int_serv_ptr;
 278         struct atm_bd_t *rbd_base_ptr;
 279         struct atm_bd_t *tbd_base_ptr;
 280         unsigned linerate_in_bps;
 281 };
 282
 283 extern struct atm_connection_t g_conn[NUM_CONNECTIONS];
 284 extern struct atm_driver_t g_atm;
 285
 286 extern int atmLoad (void);
 287 extern void atmUnload (void);