board/tqm834x/tqm834x.c

   1 /*
   2  * (C) Copyright 2005
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  *
  23  */
  24
  25 #include <common.h>
  26 #include <ioports.h>
  27 #include <mpc83xx.h>
  28 #include <asm/mpc8349_pci.h>
  29 #include <i2c.h>
  30 #include <spd.h>
  31 #include <miiphy.h>
  32 #include <asm-ppc/mmu.h>
  33 #include <pci.h>
  34
  35 DECLARE_GLOBAL_DATA_PTR;
  36
  37 #define IOSYNC                  asm("eieio")
  38 #define ISYNC                   asm("isync")
  39 #define SYNC                    asm("sync")
  40 #define FPW                     FLASH_PORT_WIDTH
  41 #define FPWV                    FLASH_PORT_WIDTHV
  42
  43 #define DDR_MAX_SIZE_PER_CS     0x20000000
  44
  45 #if defined(DDR_CASLAT_20)
  46 #define TIMING_CASLAT           TIMING_CFG1_CASLAT_20
  47 #define MODE_CASLAT             DDR_MODE_CASLAT_20
  48 #else
  49 #define TIMING_CASLAT           TIMING_CFG1_CASLAT_25
  50 #define MODE_CASLAT             DDR_MODE_CASLAT_25
  51 #endif
  52
  53 #define INITIAL_CS_CONFIG       (CSCONFIG_EN | CSCONFIG_ROW_BIT_12 | \
  54                                 CSCONFIG_COL_BIT_9)
  55
  56 /* Global variable used to store detected number of banks */
  57 int tqm834x_num_flash_banks;
  58
  59 /* External definitions */
  60 ulong flash_get_size (ulong base, int banknum);
  61 extern flash_info_t flash_info[];
  62 extern long spd_sdram (void);
  63
  64 /* Local functions */
  65 static int detect_num_flash_banks(void);
  66 static long int get_ddr_bank_size(short cs, volatile long *base);
  67 static void set_cs_bounds(short cs, long base, long size);
  68 static void set_cs_config(short cs, long config);
  69 static void set_ddr_config(void);
  70
  71 /* Local variable */
  72 static volatile immap_t *im = (immap_t *)CFG_IMMRBAR;
  73
  74 /**************************************************************************
  75  * Board initialzation after relocation to RAM. Used to detect the number
  76  * of Flash banks on TQM834x.
  77  */
  78 int board_early_init_r (void) {
  79         /* sanity check, IMMARBAR should be mirrored at offset zero of IMMR */
  80         if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
  81                 return 0;
  82
  83         /* detect the number of Flash banks */
  84         return detect_num_flash_banks();
  85 }
  86
  87 /**************************************************************************
  88  * DRAM initalization and size detection
  89  */
  90 long int initdram (int board_type)
  91 {
  92         long bank_size;
  93         long size;
  94         int cs;
  95
  96         /* during size detection, set up the max DDRLAW size */
  97         im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE;
  98         im->sysconf.ddrlaw[0].ar = (LAWAR_EN | LAWAR_SIZE_2G);
  99
 100         /* set CS bounds to maximum size */
 101         for(cs = 0; cs < 4; ++cs) {
 102                 set_cs_bounds(cs,
 103                         CFG_DDR_BASE + (cs * DDR_MAX_SIZE_PER_CS),
 104                         DDR_MAX_SIZE_PER_CS);
 105
 106                 set_cs_config(cs, INITIAL_CS_CONFIG);
 107         }
 108
 109         /* configure ddr controller */
 110         set_ddr_config();
 111
 112         udelay(200);
 113
 114         /* enable DDR controller */
 115         im->ddr.sdram_cfg = (SDRAM_CFG_MEM_EN |
 116                 SDRAM_CFG_SREN |
 117                 SDRAM_CFG_SDRAM_TYPE_DDR);
 118         SYNC;
 119
 120         /* size detection */
 121         debug("\n");
 122         size = 0;
 123         for(cs = 0; cs < 4; ++cs) {
 124                 debug("\nDetecting Bank%d\n", cs);
 125
 126                 bank_size = get_ddr_bank_size(cs,
 127                         (volatile long*)(CFG_DDR_BASE + size));
 128                 size += bank_size;
 129
 130                 debug("DDR Bank%d size: %d MiB\n\n", cs, bank_size >> 20);
 131
 132                 /* exit if less than one bank */
 133                 if(size < DDR_MAX_SIZE_PER_CS) break;
 134         }
 135
 136         return size;
 137 }
 138
 139 /**************************************************************************
 140  * checkboard()
 141  */
 142 int checkboard (void)
 143 {
 144         puts("Board: TQM834x\n");
 145
 146 #ifdef CONFIG_PCI
 147         volatile immap_t * immr;
 148         u32 w, f;
 149
 150         immr = (immap_t *)CFG_IMMRBAR;
 151         if (!(immr->reset.rcwh & RCWH_PCIHOST)) {
 152                 printf("PCI:   NOT in host mode..?!\n");
 153                 return 0;
 154         }
 155
 156         /* get bus width */
 157         w = 32;
 158         if (immr->reset.rcwh & RCWH_PCI64)
 159                 w = 64;
 160
 161         /* get clock */
 162         f = gd->pci_clk;
 163
 164         printf("PCI1:  %d bit, %d MHz\n", w, f / 1000000);
 165 #else
 166         printf("PCI:   disabled\n");
 167 #endif
 168         return 0;
 169 }
 170
 171
 172 /**************************************************************************
 173  *
 174  * Local functions
 175  *
 176  *************************************************************************/
 177
 178 /**************************************************************************
 179  * Detect the number of flash banks (1 or 2). Store it in
 180  * a global variable tqm834x_num_flash_banks.
 181  * Bank detection code based on the Monitor code.
 182  */
 183 static int detect_num_flash_banks(void)
 184 {
 185         typedef unsigned long FLASH_PORT_WIDTH;
 186         typedef volatile unsigned long FLASH_PORT_WIDTHV;
 187         FPWV *bank1_base;
 188         FPWV *bank2_base;
 189         FPW bank1_read;
 190         FPW bank2_read;
 191         ulong bank1_size;
 192         ulong bank2_size;
 193         ulong total_size;
 194
 195         tqm834x_num_flash_banks = 2;    /* assume two banks */
 196
 197         /* Get bank 1 and 2 information */
 198         bank1_size = flash_get_size(CFG_FLASH_BASE, 0);
 199         debug("Bank1 size: %lu\n", bank1_size);
 200         bank2_size = flash_get_size(CFG_FLASH_BASE + bank1_size, 1);
 201         debug("Bank2 size: %lu\n", bank2_size);
 202         total_size = bank1_size + bank2_size;
 203
 204         if (bank2_size > 0) {
 205                 /* Seems like we've got bank 2, but maybe it's mirrored 1 */
 206
 207                 /* Set the base addresses */
 208                 bank1_base = (FPWV *) (CFG_FLASH_BASE);
 209                 bank2_base = (FPWV *) (CFG_FLASH_BASE + bank1_size);
 210
 211                 /* Put bank 2 into CFI command mode and read */
 212                 bank2_base[0x55] = 0x00980098;
 213                 IOSYNC;
 214                 ISYNC;
 215                 bank2_read = bank2_base[0x10];
 216
 217                 /* Read from bank 1 (it's in read mode) */
 218                 bank1_read = bank1_base[0x10];
 219
 220                 /* Reset Flash */
 221                 bank1_base[0] = 0x00F000F0;
 222                 bank2_base[0] = 0x00F000F0;
 223
 224                 if (bank2_read == bank1_read) {
 225                         /*
 226                          * Looks like just one bank, but not sure yet. Let's
 227                          * read from bank 2 in autosoelect mode.
 228                          */
 229                         bank2_base[0x0555] = 0x00AA00AA;
 230                         bank2_base[0x02AA] = 0x00550055;
 231                         bank2_base[0x0555] = 0x00900090;
 232                         IOSYNC;
 233                         ISYNC;
 234                         bank2_read = bank2_base[0x10];
 235
 236                         /* Read from bank 1 (it's in read mode) */
 237                         bank1_read = bank1_base[0x10];
 238
 239                         /* Reset Flash */
 240                         bank1_base[0] = 0x00F000F0;
 241                         bank2_base[0] = 0x00F000F0;
 242
 243                         if (bank2_read == bank1_read) {
 244                                 /*
 245                                  * In both CFI command and autoselect modes,
 246                                  * we got the some data reading from Flash.
 247                                  * There is only one mirrored bank.
 248                                  */
 249                                 tqm834x_num_flash_banks = 1;
 250                                 total_size = bank1_size;
 251                         }
 252                 }
 253         }
 254
 255         debug("Number of flash banks detected: %d\n", tqm834x_num_flash_banks);
 256
 257         /* set OR0 and BR0 */
 258         im->lbus.bank[0].or = CFG_OR_TIMING_FLASH |
 259                 (-(total_size) & OR_GPCM_AM);
 260         im->lbus.bank[0].br = (CFG_FLASH_BASE & BR_BA) |
 261                 (BR_MS_GPCM | BR_PS_32 | BR_V);
 262
 263         return (0);
 264 }
 265
 266 /*************************************************************************
 267  * Detect the size of a ddr bank. Sets CS bounds and CS config accordingly.
 268  */
 269 static long int get_ddr_bank_size(short cs, volatile long *base)
 270 {
 271         /* This array lists all valid DDR SDRAM configurations, with
 272          * Bank sizes in bytes. (Refer to Table 9-27 in the MPC8349E RM).
 273          * The last entry has to to have size equal 0 and is igonred during
 274          * autodection. Bank sizes must be in increasing order of size
 275          */
 276         struct {
 277                 long row;
 278                 long col;
 279                 long size;
 280         } conf[] = {
 281                 {CSCONFIG_ROW_BIT_12,   CSCONFIG_COL_BIT_8,     32 << 20},
 282                 {CSCONFIG_ROW_BIT_12,   CSCONFIG_COL_BIT_9,     64 << 20},
 283                 {CSCONFIG_ROW_BIT_12,   CSCONFIG_COL_BIT_10,    128 << 20},
 284                 {CSCONFIG_ROW_BIT_13,   CSCONFIG_COL_BIT_9,     128 << 20},
 285                 {CSCONFIG_ROW_BIT_13,   CSCONFIG_COL_BIT_10,    256 << 20},
 286                 {CSCONFIG_ROW_BIT_13,   CSCONFIG_COL_BIT_11,    512 << 20},
 287                 {CSCONFIG_ROW_BIT_14,   CSCONFIG_COL_BIT_10,    512 << 20},
 288                 {CSCONFIG_ROW_BIT_14,   CSCONFIG_COL_BIT_11,    1024 << 20},
 289                 {0,                     0,                      0}
 290         };
 291
 292         int i;
 293         int detected;
 294         long size;
 295
 296         detected = -1;
 297         for(i = 0; conf[i].size != 0; ++i) {
 298
 299                 /* set sdram bank configuration */
 300                 set_cs_config(cs, CSCONFIG_EN | conf[i].col | conf[i].row);
 301
 302                 debug("Getting RAM size...\n");
 303                 size = get_ram_size(base, DDR_MAX_SIZE_PER_CS);
 304
 305                 if((size == conf[i].size) && (i == detected + 1))
 306                         detected = i;
 307
 308                 debug("Trying %ld x %ld (%ld MiB) at addr %p, detected: %ld MiB\n",
 309                         conf[i].row,
 310                         conf[i].col,
 311                         conf[i].size >> 20,
 312                         base,
 313                         size >> 20);
 314         }
 315
 316         if(detected == -1){
 317                 /* disable empty cs */
 318                 debug("\nNo valid configurations for CS%d, disabling...\n", cs);
 319                 set_cs_config(cs, 0);
 320                 return 0;
 321         }
 322
 323         debug("\nDetected configuration %ld x %ld (%ld MiB) at addr %p\n",
 324                         conf[detected].row, conf[detected].col, conf[detected].size >> 20, base);
 325
 326         /* configure cs ro detected params */
 327         set_cs_config(cs, CSCONFIG_EN | conf[detected].row |
 328                         conf[detected].col);
 329
 330         set_cs_bounds(cs, (long)base, conf[detected].size);
 331
 332         return(conf[detected].size);
 333 }
 334
 335 /**************************************************************************
 336  * Sets DDR bank CS bounds.
 337  */
 338 static void set_cs_bounds(short cs, long base, long size)
 339 {
 340         debug("Setting bounds %08x, %08x for cs %d\n", base, size, cs);
 341         if(size == 0){
 342                 im->ddr.csbnds[cs].csbnds = 0x00000000;
 343         } else {
 344                 im->ddr.csbnds[cs].csbnds =
 345                         ((base >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
 346                         (((base + size - 1) >> CSBNDS_EA_SHIFT) &
 347                                 CSBNDS_EA);
 348         }
 349         SYNC;
 350 }
 351
 352 /**************************************************************************
 353  * Sets DDR banks CS configuration.
 354  * config == 0x00000000 disables the CS.
 355  */
 356 static void set_cs_config(short cs, long config)
 357 {
 358         debug("Setting config %08x for cs %d\n", config, cs);
 359         im->ddr.cs_config[cs] = config;
 360         SYNC;
 361 }
 362
 363 /**************************************************************************
 364  * Sets DDR clocks, timings and configuration.
 365  */
 366 static void set_ddr_config(void) {
 367         /* clock control */
 368         im->ddr.sdram_clk_cntl = DDR_SDRAM_CLK_CNTL_SS_EN |
 369                 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05;
 370         SYNC;
 371
 372         /* timing configuration */
 373         im->ddr.timing_cfg_1 =
 374                 (4 << TIMING_CFG1_PRETOACT_SHIFT) |
 375                 (7 << TIMING_CFG1_ACTTOPRE_SHIFT) |
 376                 (4 << TIMING_CFG1_ACTTORW_SHIFT)  |
 377                 (5 << TIMING_CFG1_REFREC_SHIFT)   |
 378                 (3 << TIMING_CFG1_WRREC_SHIFT)    |
 379                 (3 << TIMING_CFG1_ACTTOACT_SHIFT) |
 380                 (1 << TIMING_CFG1_WRTORD_SHIFT)   |
 381                 (TIMING_CFG1_CASLAT & TIMING_CASLAT);
 382
 383         im->ddr.timing_cfg_2 =
 384                 TIMING_CFG2_CPO_DEF |
 385                 (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT);
 386         SYNC;
 387
 388         /* don't enable DDR controller yet */
 389         im->ddr.sdram_cfg =
 390                 SDRAM_CFG_SREN |
 391                 SDRAM_CFG_SDRAM_TYPE_DDR;
 392         SYNC;
 393
 394         /* Set SDRAM mode */
 395         im->ddr.sdram_mode =
 396                 ((DDR_MODE_EXT_MODEREG | DDR_MODE_WEAK) <<
 397                         SDRAM_MODE_ESD_SHIFT) |
 398                 ((DDR_MODE_MODEREG | DDR_MODE_BLEN_4) <<
 399                         SDRAM_MODE_SD_SHIFT) |
 400                 ((DDR_MODE_CASLAT << SDRAM_MODE_SD_SHIFT) &
 401                         MODE_CASLAT);
 402         SYNC;
 403
 404         /* Set fast SDRAM refresh rate */
 405         im->ddr.sdram_interval =
 406                 (DDR_REFINT_166MHZ_7US << SDRAM_INTERVAL_REFINT_SHIFT) |
 407                 (DDR_BSTOPRE << SDRAM_INTERVAL_BSTOPRE_SHIFT);
 408         SYNC;
 409
 410         /* Workaround for DDR6 Erratum
 411          * see MPC8349E Device Errata Rev.8, 2/2006
 412          * This workaround influences the MPC internal "input enables"
 413          * dependent on CAS latency and MPC revision. According to errata
 414          * sheet the internal reserved registers for this workaround are
 415          * not available from revision 2.0 and up.
 416          */
 417
 418         /* Get REVID from register SPRIDR. Skip workaround if rev >= 2.0
 419          * (0x200)
 420          */
 421         if ((im->sysconf.spridr & SPRIDR_REVID) < 0x200) {
 422
 423                 /* There is a internal reserved register at IMMRBAR+0x2F00
 424                  * which has to be written with a certain value defined by
 425                  * errata sheet.
 426                  */
 427                 u32 *reserved_p = (u32 *)((u8 *)im + 0x2f00);
 428
 429 #if defined(DDR_CASLAT_20)
 430                 *reserved_p = 0x201c0000;
 431 #else
 432                 *reserved_p = 0x202c0000;
 433 #endif
 434         }
 435 }