| blob | e66d109443a18f4260dd4c219e09083442d1cc9a |
1 /*
2 * armboot - Startup Code for ARM720 CPU-core
3 *
4 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
5 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
27 #include <config.h>
28 #include <version.h>
29 #include <asm/hardware.h>
31 /*
32 *************************************************************************
33 *
34 * Jump vector table as in table 3.1 in [1]
35 *
36 *************************************************************************
37 */
40 .globl _start
41 _start: b reset
42 ldr pc, _undefined_instruction
43 ldr pc, _software_interrupt
44 ldr pc, _prefetch_abort
45 ldr pc, _data_abort
46 ldr pc, _not_used
47 ldr pc, _irq
48 ldr pc, _fiq
50 _undefined_instruction: .word undefined_instruction
51 _software_interrupt: .word software_interrupt
52 _prefetch_abort: .word prefetch_abort
53 _data_abort: .word data_abort
54 _not_used: .word not_used
55 _irq: .word irq
56 _fiq: .word fiq
58 .balignl 16,0xdeadbeef
61 /*
62 *************************************************************************
63 *
64 * Startup Code (reset vector)
65 *
66 * do important init only if we don't start from RAM!
67 * relocate armboot to ram
68 * setup stack
69 * jump to second stage
70 *
71 *************************************************************************
72 */
74 _TEXT_BASE:
75 .word TEXT_BASE
77 .globl _armboot_start
78 _armboot_start:
79 .word _start
81 /*
82 * These are defined in the board-specific linker script.
83 */
84 .globl _bss_start
85 _bss_start:
86 .word __bss_start
88 .globl _bss_end
89 _bss_end:
90 .word _end
92 #ifdef CONFIG_USE_IRQ
93 /* IRQ stack memory (calculated at run-time) */
94 .globl IRQ_STACK_START
95 IRQ_STACK_START:
96 .word 0x0badc0de
98 /* IRQ stack memory (calculated at run-time) */
99 .globl FIQ_STACK_START
100 FIQ_STACK_START:
101 .word 0x0badc0de
102 #endif
105 /*
106 * the actual reset code
107 */
109 reset:
110 /*
111 * set the cpu to SVC32 mode
112 */
113 mrs r0,cpsr
114 bic r0,r0,#0x1f
115 orr r0,r0,#0x13
116 msr cpsr,r0
118 /*
119 * we do sys-critical inits only at reboot,
120 * not when booting from ram!
121 */
122 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
123 bl cpu_init_crit
124 #endif
126 #ifndef CONFIG_SKIP_RELOCATE_UBOOT
127 relocate: /* relocate U-Boot to RAM */
128 adr r0, _start /* r0 <- current position of code */
129 ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
130 cmp r0, r1 /* don't reloc during debug */
131 beq stack_setup
133 #if TEXT_BASE
134 ldr r2, =0x0 /* Relocate the exception vectors */
135 cmp r1, r2 /* and associated data to address */
136 ldmneia r0!, {r3-r10} /* 0x0. Do nothing if TEXT_BASE is */
137 stmneia r2!, {r3-r10} /* 0x0. Copy the first 15 words. */
138 ldmneia r0, {r3-r9}
139 stmneia r2, {r3-r9}
140 adrne r0, _start /* restore r0 */
141 #endif
143 ldr r2, _armboot_start
144 ldr r3, _bss_start
145 sub r2, r3, r2 /* r2 <- size of armboot */
146 add r2, r0, r2 /* r2 <- source end address */
148 copy_loop:
149 ldmia r0!, {r3-r10} /* copy from source address [r0] */
150 stmia r1!, {r3-r10} /* copy to target address [r1] */
151 cmp r0, r2 /* until source end addreee [r2] */
152 ble copy_loop
154 #endif /* CONFIG_SKIP_RELOCATE_UBOOT */
156 /* Set up the stack */
157 stack_setup:
158 ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
159 sub r0, r0, #CFG_MALLOC_LEN /* malloc area */
160 sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */
161 #ifdef CONFIG_USE_IRQ
162 sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
163 #endif
164 sub sp, r0, #12 /* leave 3 words for abort-stack */
166 clear_bss:
167 ldr r0, _bss_start /* find start of bss segment */
168 ldr r1, _bss_end /* stop here */
169 mov r2, #0x00000000 /* clear */
171 clbss_l:str r2, [r0] /* clear loop... */
172 add r0, r0, #4
173 cmp r0, r1
174 ble clbss_l
176 ldr pc, _start_armboot
178 _start_armboot: .word start_armboot
180 /*
181 *************************************************************************
182 *
183 * CPU_init_critical registers
184 *
185 * setup important registers
186 * setup memory timing
187 *
188 *************************************************************************
189 */
191 #if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_ARMADILLO)
193 /* Interupt-Controller base addresses */
194 INTMR1: .word 0x80000280 @ 32 bit size
195 INTMR2: .word 0x80001280 @ 16 bit size
196 INTMR3: .word 0x80002280 @ 8 bit size
198 /* SYSCONs */
199 SYSCON1: .word 0x80000100
200 SYSCON2: .word 0x80001100
201 SYSCON3: .word 0x80002200
203 #define CLKCTL 0x6 /* mask */
204 #define CLKCTL_18 0x0 /* 18.432 MHz */
205 #define CLKCTL_36 0x2 /* 36.864 MHz */
206 #define CLKCTL_49 0x4 /* 49.152 MHz */
207 #define CLKCTL_73 0x6 /* 73.728 MHz */
209 #endif
211 cpu_init_crit:
212 #if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_ARMADILLO)
214 /*
215 * mask all IRQs by clearing all bits in the INTMRs
216 */
217 mov r1, #0x00
218 ldr r0, INTMR1
219 str r1, [r0]
220 ldr r0, INTMR2
221 str r1, [r0]
222 ldr r0, INTMR3
223 str r1, [r0]
225 /*
226 * flush v4 I/D caches
227 */
228 mov r0, #0
229 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
230 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
232 /*
233 * disable MMU stuff and caches
234 */
235 mrc p15,0,r0,c1,c0
236 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
237 bic r0, r0, #0x0000008f @ clear bits 7, 3:0 (B--- WCAM)
238 orr r0, r0, #0x00000002 @ set bit 2 (A) Align
239 mcr p15,0,r0,c1,c0
240 #elif defined(CONFIG_NETARM)
241 /*
242 * prior to software reset : need to set pin PORTC4 to be *HRESET
243 */
244 ldr r0, =NETARM_GEN_MODULE_BASE
245 ldr r1, =(NETARM_GEN_PORT_MODE(0x10) | \
246 NETARM_GEN_PORT_DIR(0x10))
247 str r1, [r0, #+NETARM_GEN_PORTC]
248 /*
249 * software reset : see HW Ref. Guide 8.2.4 : Software Service register
250 * for an explanation of this process
251 */
252 ldr r0, =NETARM_GEN_MODULE_BASE
253 ldr r1, =NETARM_GEN_SW_SVC_RESETA
254 str r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE]
255 ldr r1, =NETARM_GEN_SW_SVC_RESETB
256 str r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE]
257 ldr r1, =NETARM_GEN_SW_SVC_RESETA
258 str r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE]
259 ldr r1, =NETARM_GEN_SW_SVC_RESETB
260 str r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE]
261 /*
262 * setup PLL and System Config
263 */
264 ldr r0, =NETARM_GEN_MODULE_BASE
266 ldr r1, =( NETARM_GEN_SYS_CFG_LENDIAN | \
267 NETARM_GEN_SYS_CFG_BUSFULL | \
268 NETARM_GEN_SYS_CFG_USER_EN | \
269 NETARM_GEN_SYS_CFG_ALIGN_ABORT | \
270 NETARM_GEN_SYS_CFG_BUSARB_INT | \
271 NETARM_GEN_SYS_CFG_BUSMON_EN )
273 str r1, [r0, #+NETARM_GEN_SYSTEM_CONTROL]
275 #ifndef CONFIG_NETARM_PLL_BYPASS
276 ldr r1, =( NETARM_GEN_PLL_CTL_PLLCNT(NETARM_PLL_COUNT_VAL) | \
277 NETARM_GEN_PLL_CTL_POLTST_DEF | \
278 NETARM_GEN_PLL_CTL_INDIV(1) | \
279 NETARM_GEN_PLL_CTL_ICP_DEF | \
280 NETARM_GEN_PLL_CTL_OUTDIV(2) )
281 str r1, [r0, #+NETARM_GEN_PLL_CONTROL]
282 #endif
284 /*
285 * mask all IRQs by clearing all bits in the INTMRs
286 */
287 mov r1, #0
288 ldr r0, =NETARM_GEN_MODULE_BASE
289 str r1, [r0, #+NETARM_GEN_INTR_ENABLE]
291 #elif defined(CONFIG_S3C4510B)
293 /*
294 * Mask off all IRQ sources
295 */
296 ldr r1, =REG_INTMASK
297 ldr r0, =0x3FFFFF
298 str r0, [r1]
300 /*
301 * Disable Cache
302 */
303 ldr r0, =REG_SYSCFG
304 ldr r1, =0x83ffffa0 /* cache-disabled */
305 str r1, [r0]
307 #elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
308 /* No specific initialisation for IntegratorAP/CM720T as yet */
309 #else
310 #error No cpu_init_crit() defined for current CPU type
311 #endif
313 #ifdef CONFIG_ARM7_REVD
314 /* set clock speed */
315 /* !!! we run @ 36 MHz due to a hardware flaw in Rev. D processors */
316 /* !!! not doing DRAM refresh properly! */
317 ldr r0, SYSCON3
318 ldr r1, [r0]
319 bic r1, r1, #CLKCTL
320 orr r1, r1, #CLKCTL_36
321 str r1, [r0]
322 #endif
324 mov ip, lr
325 /*
326 * before relocating, we have to setup RAM timing
327 * because memory timing is board-dependent, you will
328 * find a lowlevel_init.S in your board directory.
329 */
330 bl lowlevel_init
331 mov lr, ip
333 mov pc, lr
336 /*
337 *************************************************************************
338 *
339 * Interrupt handling
340 *
341 *************************************************************************
342 */
344 @
345 @ IRQ stack frame.
346 @
347 #define S_FRAME_SIZE 72
349 #define S_OLD_R0 68
350 #define S_PSR 64
351 #define S_PC 60
352 #define S_LR 56
353 #define S_SP 52
355 #define S_IP 48
356 #define S_FP 44
357 #define S_R10 40
358 #define S_R9 36
359 #define S_R8 32
360 #define S_R7 28
361 #define S_R6 24
362 #define S_R5 20
363 #define S_R4 16
364 #define S_R3 12
365 #define S_R2 8
366 #define S_R1 4
367 #define S_R0 0
369 #define MODE_SVC 0x13
370 #define I_BIT 0x80
372 /*
373 * use bad_save_user_regs for abort/prefetch/undef/swi ...
374 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
375 */
377 .macro bad_save_user_regs
378 sub sp, sp, #S_FRAME_SIZE
379 stmia sp, {r0 - r12} @ Calling r0-r12
380 add r8, sp, #S_PC
382 ldr r2, _armboot_start
383 sub r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
384 sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
385 ldmia r2, {r2 - r4} @ get pc, cpsr, old_r0
386 add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
388 add r5, sp, #S_SP
389 mov r1, lr
390 stmia r5, {r0 - r4} @ save sp_SVC, lr_SVC, pc, cpsr, old_r
391 mov r0, sp
392 .endm
394 .macro irq_save_user_regs
395 sub sp, sp, #S_FRAME_SIZE
396 stmia sp, {r0 - r12} @ Calling r0-r12
397 add r8, sp, #S_PC
398 stmdb r8, {sp, lr}^ @ Calling SP, LR
399 str lr, [r8, #0] @ Save calling PC
400 mrs r6, spsr
401 str r6, [r8, #4] @ Save CPSR
402 str r0, [r8, #8] @ Save OLD_R0
403 mov r0, sp
404 .endm
406 .macro irq_restore_user_regs
407 ldmia sp, {r0 - lr}^ @ Calling r0 - lr
408 mov r0, r0
409 ldr lr, [sp, #S_PC] @ Get PC
410 add sp, sp, #S_FRAME_SIZE
411 subs pc, lr, #4 @ return & move spsr_svc into cpsr
412 .endm
414 .macro get_bad_stack
415 ldr r13, _armboot_start @ setup our mode stack
416 sub r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
417 sub r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
419 str lr, [r13] @ save caller lr / spsr
420 mrs lr, spsr
421 str lr, [r13, #4]
423 mov r13, #MODE_SVC @ prepare SVC-Mode
424 msr spsr_c, r13
425 mov lr, pc
426 movs pc, lr
427 .endm
429 .macro get_irq_stack @ setup IRQ stack
430 ldr sp, IRQ_STACK_START
431 .endm
433 .macro get_fiq_stack @ setup FIQ stack
434 ldr sp, FIQ_STACK_START
435 .endm
437 /*
438 * exception handlers
439 */
440 .align 5
441 undefined_instruction:
442 get_bad_stack
443 bad_save_user_regs
444 bl do_undefined_instruction
446 .align 5
447 software_interrupt:
448 get_bad_stack
449 bad_save_user_regs
450 bl do_software_interrupt
452 .align 5
453 prefetch_abort:
454 get_bad_stack
455 bad_save_user_regs
456 bl do_prefetch_abort
458 .align 5
459 data_abort:
460 get_bad_stack
461 bad_save_user_regs
462 bl do_data_abort
464 .align 5
465 not_used:
466 get_bad_stack
467 bad_save_user_regs
468 bl do_not_used
470 #ifdef CONFIG_USE_IRQ
472 .align 5
473 irq:
474 get_irq_stack
475 irq_save_user_regs
476 bl do_irq
477 irq_restore_user_regs
479 .align 5
480 fiq:
481 get_fiq_stack
482 /* someone ought to write a more effiction fiq_save_user_regs */
483 irq_save_user_regs
484 bl do_fiq
485 irq_restore_user_regs
487 #else
489 .align 5
490 irq:
491 get_bad_stack
492 bad_save_user_regs
493 bl do_irq
495 .align 5
496 fiq:
497 get_bad_stack
498 bad_save_user_regs
499 bl do_fiq
501 #endif
503 #if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_ARMADILLO)
504 .align 5
505 .globl reset_cpu
506 reset_cpu:
507 mov ip, #0
508 mcr p15, 0, ip, c7, c7, 0 @ invalidate cache
509 mcr p15, 0, ip, c8, c7, 0 @ flush TLB (v4)
510 mrc p15, 0, ip, c1, c0, 0 @ get ctrl register
511 bic ip, ip, #0x000f @ ............wcam
512 bic ip, ip, #0x2100 @ ..v....s........
513 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
514 mov pc, r0
515 #elif defined(CONFIG_NETARM)
516 .align 5
517 .globl reset_cpu
518 reset_cpu:
519 ldr r1, =NETARM_MEM_MODULE_BASE
520 ldr r0, [r1, #+NETARM_MEM_CS0_BASE_ADDR]
521 ldr r1, =0xFFFFF000
522 and r0, r1, r0
523 ldr r1, =(relocate-TEXT_BASE)
524 add r0, r1, r0
525 ldr r4, =NETARM_GEN_MODULE_BASE
526 ldr r1, =NETARM_GEN_SW_SVC_RESETA
527 str r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE]
528 ldr r1, =NETARM_GEN_SW_SVC_RESETB
529 str r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE]
530 ldr r1, =NETARM_GEN_SW_SVC_RESETA
531 str r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE]
532 ldr r1, =NETARM_GEN_SW_SVC_RESETB
533 str r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE]
534 mov pc, r0
535 #elif defined(CONFIG_S3C4510B)
536 /* Nothing done here as reseting the CPU is board specific, depending
537 * on external peripherals such as watchdog timers, etc. */
538 #elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
539 /* No specific reset actions for IntegratorAP/CM720T as yet */
540 #else
541 #error No reset_cpu() defined for current CPU type
542 #endif