2 * lowlevel_init.S - basic hardware initialization for the KS8695 CPU
4 * Copyright (c) 2004-2005, Greg Ungerer <greg.ungerer@opengear.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <asm/arch/platform.h>
29 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
32 *************************************************************************
36 *************************************************************************
40 .macro DELAY_FOR cycles, reg0
47 *************************************************************************
51 *************************************************************************
54 /* Should we boot with an interactive console or not */
58 *************************************************************************
60 * Raw hardware initialization code. The important thing is to get
61 * SDRAM setup and running. We do some other basic things here too,
62 * like getting the PLL set for high speed, and init the LEDs.
64 *************************************************************************
72 * enable UART for early debug trace
74 ldr r1, =(KS8695_IO_BASE+KS8695_UART_DIVISOR)
76 str r2, [r1] /* 115200 baud */
77 ldr r1, =(KS8695_IO_BASE+KS8695_UART_LINE_CTRL)
79 str r2, [r1] /* 8 data bits, no parity, 1 stop */
80 ldr r1, =(KS8695_IO_BASE+KS8695_UART_TX_HOLDING)
82 str r2, [r1] /* write 'A' */
85 ldr r1, =(KS8695_IO_BASE+KS8695_UART_TX_HOLDING)
91 * remap the memory and flash regions. we want to end up with
92 * ram from address 0, and flash at 32MB.
94 ldr r1, =(KS8695_IO_BASE+KS8695_MEM_CTRL0)
96 str r2, [r1] /* large flash map */
97 ldr pc, =(highflash+0x02000000-0x00f00000) /* jump to high flash address */
100 str r2, [r1] /* remap flash range */
103 * remap the second select region to the 4MB immediately after
104 * the first region. This way if you have a larger flash (say 8Mb)
105 * then you can have it all mapped nicely. Has no effect if you
106 * only have a 4Mb or smaller flash.
108 ldr r1, =(KS8695_IO_BASE+KS8695_MEM_CTRL1)
110 str r2, [r1] /* remap flash2 region, contiguous */
111 ldr r1, =(KS8695_IO_BASE+KS8695_MEM_GENERAL)
113 str r2, [r1] /* enable both flash selects */
117 * map the second flash chip, using the external IO lines.
119 ldr r1, =(KS8695_IO_BASE+KS8695_IO_CTRL0)
121 str r2, [r1] /* remap io0 region, contiguous */
122 ldr r1, =(KS8695_IO_BASE+KS8695_IO_CTRL1)
124 str r2, [r1] /* remap io1 region, contiguous */
125 ldr r1, =(KS8695_IO_BASE+KS8695_MEM_GENERAL)
127 str r2, [r1] /* enable second flash */
131 * before relocating, we have to setup RAM timing
133 ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_CTRL0)
134 #if (PHYS_SDRAM_1_SIZE == 0x02000000)
135 ldr r2, =0x7fc0000e /* 32MB */
137 ldr r2, =0x3fc0000e /* 16MB */
139 str r2, [r1] /* configure sdram bank0 setup */
140 ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_CTRL1)
142 str r2, [r1] /* configure sdram bank1 setup */
144 ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_GENERAL)
146 str r2, [r1] /* set RAS/CAS timing */
148 ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_BUFFER)
150 str r2, [r1] /* send NOP command */
153 str r2, [r1] /* send PRECHARGE-ALL */
156 ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_REFRESH)
158 str r2, [r1] /* set for fast refresh */
161 str r2, [r1] /* set normal refresh timing */
163 ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_BUFFER)
165 str r2, [r1] /* send mode command */
168 str r2, [r1] /* enable sdram fifos */
171 * set pll to top speed
173 ldr r1, =(KS8695_IO_BASE+KS8695_SYSTEN_BUS_CLOCK)
175 str r2, [r1] /* set pll clock to 166MHz */
177 ldr r1, =(KS8695_IO_BASE+KS8695_SWITCH_CTRL0)
178 ldr r2, [r1] /* Get switch ctrl0 register */
179 and r2, r2, #0x0fc00000 /* Mask out LED control bits */
180 orr r2, r2, #0x01800000 /* Set Link/activity/speed actions */
184 ldr r1, =(KS8695_IO_BASE+KS8695_GPIO_MODE)
186 str r2, [r1] /* enable LED's as outputs */
187 ldr r1, =(KS8695_IO_BASE+KS8695_GPIO_DATA)
189 str r2, [r1] /* turn on power LED */
191 #if defined(CONFIG_CM4008) || defined(CONFIG_CM41xx)
192 ldr r2, [r1] /* get current GPIO input data */
193 tst r2, #0x8 /* check if "erase" depressed */
195 mov r2, #0 /* be quiet on boot, no console */
196 ldr r1, =serial_console
201 add lr, lr, #0x02000000 /* flash is now mapped high */
202 add ip, ip, #0x02000000 /* this is a hack */
203 mov pc, lr /* all done, return */
205 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */