cpu/bf533/cache.S

   1
   2
   3 #define ASSEMBLY
   4 #include <asm/linkage.h>
   5 #include <asm/cpu/def_LPBlackfin.h>
   6
   7 .text
   8 .align 2
   9 ENTRY(blackfin_icache_flush_range)
  10         R2 = -32;
  11         R2 = R0 & R2;
  12         P0 = R2;
  13         P1 = R1;
  14         CSYNC;
  15 1:
  16         IFLUSH[P0++];
  17         CC = P0 < P1(iu);
  18         IF CC JUMP 1b(bp);
  19         IFLUSH[P0];
  20         SSYNC;
  21         RTS;
  22
  23 ENTRY(blackfin_dcache_flush_range)
  24         R2 = -32;
  25         R2 = R0 & R2;
  26         P0 = R2;
  27         P1 = R1;
  28         CSYNC;
  29 1:
  30         FLUSH[P0++];
  31         CC = P0 < P1(iu);
  32         IF CC JUMP 1b(bp);
  33         FLUSH[P0];
  34         SSYNC;
  35         RTS;
  36
  37 ENTRY(_icache_invalidate)
  38 ENTRY(invalidate_entire_icache)
  39         [--SP] = ( R7:5);
  40
  41         P0.L = (IMEM_CONTROL & 0xFFFF);
  42         P0.H = (IMEM_CONTROL >> 16);
  43         R7 = [P0];
  44
  45         /* Clear the IMC bit , All valid bits in the instruction
  46          * cache are set to the invalid state
  47          */
  48         BITCLR(R7,IMC_P);
  49         CLI R6;
  50         SSYNC;          /* SSYNC required before invalidating cache. */
  51         .align 8;
  52         [P0] = R7;
  53         SSYNC;
  54         STI R6;
  55
  56         /* Configures the instruction cache agian */
  57         R6 = (IMC | ENICPLB);
  58         R7 = R7 | R6;
  59
  60         CLI R6;
  61         SSYNC;          /* SSYNC required before writing to IMEM_CONTROL. */
  62         .align 8;
  63         [P0] = R7;
  64         SSYNC;
  65         STI R6;
  66
  67         ( R7:5) = [SP++];
  68         RTS;
  69
  70 /* Invalidate the Entire Data cache by
  71  * clearing DMC[1:0] bits
  72  */
  73 ENTRY(invalidate_entire_dcache)
  74 ENTRY(_dcache_invalidate)
  75         [--SP] = ( R7:6);
  76
  77         P0.L = (DMEM_CONTROL & 0xFFFF);
  78         P0.H = (DMEM_CONTROL >> 16);
  79         R7 = [P0];
  80
  81         /* Clear the DMC[1:0] bits, All valid bits in the data
  82          * cache are set to the invalid state
  83          */
  84         BITCLR(R7,DMC0_P);
  85         BITCLR(R7,DMC1_P);
  86         CLI R6;
  87         SSYNC;          /* SSYNC required before writing to DMEM_CONTROL. */
  88         .align 8;
  89         [P0] = R7;
  90         SSYNC;
  91         STI R6;
  92
  93         /* Configures the data cache again */
  94
  95         R6 = (ACACHE_BCACHE | ENDCPLB | PORT_PREF0);
  96         R7 = R7 | R6;
  97
  98         CLI R6;
  99         SSYNC;          /* SSYNC required before writing to DMEM_CONTROL. */
 100         .align 8;
 101         [P0] = R7;
 102         SSYNC;
 103         STI R6;
 104
 105         ( R7:6) = [SP++];
 106         RTS;
 107
 108 ENTRY(blackfin_dcache_invalidate_range)
 109         R2 = -32;
 110         R2 = R0 & R2;
 111         P0 = R2;
 112         P1 = R1;
 113         CSYNC;
 114 1:
 115         FLUSHINV[P0++];
 116         CC = P0 < P1 (iu);
 117         IF CC JUMP 1b (bp);
 118
 119         /* If the data crosses a cache line, then we'll be pointing to
 120         ** the last cache line, but won't have flushed/invalidated it yet, so do
 121         ** one more.
 122         */
 123         FLUSHINV[P0];
 124         SSYNC;
 125         RTS;