cpu/mips/jz5730_nand.c

   1 /*
   2  * Platform independend driver for JZ5730.
   3  *
   4  * Copyright (c) 2007 Ingenic Semiconductor Inc.
   5  * Author: <jlwei@ingenic.cn>
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  */
  12 #include <common.h>
  13
  14 #if (CONFIG_COMMANDS & CFG_CMD_NAND) && defined(CONFIG_JZ5730)
  15
  16 #include <nand.h>
  17
  18 #include <asm/jz5730.h>
  19
  20 static void jz_hwcontrol(struct mtd_info *mtd, int cmd)
  21 {
  22         struct nand_chip *this = (struct nand_chip *)(mtd->priv);
  23         switch (cmd) {
  24                 case NAND_CTL_SETNCE:
  25                         REG_EMC_NFCSR |= EMC_NFCSR_FCE;
  26                         break;
  27
  28                 case NAND_CTL_CLRNCE:
  29                         REG_EMC_NFCSR &= ~EMC_NFCSR_FCE;
  30                         break;
  31
  32                 case NAND_CTL_SETCLE:
  33                         this->IO_ADDR_W = (void __iomem *)((unsigned long)(this->IO_ADDR_W) | 0x00040000);
  34                         break;
  35
  36                 case NAND_CTL_CLRCLE:
  37                         this->IO_ADDR_W = (void __iomem *)((unsigned long)(this->IO_ADDR_W) & ~0x00040000);
  38                         break;
  39
  40                 case NAND_CTL_SETALE:
  41                         this->IO_ADDR_W = (void __iomem *)((unsigned long)(this->IO_ADDR_W) | 0x00080000);
  42                         break;
  43
  44                 case NAND_CTL_CLRALE:
  45                         this->IO_ADDR_W = (void __iomem *)((unsigned long)(this->IO_ADDR_W) & ~0x00080000);
  46                         break;
  47         }
  48 }
  49
  50 static int jz_device_ready(struct mtd_info *mtd)
  51 {
  52         int ready;
  53         ready = (REG_EMC_NFCSR & EMC_NFCSR_RB) ? 1 : 0;
  54         return ready;
  55 }
  56
  57 /*
  58  * EMC setup
  59  */
  60 static void jz_device_setup(void)
  61 {
  62         /* Set NFE bit */
  63         REG_EMC_NFCSR |= EMC_NFCSR_NFE;
  64 }
  65
  66 void board_nand_select_device(struct nand_chip *nand, int chip)
  67 {
  68         /*
  69          * Don't use "chip" to address the NAND device,
  70          * generate the cs from the address where it is encoded.
  71          */
  72 }
  73
  74 /*
  75  * Main initialization routine
  76  */
  77 void board_nand_init(struct nand_chip *nand)
  78 {
  79         jz_device_setup();
  80
  81         nand->eccmode = NAND_ECC_SOFT;
  82         nand->hwcontrol = jz_hwcontrol;
  83         nand->dev_ready = jz_device_ready;
  84
  85         /* Set address of NAND IO lines */
  86         nand->IO_ADDR_R = (void __iomem *) CFG_NAND_BASE;
  87         nand->IO_ADDR_W = (void __iomem *) CFG_NAND_BASE;
  88
  89         /* 20 us command delay time */
  90         nand->chip_delay = 20;
  91 }
  92
  93 #endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */