cpu/mips/jz_lcd.h

   1 #ifndef __JZLCD_H__
   2 #define __JZLCD_H__
   3
   4 #include <asm/io.h>
   5
   6 /* =============================================== */
   7 /*
   8  * change u-boot macro to celinux macro
   9  */
  10
  11 /* Chip type */
  12 #if defined(CONFIG_JZ4730)
  13 #define CONFIG_MIPS_JZ4730              1
  14 #endif
  15 #if defined(CONFIG_JZ4740)
  16 #define CONFIG_MIPS_JZ4740              1
  17 #endif
  18 #if defined(CONFIG_JZ5730)
  19 #define CONFIG_MIPS_JZ5730              1
  20 #endif
  21
  22 /* board */
  23 #if defined(CONFIG_LIBRA)
  24 #define CONFIG_MIPS_JZ4730_LIBRA                1
  25 #endif
  26 #if defined(CONFIG_PMPV1)
  27 #define CONFIG_MIPS_JZ4730_PMPV1                1
  28 #endif
  29 #if defined(CONFIG_PMPV2)
  30 #define CONFIG_MIPS_JZ4730_PMPV2                1
  31 #endif
  32 #if defined(CONFIG_GPS)
  33 #define CONFIG_MIPS_JZ4730_GPS                  1
  34 #endif
  35 #if defined(CONFIG_FPRINT)
  36 #define CONFIG_MIPS_JZ4730_FPRINT               1
  37 #endif
  38 #if defined(CONFIG_LEO)
  39 #define CONFIG_MIPS_JZ4740_LEO                  1
  40 #endif
  41 #if defined(CONFIG_PAVO)
  42 #define CONFIG_MIPS_JZ4740_PAVO                 1
  43 #endif
  44 #if defined(CONFIG_VIRGO)
  45 #define CONFIG_MIPS_JZ4740_VIRGO                1
  46 #endif
  47
  48 #define mdelay(n)               udelay((n)*1000)
  49
  50 /*
  51  * change u-boot macro to celinux macro
  52  */
  53 /* =============================================== */
  54
  55 #define NR_PALETTE      256
  56
  57 struct lcd_desc{
  58         unsigned int next_desc; /* LCDDAx */
  59         unsigned int databuf;   /* LCDSAx */
  60         unsigned int frame_id;  /* LCDFIDx */
  61         unsigned int cmd;       /* LCDCMDx */
  62 };
  63
  64 #define MODE_MASK               0x0f
  65 #define MODE_TFT_GEN            0x00
  66 #define MODE_TFT_SHARP          0x01
  67 #define MODE_TFT_CASIO          0x02
  68 #define MODE_TFT_SAMSUNG        0x03
  69 #define MODE_CCIR656_NONINT     0x04
  70 #define MODE_CCIR656_INT        0x05
  71 #define MODE_STN_COLOR_SINGLE   0x08
  72 #define MODE_STN_MONO_SINGLE    0x09
  73 #define MODE_STN_COLOR_DUAL     0x0a
  74 #define MODE_STN_MONO_DUAL      0x0b
  75 #define MODE_8BIT_SERIAL_TFT    0x0c
  76
  77 #define MODE_TFT_18BIT          (1<<7)
  78
  79 #define STN_DAT_PIN1    (0x00 << 4)
  80 #define STN_DAT_PIN2    (0x01 << 4)
  81 #define STN_DAT_PIN4    (0x02 << 4)
  82 #define STN_DAT_PIN8    (0x03 << 4)
  83 #define STN_DAT_PINMASK STN_DAT_PIN8
  84
  85 #define STFT_PSHI       (1 << 15)
  86 #define STFT_CLSHI      (1 << 14)
  87 #define STFT_SPLHI      (1 << 13)
  88 #define STFT_REVHI      (1 << 12)
  89
  90 #define SYNC_MASTER     (0 << 16)
  91 #define SYNC_SLAVE      (1 << 16)
  92
  93 #define DE_P            (0 << 9)
  94 #define DE_N            (1 << 9)
  95
  96 #define PCLK_P          (0 << 10)
  97 #define PCLK_N          (1 << 10)
  98
  99 #define HSYNC_P         (0 << 11)
 100 #define HSYNC_N         (1 << 11)
 101
 102 #define VSYNC_P         (0 << 8)
 103 #define VSYNC_N         (1 << 8)
 104
 105 #define DATA_NORMAL     (0 << 17)
 106 #define DATA_INVERSE    (1 << 17)
 107
 108
 109 /* Jz LCDFB supported I/O controls. */
 110 #define FBIOSETBACKLIGHT        0x4688
 111 #define FBIODISPON              0x4689
 112 #define FBIODISPOFF             0x468a
 113 #define FBIORESET               0x468b
 114 #define FBIOPRINT_REG           0x468c
 115
 116 /*
 117  * LCD panel specific definition
 118  */
 119
 120 #if defined(CONFIG_JZLCD_TRULY_TFTG320240DTSW) || defined(CONFIG_JZLCD_TRULY_TFTG320240DTSW_SERIAL)
 121
 122 #if defined(CONFIG_MIPS_JZ4730_PMPV1)
 123 #define LCD_RESET_PIN   63
 124 #elif defined(CONFIG_MIPS_JZ4730_PMPV2)
 125 #define LCD_RESET_PIN   60
 126 #elif defined(CONFIG_MIPS_JZ4740_LEO)
 127 #define LCD_RESET_PIN   50
 128 #endif
 129
 130 #define __lcd_special_on() \
 131 do { \
 132         __gpio_set_pin(LCD_RESET_PIN); \
 133         __gpio_as_output(LCD_RESET_PIN); \
 134         __gpio_clear_pin(LCD_RESET_PIN); \
 135         udelay(100); \
 136         __gpio_set_pin(LCD_RESET_PIN); \
 137 } while (0)
 138
 139 #endif /* CONFIG_JZLCD_TRULY_TFTG320240DTSW, parellel or serial RGB mode */
 140
 141 #if defined(CONFIG_JZLCD_SAMSUNG_LTV350QVF04)
 142
 143 #if defined(CONFIG_MIPS_JZ4730_FPRINT)
 144 #define PortSDI 60
 145 #define PortSCL 61
 146 #define PortCS  62
 147 #define PortRST 63
 148 #define PortSht 64
 149 #endif
 150
 151 #if defined(CONFIG_MIPS_JZ4730_GPS)
 152 #define PortSDI 74
 153 #define PortSCL 72
 154 #define PortCS  73
 155 #define PortRST 60
 156 #define PortSht 59
 157 #endif
 158
 159 #ifndef PortSDI
 160 #define PortSDI 0
 161 #endif
 162 #ifndef PortSCL
 163 #define PortSCL 0
 164 #endif
 165 #ifndef PortCS
 166 #define PortCS  0
 167 #endif
 168 #ifndef PortRST
 169 #define PortRST 0
 170 #endif
 171 #ifndef PortSht
 172 #define PortSht 0
 173 #endif
 174
 175 #define __lcd_special_pin_init() \
 176 do { \
 177         __gpio_as_output(PortSDI); /* SDI */\
 178         __gpio_as_output(PortSCL); /* SCL */ \
 179         __gpio_as_output(PortCS); /* CS */ \
 180         __gpio_as_output(PortRST); /* Reset */ \
 181         __gpio_as_output(PortSht); /* Shut Down # */ \
 182         __gpio_set_pin(PortCS); \
 183         __gpio_set_pin(PortSCL); \
 184         __gpio_set_pin(PortSDI); \
 185 } while (0)
 186
 187 #define __spi_out(val) \
 188 do { \
 189         int __i__; \
 190         unsigned int _t_ = (val); \
 191         __gpio_clear_pin(PortCS); \
 192         udelay(25); \
 193         for (__i__ = 0; __i__ < 24; __i__++ ) { \
 194                 __gpio_clear_pin(PortSCL); \
 195                 if (_t_ & 0x800000) \
 196                         __gpio_set_pin(PortSDI); \
 197                 else \
 198                         __gpio_clear_pin(PortSDI); \
 199                 _t_ <<= 1; \
 200                 udelay(25); \
 201                 __gpio_set_pin(PortSCL); \
 202                 udelay(25); \
 203         } \
 204         __gpio_set_pin(PortCS); \
 205         udelay(25); \
 206         __gpio_set_pin(PortSDI); \
 207         udelay(25); \
 208         __gpio_set_pin(PortSCL); \
 209 } while (0)
 210
 211 #define __spi_id_op_data(rs, rw, val) \
 212         __spi_out((0x1d<<18)|((rs)<<17)|((rw)<<16)|(val))
 213
 214 #define __spi_write_reg(reg, val) \
 215 do { \
 216         __spi_id_op_data(0, 0, (reg)); \
 217         __spi_id_op_data(1, 0, (val)); \
 218 } while (0)
 219
 220 #define __lcd_special_on() \
 221 do { \
 222         __gpio_set_pin(PortSht); \
 223         __gpio_clear_pin(PortRST); \
 224         mdelay(10); \
 225         __gpio_set_pin(PortRST); \
 226         mdelay(1); \
 227         __spi_write_reg(0x09, 0); \
 228         mdelay(10); \
 229         __spi_write_reg(0x09, 0x4000); \
 230         __spi_write_reg(0x0a, 0x2000); \
 231         mdelay(40); \
 232         __spi_write_reg(0x09, 0x4055); \
 233         mdelay(50); \
 234         __spi_write_reg(0x01, 0x409d); \
 235         __spi_write_reg(0x02, 0x0204); \
 236         __spi_write_reg(0x03, 0x0100); \
 237         __spi_write_reg(0x04, 0x3000); \
 238         __spi_write_reg(0x05, 0x4003); \
 239         __spi_write_reg(0x06, 0x000a); \
 240         __spi_write_reg(0x07, 0x0021); \
 241         __spi_write_reg(0x08, 0x0c00); \
 242         __spi_write_reg(0x10, 0x0103); \
 243         __spi_write_reg(0x11, 0x0301); \
 244         __spi_write_reg(0x12, 0x1f0f); \
 245         __spi_write_reg(0x13, 0x1f0f); \
 246         __spi_write_reg(0x14, 0x0707); \
 247         __spi_write_reg(0x15, 0x0307); \
 248         __spi_write_reg(0x16, 0x0707); \
 249         __spi_write_reg(0x17, 0x0000); \
 250         __spi_write_reg(0x18, 0x0004); \
 251         __spi_write_reg(0x19, 0x0000); \
 252         mdelay(60); \
 253         __spi_write_reg(0x09, 0x4a55); \
 254         __spi_write_reg(0x05, 0x5003); \
 255 } while (0)
 256
 257 #define __lcd_special_off() \
 258 do { \
 259         __spi_write_reg(0x09, 0x4055); \
 260         __spi_write_reg(0x05, 0x4003); \
 261         __spi_write_reg(0x0a, 0x0000); \
 262         mdelay(10); \
 263         __spi_write_reg(0x09, 0x4000); \
 264         __gpio_clear_pin(PortSht); \
 265 } while (0)
 266
 267 #endif  /* CONFIG_JZLCD_SAMSUNG_LTV350QVF04 */
 268
 269 #if defined(CONFIG_JZLCD_FOXCONN_PT035TN01) || defined(CONFIG_JZLCD_INNOLUX_PT035TN01_SERIAL)
 270
 271 #if defined(CONFIG_JZLCD_FOXCONN_PT035TN01) /* board pmp */
 272 #define MODE 0xcd               /* 24bit parellel RGB */
 273 #endif
 274 #if defined(CONFIG_JZLCD_INNOLUX_PT035TN01_SERIAL)
 275 #define MODE 0xc9               /* 8bit serial RGB */
 276 #endif
 277
 278 #if defined(CONFIG_MIPS_JZ4730_PMPV1) || defined(CONFIG_MIPS_JZ4730_PMPV2)
 279         #define SPEN    60       //LCD_SPL
 280         #define SPCK    61       //LCD_CLS
 281         #define SPDA    62       //LCD_PS
 282         #define LCD_RET 63       //LCD_REV  //use for lcd reset
 283 #elif defined(CONFIG_MIPS_JZ4740_LEO) /* board leo */
 284         #define SPEN    (32*1+18)       //LCD_SPL
 285         #define SPCK    (32*1+17)       //LCD_CLS
 286         #define SPDA    (32*2+22)       //LCD_PS
 287         #define LCD_RET (32*2+23)       //LCD_REV  //use for lcd reset
 288 #elif defined(CONFIG_MIPS_JZ4740_PAVO) /* board pavo */
 289         #define SPEN    (32*1+18)       //LCD_SPL
 290         #define SPCK    (32*1+17)       //LCD_CLS
 291         #define SPDA    (32*2+12)       //LCD_D12
 292         #define LCD_RET (32*2+23)       //LCD_REV, GPC23
 293 #else
 294 #error "driver/video/Jzlcd.h, please define SPI pins on your board."
 295 #endif
 296
 297         #define __spi_write_reg1(reg, val) \
 298         do { \
 299                 unsigned char no;\
 300                 unsigned short value;\
 301                 unsigned char a=0;\
 302                 unsigned char b=0;\
 303                 a=reg;\
 304                 b=val;\
 305                 __gpio_set_pin(SPEN);\
 306                 __gpio_set_pin(SPCK);\
 307                 __gpio_clear_pin(SPDA);\
 308                 __gpio_clear_pin(SPEN);\
 309                 udelay(25);\
 310                 value=((a<<8)|(b&0xFF));\
 311                 for(no=0;no<16;no++)\
 312                 {\
 313                         __gpio_clear_pin(SPCK);\
 314                         if((value&0x8000)==0x8000)\
 315                         __gpio_set_pin(SPDA);\
 316                         else\
 317                         __gpio_clear_pin(SPDA);\
 318                         udelay(25);\
 319                         __gpio_set_pin(SPCK);\
 320                         value=(value<<1); \
 321                         udelay(25);\
 322                  }\
 323                 __gpio_set_pin(SPEN);\
 324                 udelay(100);\
 325         } while (0)
 326
 327         #define __spi_write_reg(reg, val) \
 328         do {\
 329                 __spi_write_reg1((reg<<2|2), val);\
 330                 udelay(100); \
 331         }while(0)
 332
 333
 334         #define __lcd_special_pin_init() \
 335         do { \
 336                 __gpio_as_output(SPEN); /* use SPDA */\
 337                 __gpio_as_output(SPCK); /* use SPCK */\
 338                 __gpio_as_output(SPDA); /* use SPDA */\
 339                 __gpio_as_output(LCD_RET);\
 340         } while (0)
 341
 342         #define __lcd_special_on() \
 343         do { \
 344                 udelay(50);\
 345                 __gpio_clear_pin(LCD_RET);\
 346                 mdelay(150);\
 347                 __gpio_set_pin(LCD_RET);\
 348                 mdelay(10);\
 349                 __spi_write_reg(0x00, 0x03); \
 350                 __spi_write_reg(0x01, 0x40); \
 351                 __spi_write_reg(0x02, 0x11); \
 352                 __spi_write_reg(0x03, MODE); /* mode */ \
 353                 __spi_write_reg(0x04, 0x32); \
 354                 __spi_write_reg(0x05, 0x0e); \
 355                 __spi_write_reg(0x07, 0x03); \
 356                 __spi_write_reg(0x08, 0x08); \
 357                 __spi_write_reg(0x09, 0x40); \
 358                 __spi_write_reg(0x0A, 0x88); \
 359                 __spi_write_reg(0x0B, 0x88); \
 360                 __spi_write_reg(0x0C, 0x20); \
 361                 __spi_write_reg(0x0D, 0x20); \
 362         } while (0)     //reg 0x0a is control the display direction:DB0->horizontal level DB1->vertical level
 363
 364         #define __lcd_special_off() \
 365         do { \
 366                 __spi_write_reg(0x00, 0x03); \
 367         } while (0)
 368
 369 #endif  /* CONFIG_JZLCD_FOXCONN_PT035TN01 or CONFIG_JZLCD_INNOLUX_PT035TN01_SERIAL */
 370
 371 #if defined(CONFIG_JZLCD_TRULY_TFTG240320UTSW_63W_E)
 372
 373 #if defined(CONFIG_MIPS_JZ4730_FPRINT)
 374  #define PortSDI        60
 375  #define PortSCL        65              /* GPIO65 as WR/SCL */
 376  #define PortCS 62
 377  #define PortRST        63
 378  #define PortSDO 64
 379  #define PortSCL1  61
 380 #else
 381  #error "driver/video/Jzlcd.h, please define pins on your board."
 382 #endif
 383
 384 #define __spi_out(val) \
 385 do { \
 386         int __i__; \
 387         unsigned int _t_ = (val); \
 388         __gpio_clear_pin(PortCS); \
 389         udelay(2); \
 390         for (__i__ = 0; __i__ < 24; __i__++ ) { \
 391                 __gpio_clear_pin(PortSCL); \
 392                 if (_t_ & 0x800000) \
 393                         __gpio_set_pin(PortSDI); \
 394                 else \
 395                         __gpio_clear_pin(PortSDI); \
 396                 _t_ <<= 1; \
 397                 udelay(1); \
 398                 __gpio_set_pin(PortSCL); \
 399                 udelay(1); \
 400         } \
 401         udelay(2); \
 402         __gpio_set_pin(PortCS); \
 403         __gpio_set_pin(PortSDI); \
 404         __gpio_set_pin(PortSCL); \
 405 } while (0)
 406
 407 #define __spi_id_op_data(rs, rw, val) \
 408         __spi_out((0x0e<<19)|(0<<18)|((rs)<<17)|((rw)<<16)|(val)) /* 0e: 01110. ID:? */
 409
 410 #define __spi_write_reg(reg, val) \
 411 do { \
 412         __spi_id_op_data(0, 0, (reg)); \
 413         __spi_id_op_data(1, 0, (val)); \
 414 } while (0)
 415
 416 #define get_data(n)     (__gpio_get_pin((n)) ? 1:0) /* 1: high level, 0: low level */
 417
 418 static inline unsigned int __spi_in(void)
 419 {
 420         int __i__;
 421         unsigned int read_val = 0;
 422         unsigned int _t_ = (0x0e<<19)|(0<<18)|((1)<<17)|((1)<<16);/* 0e: 01110. ID:? */
 423
 424         __gpio_clear_pin(PortCS);
 425         udelay(2);
 426         //for (__i__ = 0; __i__ < 24; __i__++ ) {
 427         for (__i__ = 0; __i__ < 32; __i__++ ) {
 428                 __gpio_clear_pin(PortSCL);
 429                 if (_t_ & 0x800000) /* send data */
 430                         __gpio_set_pin(PortSDI);
 431                 else
 432                         __gpio_clear_pin(PortSDI);
 433                 _t_ <<= 1;
 434                 udelay(1);
 435                 __gpio_set_pin(PortSCL);
 436                 read_val <<= 1;
 437                 read_val |= get_data(PortSDO); /* receive data */
 438                 udelay(1);
 439         }
 440         udelay(2);
 441         __gpio_set_pin(PortCS);
 442         __gpio_set_pin(PortSDI);
 443         __gpio_set_pin(PortSCL);
 444
 445         return read_val;
 446  }
 447 static inline unsigned int __spi_read_reg(int reg)
 448 {
 449         unsigned int read_val;
 450         __spi_id_op_data(0, 0, (reg));
 451         udelay(40);
 452         read_val = __spi_in();
 453         return read_val;
 454 }
 455
 456
 457 #define WMLCDCOM(val)   __spi_id_op_data(0,0,val)
 458 #define WMLCDDATA(val)  __spi_id_op_data(1,0,val)
 459 #define Delayms(n)      mdelay(n)
 460
 461 static inline void mlcd_mode_setting(void)
 462 {
 463         /* RGB Interface */
 464         WMLCDCOM(0x0001);WMLCDDATA(0x0000); /* Horizontal reverse  */
 465         WMLCDCOM(0x0002);WMLCDDATA(0x0700);
 466         /* Entry Mode */
 467         //WMLCDCOM(0x0003);WMLCDDATA(0x1230); /* default 240x320, HWM=1 write data in high speed */
 468         WMLCDCOM(0x0003);WMLCDDATA(0x1038); /* Rotate to 320x240, HWM=0, low speed */
 469         WMLCDCOM(0x000C);WMLCDDATA(0x0111); /* External interface, as 16bit RGB interface */
 470         WMLCDCOM(0x0020);WMLCDDATA(0x0000); /* Horizontal base */
 471         WMLCDCOM(0x0021);WMLCDDATA(0x0000); /* Vertical base */
 472         WMLCDCOM(0x0030);WMLCDDATA(0x0707);
 473         WMLCDCOM(0x0031);WMLCDDATA(0x0407);
 474         WMLCDCOM(0x0032);WMLCDDATA(0x0203);
 475         WMLCDCOM(0x0033);WMLCDDATA(0x0303);
 476         WMLCDCOM(0x0034);WMLCDDATA(0x0303);
 477         WMLCDCOM(0x0035);WMLCDDATA(0x0202);
 478         WMLCDCOM(0x0036);WMLCDDATA(0x001F);
 479         WMLCDCOM(0x0037);WMLCDDATA(0x0707);
 480         WMLCDCOM(0x0038);WMLCDDATA(0x0407);
 481         WMLCDCOM(0x0039);WMLCDDATA(0x0203);
 482         WMLCDCOM(0x003A);WMLCDDATA(0x0303);
 483         WMLCDCOM(0x003B);WMLCDDATA(0x0303);
 484         WMLCDCOM(0x003C);WMLCDDATA(0x0202);
 485         WMLCDCOM(0x003D);WMLCDDATA(0x001F);
 486         WMLCDCOM(0x0050);WMLCDDATA(0x0000); /* X start:  0 */
 487         WMLCDCOM(0x0051);WMLCDDATA(0x00EF); /* X end:  239 */
 488         WMLCDCOM(0x0052);WMLCDDATA(0x0000); /* Y start:  0 */
 489         WMLCDCOM(0x0053);WMLCDDATA(0x013F); /* Y end:  319 */
 490         WMLCDCOM(0x0060);WMLCDDATA(0x2700);
 491         WMLCDCOM(0x0061);WMLCDDATA(0x0001);
 492         WMLCDCOM(0x006A);WMLCDDATA(0x0000); /* VL: Vertical Scroll */
 493         WMLCDCOM(0x0090);WMLCDDATA(0x0016);
 494         WMLCDCOM(0x0092);WMLCDDATA(0x0000);
 495         WMLCDCOM(0x0093);WMLCDDATA(0x0000);
 496 }
 497
 498 static inline void mlcd_power_on(void)
 499 {
 500         /* Power supply on */
 501         WMLCDCOM(0x0007);WMLCDDATA(0x0001);
 502         WMLCDCOM(0x0017);WMLCDDATA(0x0001);
 503         Delayms(50);
 504         WMLCDCOM(0x0010);WMLCDDATA(0x17B0);
 505         WMLCDCOM(0x0011);WMLCDDATA(0x0007);
 506         WMLCDCOM(0x0012);WMLCDDATA(0x011A);
 507         WMLCDCOM(0x0013);WMLCDDATA(0x0F00);
 508         WMLCDCOM(0x0029);WMLCDDATA(0x0010);
 509         WMLCDCOM(0x0012);WMLCDDATA(0x013A);
 510         Delayms(50);
 511 }
 512 static inline void mlcd_power_off(void)
 513 {
 514         WMLCDCOM(0x0010);WMLCDDATA(0x0780);
 515         WMLCDCOM(0x0011);WMLCDDATA(0x0067);
 516         WMLCDCOM(0x0012);WMLCDDATA(0x010A);
 517         Delayms(20);
 518         WMLCDCOM(0x0010);WMLCDDATA(0x0700);
 519 }
 520
 521 static inline void mlcd_display_on(void)
 522 {
 523         /* Display on sequence */
 524         WMLCDCOM(0x0007);WMLCDDATA(0x0021);
 525         Delayms(1);
 526         WMLCDCOM(0x0007);WMLCDDATA(0x0061);
 527         Delayms(20);
 528         WMLCDCOM(0x0007);WMLCDDATA(0x0173);
 529         WMLCDCOM(0x0022);       /* set Index register R22 */
 530 }
 531 static inline void mlcd_display_off(void)
 532 {
 533         /* Display off sequence */
 534         WMLCDCOM(0x0007);WMLCDDATA(0x0072);
 535         Delayms(20);
 536         WMLCDCOM(0x0007);WMLCDDATA(0x0001);
 537         Delayms(1);
 538         WMLCDCOM(0x0007);WMLCDDATA(0x0000);
 539 }
 540
 541 #define __lcd_special_pin_init() \
 542 do { \
 543         __gpio_as_input(PortSDO);  /* SDO */\
 544         __gpio_as_output(PortSDI); /* SDI */\
 545         __gpio_as_output(PortSCL); /* SCL */ \
 546         __gpio_as_output(PortCS);  /* CS */ \
 547         __gpio_as_output(PortRST); /* Reset */ \
 548         __gpio_as_output(PortSCL1); /* SCL1 */ \
 549         __gpio_set_pin(PortCS); \
 550         __gpio_set_pin(PortSCL); \
 551         __gpio_set_pin(PortSDI); \
 552         __gpio_set_pin(PortRST); \
 553         __gpio_set_pin(PortSCL1); \
 554         __gpio_set_pin(PortRST); \
 555 } while (0)
 556
 557 #define __lcd_special_on() \
 558 do { \
 559         mdelay(10); \
 560         __gpio_clear_pin(PortRST); /* Reset period > 1ms */ \
 561         mdelay(10); \
 562         __gpio_set_pin(PortRST); \
 563         mdelay(1); \
 564         mlcd_power_on(); \
 565         mlcd_mode_setting();\
 566         mlcd_display_on(); \
 567 } while (0)
 568
 569 #if 0                           /* Customer need Power Off? --No need, right now */
 570 #define __lcd_special_off() \
 571 do { \
 572         mlcd_display_off(); \
 573         mlcd_power_off(); \
 574 } while (0)
 575 #endif /* if 0 */
 576
 577 #endif  /* CONFIG_JZLCD_TRULY_TFTG240320UTSW_63W_E */
 578
 579 #ifndef __lcd_special_pin_init
 580 #define __lcd_special_pin_init()
 581 #endif
 582 #ifndef __lcd_special_on
 583 #define __lcd_special_on()
 584 #endif
 585 #ifndef __lcd_special_off
 586 #define __lcd_special_off()
 587 #endif
 588
 589
 590 /*
 591  * Platform specific definition
 592  */
 593
 594 #if defined(CONFIG_MIPS_JZ4730_GPS)
 595
 596 #define __lcd_set_backlight_level(n) \
 597 do { \
 598         ; \
 599 } while (0)
 600
 601 #define __lcd_display_pin_init() \
 602 do { \
 603         __lcd_special_pin_init(); \
 604         __gpio_as_output(94); /* PWM0 pin */ \
 605         __gpio_as_output(95); /* PWM1 pin */ \
 606 } while (0)
 607
 608 #define __lcd_display_on() \
 609 do { \
 610         __lcd_special_on(); \
 611         __gpio_set_pin(94); /* PWM0 pin */ \
 612         __gpio_set_pin(95); /* PWM1 pin */ \
 613         __lcd_set_backlight_level(8); \
 614 } while (0)
 615
 616 #define __lcd_display_off() \
 617 do { \
 618         __lcd_special_off(); \
 619 } while (0)
 620
 621 #endif /* CONFIG_MIPS_JZ4730_GPS */
 622
 623 #if defined(CONFIG_MIPS_JZ4730_FPRINT)
 624
 625 #define __lcd_set_backlight_level(n) \
 626 do { \
 627         REG_PWM_DUT(0) = n; \
 628         REG_PWM_PER(0) = 7; \
 629         REG_PWM_CTR(0) = 0xc1; \
 630 } while (0)
 631
 632 #if defined(CONFIG_JZLCD_FOXCONN_PT035TN01)
 633
 634 #define __lcd_display_pin_init() \
 635 do { \
 636         __lcd_special_pin_init();\
 637         __gpio_as_pwm();\
 638         __lcd_set_backlight_level(8);\
 639 } while (0)
 640
 641 #define __lcd_display_on() \
 642 do { \
 643         __lcd_set_backlight_level(8); \
 644         __lcd_special_on();\
 645 } while (0)
 646
 647 #define __lcd_display_off() \
 648 do { \
 649         __lcd_set_backlight_level(0); \
 650         __lcd_special_off();\
 651 } while (0)
 652
 653 #elif   defined(CONFIG_JZLCD_TRULY_TFTG240320UTSW_63W_E)
 654 /* pwm circle frequece = 1KHz */
 655 /* back light level: 0~100 */
 656 #undef  __lcd_set_backlight_level
 657 #define __lcd_set_backlight_level(n) \
 658 do { \
 659         REG_PWM_DUT(0) = n; \
 660         REG_PWM_PER(0) = 99; \
 661         REG_PWM_CTR(0) = 0xe4; \
 662 } while (0)
 663
 664 #define __lcd_display_pin_init() \
 665 do { \
 666         __lcd_special_pin_init();\
 667         __gpio_as_pwm();\
 668         __lcd_set_backlight_level(88);\
 669 } while (0)
 670
 671 #define __lcd_display_on() \
 672 do { \
 673         __lcd_set_backlight_level(88); \
 674         __lcd_special_on();\
 675 } while (0)
 676
 677 #define __lcd_display_off() \
 678 do { \
 679         __lcd_set_backlight_level(0); \
 680         __lcd_special_off();\
 681 } while (0)
 682
 683 #else
 684
 685 #define __lcd_display_pin_init() \
 686 do { \
 687         __gpio_as_output(GPIO_DISP_OFF_N); \
 688         __gpio_as_pwm(); \
 689         __lcd_set_backlight_level(8); \
 690 } while (0)
 691
 692 #define __lcd_display_on() \
 693 do { \
 694         __lcd_set_backlight_level(8); \
 695         __gpio_set_pin(GPIO_DISP_OFF_N); \
 696 } while (0)
 697
 698 #define __lcd_display_off() \
 699 do { \
 700         __lcd_set_backlight_level(0); \
 701         __gpio_clear_pin(GPIO_DISP_OFF_N); \
 702 } while (0)
 703 #endif
 704
 705 #endif /* CONFIG_MIPS_JZ4730_FPRINT */
 706
 707 #if defined(CONFIG_MIPS_JZ4730_LIBRA)
 708
 709 #define __lcd_set_backlight_level(n) \
 710 do { \
 711 } while (0)
 712
 713 #define __lcd_display_pin_init() \
 714 do { \
 715         __lcd_special_pin_init(); \
 716         __gpio_clear_pin(100); \
 717         __gpio_as_output(100); \
 718         __gpio_as_output(94); \
 719         __gpio_as_output(95); \
 720         __lcd_set_backlight_level(8); \
 721 } while (0)
 722
 723 #define __lcd_display_on() \
 724 do { \
 725         __lcd_special_on(); \
 726         __gpio_set_pin(100); \
 727         __gpio_set_pin(94); \
 728         __gpio_set_pin(95); \
 729 } while (0)
 730
 731 #define __lcd_display_off() \
 732 do { \
 733         __lcd_special_off(); \
 734         __gpio_clear_pin(100); \
 735         __gpio_clear_pin(94); \
 736         __gpio_clear_pin(95); \
 737 } while (0)
 738
 739 #endif /* CONFIG_MIPS_JZ4730_LIBRA */
 740
 741 #if defined(CONFIG_MIPS_JZ4730_PMPV1) || defined(CONFIG_MIPS_JZ4730_PMPV2)
 742
 743 #define GPIO_PWM0 94
 744
 745 #define __lcd_set_backlight_level(n) \
 746 do { \
 747         __gpio_as_pwm(); \
 748         REG_PWM_DUT(0) = n; \
 749         REG_PWM_PER(0) = 7; \
 750         REG_PWM_CTR(0) = 0xc1; \
 751 } while (0)
 752
 753 #define __lcd_close_backlight() \
 754 do { \
 755 __gpio_as_output(GPIO_PWM0);\
 756 __gpio_clear_pin(GPIO_PWM0);\
 757 } while (0)
 758
 759 #define __lcd_display_pin_init() \
 760 do { \
 761         __gpio_as_output(GPIO_DISP_OFF_N); \
 762         __lcd_set_backlight_level(8); \
 763         __lcd_special_pin_init(); \
 764 } while (0)
 765
 766 #define __lcd_display_on() \
 767 do { \
 768         __gpio_set_pin(GPIO_DISP_OFF_N); \
 769         __lcd_special_on(); \
 770         __lcd_set_backlight_level(8); \
 771 } while (0)
 772
 773 #define __lcd_display_off() \
 774 do { \
 775         __lcd_special_off(); \
 776         __lcd_close_backlight(); \
 777         __gpio_clear_pin(GPIO_DISP_OFF_N); \
 778 } while (0)
 779
 780 #endif /* CONFIG_MIPS_JZ4730_PMPV1 | CONFIG_MIPS_JZ4730_PMPV1 */
 781
 782
 783 #if defined(CONFIG_MIPS_JZ4740_LEO) || defined(CONFIG_MIPS_JZ4740_PAVO)|| defined(CONFIG_MIPS_JZ4740_VIRGO)
 784
 785 #if defined(CONFIG_MIPS_JZ4740_PAVO)
 786 #define GPIO_PWM    123         /* GP_D27 */
 787 #define PWM_CHN 4    /* pwm channel */
 788 #define PWM_FULL 101
 789 /* 100 level: 0,1,...,100 */
 790 /*#define __lcd_set_backlight_level(n)                     \
 791 do {                                                     \
 792         __gpio_as_pwm(4); \
 793         __tcu_disable_pwm_output(PWM_CHN);               \
 794         __tcu_stop_counter(PWM_CHN);                     \
 795         __tcu_init_pwm_output_high(PWM_CHN);             \
 796         __tcu_set_pwm_output_shutdown_abrupt(PWM_CHN);   \
 797         __tcu_select_clk_div1(PWM_CHN);                  \
 798         __tcu_mask_full_match_irq(PWM_CHN);              \
 799         __tcu_mask_half_match_irq(PWM_CHN);              \
 800         __tcu_set_count(PWM_CHN,0);                      \
 801         __tcu_set_full_data(PWM_CHN,__cpm_get_extalclk()/1000);           \
 802         __tcu_set_half_data(PWM_CHN,__cpm_get_extalclk()/1000*n/100);     \
 803         __tcu_enable_pwm_output(PWM_CHN);                \
 804         __tcu_select_extalclk(PWM_CHN);                  \
 805         __tcu_start_counter(PWM_CHN);                    \
 806 } while (0)
 807 */
 808 #define __lcd_set_backlight_level(n)                     \
 809 do { \
 810 __gpio_as_output(GPIO_PWM); \
 811 __gpio_set_pin(GPIO_PWM); \
 812 } while (0)
 813
 814 #define __lcd_close_backlight() \
 815 do { \
 816 __gpio_as_output(GPIO_PWM); \
 817 __gpio_clear_pin(GPIO_PWM); \
 818 } while (0)
 819
 820 #elif defined(CONFIG_MIPS_JZ4740_VIRGO)
 821 #define GPIO_PWM    119         /* GP_D23 */
 822 #define PWM_CHN 0    /* pwm channel */
 823 #define PWM_FULL 101
 824 /* 100 level: 0,1,...,100 */
 825 /*#define __lcd_set_backlight_level(n)                     \
 826 do {                                                     \
 827         __gpio_as_pwm(0); \
 828         __tcu_disable_pwm_output(PWM_CHN);               \
 829         __tcu_stop_counter(PWM_CHN);                     \
 830         __tcu_init_pwm_output_high(PWM_CHN);             \
 831         __tcu_set_pwm_output_shutdown_abrupt(PWM_CHN);   \
 832         __tcu_select_clk_div1(PWM_CHN);                  \
 833         __tcu_mask_full_match_irq(PWM_CHN);              \
 834         __tcu_mask_half_match_irq(PWM_CHN);              \
 835         __tcu_set_count(PWM_CHN,0);                      \
 836         __tcu_set_full_data(PWM_CHN,__cpm_get_extalclk()/1000);           \
 837         __tcu_set_half_data(PWM_CHN,__cpm_get_extalclk()/1000*n/100);     \
 838         __tcu_enable_pwm_output(PWM_CHN);                \
 839         __tcu_select_extalclk(PWM_CHN);                  \
 840         __tcu_start_counter(PWM_CHN);                    \
 841         } while (0)
 842 */
 843
 844 #define __lcd_set_backlight_level(n)                     \
 845 do { \
 846 __gpio_as_output(GPIO_PWM); \
 847 __gpio_set_pin(GPIO_PWM); \
 848 } while (0)
 849
 850 #define __lcd_close_backlight() \
 851 do { \
 852 __gpio_as_output(GPIO_PWM); \
 853 __gpio_clear_pin(GPIO_PWM); \
 854 } while (0)
 855
 856 #elif defined CONFIG_MIPS_JZ4740_LEO
 857
 858 #define __lcd_set_backlight_level(n)
 859 #define __lcd_close_backlight()
 860
 861 #endif /* #if defined(CONFIG_MIPS_JZ4740_PAVO) */
 862
 863 #define __lcd_display_pin_init() \
 864 do { \
 865         __gpio_as_output(GPIO_DISP_OFF_N); \
 866         __cpm_start_tcu(); \
 867         __lcd_special_pin_init(); \
 868 } while (0)
 869
 870 #define __lcd_display_on() \
 871 do { \
 872         __lcd_special_on(); \
 873         __gpio_set_pin(GPIO_DISP_OFF_N); \
 874         udelay(500000); \
 875         __lcd_set_backlight_level(80); \
 876 } while (0)
 877
 878 #define __lcd_display_off() \
 879 do { \
 880         __lcd_close_backlight(); \
 881         __lcd_special_off(); \
 882         __gpio_clear_pin(GPIO_DISP_OFF_N); \
 883 } while (0)
 884
 885 #endif /* CONFIG_MIPS_JZ4740_LEO */
 886
 887 #if defined(CONFIG_JZLCD_MSTN_240x128)
 888 #if 0   /* The final version does not use software emulation of VCOM. */
 889
 890 #define GPIO_VSYNC      59
 891 #define GPIO_VCOM       90
 892
 893 #define REG_VCOM        REG_GPIO_GPDR((GPIO_VCOM>>5))
 894 #define VCOM_BIT        (1 << (GPIO_VCOM & 0x1f))
 895 static unsigned int vcom_static;
 896 static void vsync_irq(int irq, void *dev_id, struct pt_regs *reg)
 897 {
 898         vcom_static = REG_VCOM;
 899         vcom_static ^= VCOM_BIT;
 900         REG_VCOM = vcom_static;
 901 }
 902
 903 #define __lcd_display_pin_init()                                          \
 904         __gpio_as_irq_rise_edge(GPIO_VSYNC);                              \
 905         __gpio_as_output(GPIO_VCOM);                                      \
 906         {                                                                 \
 907         static int inited = 0;                                            \
 908         if (!inited) {                                                    \
 909         inited = 1;                                                       \
 910         if (request_irq(IRQ_GPIO_0 + GPIO_VSYNC, vsync_irq, SA_INTERRUPT, \
 911                         "vsync", 0)) {                                    \
 912                 err = -EBUSY;                                             \
 913                 goto failed;                                              \
 914         }}}
 915
 916 #endif
 917
 918 /* We uses AC BIAs pin to generate VCOM signal, so above code should be removed.
 919  */
 920
 921 #endif
 922 /*****************************************************************************
 923  * LCD display pin dummy macros
 924  *****************************************************************************/
 925 #ifndef __lcd_display_pin_init
 926 #define __lcd_display_pin_init()
 927 #endif
 928 #ifndef __lcd_display_on
 929 #define __lcd_display_on()
 930 #endif
 931 #ifndef __lcd_display_off
 932 #define __lcd_display_off()
 933 #endif
 934 #ifndef __lcd_set_backlight_level
 935 #define __lcd_set_backlight_level(n)
 936 #endif
 937
 938 #endif /* __JZLCD_H__ */