cpu/mips/jz_slcd.h

   1 #ifndef __JZSLCD_H__
   2 #define __JZSLCD_H__
   3
   4 #include <asm/io.h>
   5
   6 /*from rockbox. thanks Maurus*/
   7
   8 #define PIN_CS_N    (32*1+17) /* Chip select */
   9 #define PIN_RESET_N (32*1+18) /* Reset */
  10
  11 #define WAIT_ON_SLCD while(REG_SLCD_STATE & SLCD_STATE_BUSY);
  12 #define SLCD_SET_DATA(x) WAIT_ON_SLCD; REG_SLCD_DATA = (x) | SLCD_DATA_RS_DATA;
  13 #define SLCD_SET_COMMAND(x) WAIT_ON_SLCD; REG_SLCD_DATA = (x) | SLCD_DATA_RS_COMMAND;
  14 #define SLCD_SEND_COMMAND(cmd,val) SLCD_SET_COMMAND(cmd); SLCD_SET_DATA(val);
  15
  16 #if defined(CONFIG_JZSLCD_TFT_G240400RTSW_3WTP_E)
  17
  18 /* Register list from rockbox*/
  19 #define REG_DRIVER_OUTPUT                0x001
  20 #define REG_LCD_DR_WAVE_CTRL             0x002
  21 #define REG_ENTRY_MODE                   0x003
  22 #define REG_OUTL_SHARP_CTRL              0x006
  23 #define REG_DISP_CTRL1                   0x007
  24 #define REG_DISP_CTRL2                   0x008
  25 #define REG_DISP_CTRL3                   0x009
  26 #define REG_LPCTRL                       0x00B
  27 #define REG_EXT_DISP_CTRL1               0x00C
  28 #define REG_EXT_DISP_CTRL2               0x00F
  29 #define REG_PAN_INTF_CTRL1               0x010
  30 #define REG_PAN_INTF_CTRL2               0x011
  31 #define REG_PAN_INTF_CTRL3               0x012
  32 #define REG_PAN_INTF_CTRL4               0x020
  33 #define REG_PAN_INTF_CTRL5               0x021
  34 #define REG_PAN_INTF_CTRL6               0x022
  35 #define REG_FRM_MRKR_CTRL                0x090
  36
  37 #define REG_PWR_CTRL1                    0x100
  38 #define REG_PWR_CTRL2                    0x101
  39 #define REG_PWR_CTRL3                    0x102
  40 #define REG_PWR_CTRL4                    0x103
  41 #define REG_PWR_CTRL5                    0x107
  42 #define REG_PWR_CTRL6                    0x110
  43 #define REG_PWR_CTRL7                    0x112
  44
  45 #define REG_RAM_HADDR_SET                0x200
  46 #define REG_RAM_VADDR_SET                0x201
  47 #define REG_RW_GRAM                      0x202
  48 #define REG_RAM_HADDR_START              0x210
  49 #define REG_RAM_HADDR_END                0x211
  50 #define REG_RAM_VADDR_START              0x212
  51 #define REG_RAM_VADDR_END                0x213
  52 #define REG_RW_NVM                       0x280
  53 #define REG_VCOM_HVOLTAGE1               0x281
  54 #define REG_VCOM_HVOLTAGE2               0x282
  55
  56 #define REG_GAMMA_CTRL1                  0x300
  57 #define REG_GAMMA_CTRL2                  0x301
  58 #define REG_GAMMA_CTRL3                  0x302
  59 #define REG_GAMMA_CTRL4                  0x303
  60 #define REG_GAMMA_CTRL5                  0x304
  61 #define REG_GAMMA_CTRL6                  0x305
  62 #define REG_GAMMA_CTRL7                  0x306
  63 #define REG_GAMMA_CTRL8                  0x307
  64 #define REG_GAMMA_CTRL9                  0x308
  65 #define REG_GAMMA_CTRL10                 0x309
  66 #define REG_GAMMA_CTRL11                 0x30A
  67 #define REG_GAMMA_CTRL12                 0x30B
  68 #define REG_GAMMA_CTRL13                 0x30C
  69 #define REG_GAMMA_CTRL14                 0x30D
  70
  71 #define REG_BIMG_NR_LINE                 0x400
  72 #define REG_BIMG_DISP_CTRL               0x401
  73 #define REG_BIMG_VSCROLL_CTRL            0x404
  74
  75 #define REG_PARTIMG1_POS                 0x500
  76 #define REG_PARTIMG1_RAM_START           0x501
  77 #define REG_PARTIMG1_RAM_END             0x502
  78 #define REG_PARTIMG2_POS                 0x503
  79 #define REG_PARTIMG2_RAM_START           0x504
  80 #define REG_PARTIMG2_RAM_END             0x505
  81
  82 #define REG_SOFT_RESET                   0x600
  83 #define REG_ENDIAN_CTRL                  0x606
  84 #define REG_NVM_ACCESS_CTRL              0x6F0
  85
  86 /* Bits */
  87 #define DRIVER_OUTPUT_SS_BIT             (1 << 8)
  88 #define DRIVER_OUTPUT_SM_BIT             (1 << 10)
  89
  90 #define ENTRY_MODE_TRI                   (1 << 15)
  91 #define ENTRY_MODE_DFM                   (1 << 14)
  92 #define ENTRY_MODE_BGR                   (1 << 12)
  93 #define ENTRY_MODE_HWM                   (1 << 9)
  94 #define ENTRY_MODE_ORG                   (1 << 7)
  95 #define ENTRY_MODE_VID                   (1 << 5)
  96 #define ENTRY_MODE_HID                   (1 << 4)
  97 #define ENTRY_MODE_AM                    (1 << 3)
  98 #define ENTRY_MODE_EPF(n)                (n & 3)
  99
 100 #define OUTL_SHARP_CTRL_EGMODE           (1 << 15)
 101 #define OUTL_SHARP_CTRL_AVST(n)          ((n & 7) << 7)
 102 #define OUTL_SHARP_CTRL_ADST(n)          ((n & 7) << 4)
 103 #define OUTL_SHARP_CTRL_DTHU(n)          ((n & 3) << 2)
 104 #define OUTL_SHARP_CTRL_DTHL(n)          (n & 3)
 105
 106 #define DISP_CTRL1_PTDE(n)               ((n & 4) << 12)
 107 #define DISP_CTRL1_BASEE                 (1 << 8)
 108 #define DISP_CTRL1_VON                   (1 << 6)
 109 #define DISP_CTRL1_GON                   (1 << 5)
 110 #define DISP_CTRL1_DTE                   (1 << 4)
 111 #define DISP_CTRL1_D(n)                  (n & 3)
 112
 113 #define PWR_CTRL1_SAP(n)                 ((n & 3) << 13)
 114 #define PWR_CTRL1_SAPE                   (1 << 12)
 115 #define PWR_CTRL1_BT(n)                  ((n & 7) << 8)
 116 #define PWR_CTRL1_APE                    (1 << 7)
 117 #define PWR_CTRL1_AP(n)                  ((n & 7) << 4)
 118 #define PWR_CTRL1_DSTB                   (1 << 2)
 119 #define PWR_CTRL1_SLP                    (1 << 1)
 120
 121 #define SOFT_RESET(n)                    (n << 0)
 122
 123 #define BACKLIGHT_GPIO  (32*3+31)
 124 #define BACKLIGHT_PWM   7
 125
 126
 127 #endif
 128
 129 #endif