include/asm-blackfin/mem_init.h

   1 /*
   2  * U-boot - mem_init.h Header file for memory initialization
   3  *
   4  * Copyright (c) 2005 blackfin.uclinux.org
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #if ( CONFIG_MEM_MT48LC16M16A2TG_75  ||  CONFIG_MEM_MT48LC64M4A2FB_7E )
  26         #if ( CONFIG_SCLK_HZ > 119402985 )
  27                 #define SDRAM_tRP       TRP_2
  28                 #define SDRAM_tRP_num   2
  29                 #define SDRAM_tRAS      TRAS_7
  30                 #define SDRAM_tRAS_num  7
  31                 #define SDRAM_tRCD      TRCD_2
  32                 #define SDRAM_tWR       TWR_2
  33         #endif
  34         #if ( CONFIG_SCLK_HZ > 104477612 ) && ( CONFIG_SCLK_HZ <= 119402985 )
  35                 #define SDRAM_tRP       TRP_2
  36                 #define SDRAM_tRP_num   2
  37                 #define SDRAM_tRAS      TRAS_6
  38                 #define SDRAM_tRAS_num  6
  39                 #define SDRAM_tRCD      TRCD_2
  40                 #define SDRAM_tWR       TWR_2
  41         #endif
  42         #if ( CONFIG_SCLK_HZ >  89552239 ) && ( CONFIG_SCLK_HZ <= 104477612 )
  43                 #define SDRAM_tRP       TRP_2
  44                 #define SDRAM_tRP_num   2
  45                 #define SDRAM_tRAS      TRAS_5
  46                 #define SDRAM_tRAS_num  5
  47                 #define SDRAM_tRCD      TRCD_2
  48                 #define SDRAM_tWR       TWR_2
  49         #endif
  50         #if ( CONFIG_SCLK_HZ >  74626866 ) && ( CONFIG_SCLK_HZ <=  89552239 )
  51                 #define SDRAM_tRP       TRP_2
  52                 #define SDRAM_tRP_num   2
  53                 #define SDRAM_tRAS      TRAS_4
  54                 #define SDRAM_tRAS_num  4
  55                 #define SDRAM_tRCD      TRCD_2
  56                 #define SDRAM_tWR       TWR_2
  57         #endif
  58         #if ( CONFIG_SCLK_HZ >  66666667 ) && ( CONFIG_SCLK_HZ <= 74626866 )
  59                 #define SDRAM_tRP       TRP_2
  60                 #define SDRAM_tRP_num   2
  61                 #define SDRAM_tRAS      TRAS_3
  62                 #define SDRAM_tRAS_num  3
  63                 #define SDRAM_tRCD      TRCD_2
  64                 #define SDRAM_tWR       TWR_2
  65         #endif
  66         #if ( CONFIG_SCLK_HZ >  59701493 ) && ( CONFIG_SCLK_HZ <= 66666667 )
  67                 #define SDRAM_tRP       TRP_1
  68                 #define SDRAM_tRP_num   1
  69                 #define SDRAM_tRAS      TRAS_4
  70                 #define SDRAM_tRAS_num  3
  71                 #define SDRAM_tRCD      TRCD_1
  72                 #define SDRAM_tWR       TWR_2
  73         #endif
  74         #if ( CONFIG_SCLK_HZ >  44776119 ) && ( CONFIG_SCLK_HZ <=  59701493 )
  75                 #define SDRAM_tRP       TRP_1
  76                 #define SDRAM_tRP_num   1
  77                 #define SDRAM_tRAS      TRAS_3
  78                 #define SDRAM_tRAS_num  3
  79                 #define SDRAM_tRCD      TRCD_1
  80                 #define SDRAM_tWR       TWR_2
  81         #endif
  82         #if ( CONFIG_SCLK_HZ >  29850746 ) && ( CONFIG_SCLK_HZ <=  44776119 )
  83                 #define SDRAM_tRP       TRP_1
  84                 #define SDRAM_tRP_num   1
  85                 #define SDRAM_tRAS      TRAS_2
  86                 #define SDRAM_tRAS_num  2
  87                 #define SDRAM_tRCD      TRCD_1
  88                 #define SDRAM_tWR       TWR_2
  89         #endif
  90         #if ( CONFIG_SCLK_HZ <=  29850746 )
  91                 #define SDRAM_tRP       TRP_1
  92                 #define SDRAM_tRP_num   1
  93                 #define SDRAM_tRAS      TRAS_1
  94                 #define SDRAM_tRAS_num  1
  95                 #define SDRAM_tRCD      TRCD_1
  96                 #define SDRAM_tWR       TWR_2
  97         #endif
  98 #endif
  99
 100 #if (CONFIG_MEM_MT48LC16M16A2TG_75)
 101         /*SDRAM INFORMATION: */
 102         #define SDRAM_Tref      64       /* Refresh period in milliseconds   */
 103         #define SDRAM_NRA       8192     /* Number of row addresses in SDRAM */
 104         #define SDRAM_CL        CL_3
 105 #endif
 106
 107 #if (CONFIG_MEM_MT48LC64M4A2FB_7E)
 108         /*SDRAM INFORMATION: */
 109         #define SDRAM_Tref      64       /* Refresh period in milliseconds   */
 110         #define SDRAM_NRA       8192     /* Number of row addresses in SDRAM */
 111         #define SDRAM_CL        CL_2
 112 #endif
 113
 114 #if ( CONFIG_MEM_SIZE == 128 )
 115         #define SDRAM_SIZE      EBSZ_128
 116 #endif
 117 #if ( CONFIG_MEM_SIZE == 64 )
 118         #define SDRAM_SIZE      EBSZ_64
 119 #endif
 120 #if (  CONFIG_MEM_SIZE == 32 )
 121         #define SDRAM_SIZE      EBSZ_32
 122 #endif
 123 #if ( CONFIG_MEM_SIZE == 16 )
 124         #define SDRAM_SIZE      EBSZ_16
 125 #endif
 126 #if ( CONFIG_MEM_ADD_WDTH == 11 )
 127         #define SDRAM_WIDTH     EBCAW_11
 128 #endif
 129 #if ( CONFIG_MEM_ADD_WDTH == 10 )
 130         #define SDRAM_WIDTH     EBCAW_10
 131 #endif
 132 #if ( CONFIG_MEM_ADD_WDTH == 9 )
 133         #define SDRAM_WIDTH     EBCAW_9
 134 #endif
 135 #if ( CONFIG_MEM_ADD_WDTH == 8 )
 136         #define SDRAM_WIDTH     EBCAW_8
 137 #endif
 138
 139 #define mem_SDBCTL      SDRAM_WIDTH | SDRAM_SIZE | EBE
 140
 141 /* Equation from section 17 (p17-46) of BF533 HRM */
 142 #define mem_SDRRC       ((( CONFIG_SCLK_HZ / 1000) * SDRAM_Tref)  / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num)
 143
 144 /* Enable SCLK Out */
 145 #define mem_SDGCTL      ( SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR | PSS )
 146
 147 #define flash_EBIU_AMBCTL_WAT   ( ( CONFIG_FLASH_SPEED_BWAT * 4 )  / ( 4000000000 / CONFIG_SCLK_HZ ) ) + 1
 148 #define flash_EBIU_AMBCTL_RAT   ( ( CONFIG_FLASH_SPEED_BRAT * 4 )  / ( 4000000000 / CONFIG_SCLK_HZ ) ) + 1
 149 #define flash_EBIU_AMBCTL_HT    ( ( CONFIG_FLASH_SPEED_BHT  * 4 )  / ( 4000000000 / CONFIG_SCLK_HZ ) )
 150 #define flash_EBIU_AMBCTL_ST    ( ( CONFIG_FLASH_SPEED_BST  * 4 )  / ( 4000000000 / CONFIG_SCLK_HZ ) ) + 1
 151 #define flash_EBIU_AMBCTL_TT    ( ( CONFIG_FLASH_SPEED_BTT  * 4 )  / ( 4000000000 / CONFIG_SCLK_HZ ) ) + 1
 152
 153 #if (flash_EBIU_AMBCTL_TT > 3 )
 154         #define flash_EBIU_AMBCTL0_TT   B0TT_4
 155 #endif
 156 #if (flash_EBIU_AMBCTL_TT == 3 )
 157         #define flash_EBIU_AMBCTL0_TT   B0TT_3
 158 #endif
 159 #if (flash_EBIU_AMBCTL_TT == 2 )
 160         #define flash_EBIU_AMBCTL0_TT   B0TT_2
 161 #endif
 162 #if (flash_EBIU_AMBCTL_TT < 2 )
 163         #define flash_EBIU_AMBCTL0_TT   B0TT_1
 164 #endif
 165
 166 #if (flash_EBIU_AMBCTL_ST > 3 )
 167         #define flash_EBIU_AMBCTL0_ST   B0ST_4
 168 #endif
 169 #if (flash_EBIU_AMBCTL_ST == 3 )
 170         #define flash_EBIU_AMBCTL0_ST   B0ST_3
 171 #endif
 172 #if (flash_EBIU_AMBCTL_ST == 2 )
 173         #define flash_EBIU_AMBCTL0_ST   B0ST_2
 174 #endif
 175 #if (flash_EBIU_AMBCTL_ST < 2 )
 176         #define flash_EBIU_AMBCTL0_ST   B0ST_1
 177 #endif
 178
 179 #if (flash_EBIU_AMBCTL_HT > 2 )
 180         #define flash_EBIU_AMBCTL0_HT   B0HT_3
 181 #endif
 182 #if (flash_EBIU_AMBCTL_HT == 2 )
 183         #define flash_EBIU_AMBCTL0_HT   B0HT_2
 184 #endif
 185 #if (flash_EBIU_AMBCTL_HT == 1 )
 186         #define flash_EBIU_AMBCTL0_HT   B0HT_1
 187 #endif
 188 #if (flash_EBIU_AMBCTL_HT == 0  && CONFIG_FLASH_SPEED_BHT == 0)
 189         #define flash_EBIU_AMBCTL0_HT   B0HT_0
 190 #endif
 191 #if (flash_EBIU_AMBCTL_HT == 0  && CONFIG_FLASH_SPEED_BHT != 0)
 192         #define flash_EBIU_AMBCTL0_HT   B0HT_1
 193 #endif
 194
 195 #if (flash_EBIU_AMBCTL_WAT > 14)
 196         #define flash_EBIU_AMBCTL0_WAT  B0WAT_15
 197 #endif
 198 #if (flash_EBIU_AMBCTL_WAT == 14)
 199         #define flash_EBIU_AMBCTL0_WAT  B0WAT_14
 200 #endif
 201 #if (flash_EBIU_AMBCTL_WAT == 13)
 202         #define flash_EBIU_AMBCTL0_WAT  B0WAT_13
 203 #endif
 204 #if (flash_EBIU_AMBCTL_WAT == 12)
 205         #define flash_EBIU_AMBCTL0_WAT  B0WAT_12
 206 #endif
 207 #if (flash_EBIU_AMBCTL_WAT == 11)
 208         #define flash_EBIU_AMBCTL0_WAT  B0WAT_11
 209 #endif
 210 #if (flash_EBIU_AMBCTL_WAT == 10)
 211         #define flash_EBIU_AMBCTL0_WAT  B0WAT_10
 212 #endif
 213 #if (flash_EBIU_AMBCTL_WAT == 9)
 214         #define flash_EBIU_AMBCTL0_WAT  B0WAT_9
 215 #endif
 216 #if (flash_EBIU_AMBCTL_WAT == 8)
 217         #define flash_EBIU_AMBCTL0_WAT  B0WAT_8
 218 #endif
 219 #if (flash_EBIU_AMBCTL_WAT == 7)
 220         #define flash_EBIU_AMBCTL0_WAT  B0WAT_7
 221 #endif
 222 #if (flash_EBIU_AMBCTL_WAT == 6)
 223         #define flash_EBIU_AMBCTL0_WAT  B0WAT_6
 224 #endif
 225 #if (flash_EBIU_AMBCTL_WAT == 5)
 226         #define flash_EBIU_AMBCTL0_WAT  B0WAT_5
 227 #endif
 228 #if (flash_EBIU_AMBCTL_WAT == 4)
 229         #define flash_EBIU_AMBCTL0_WAT  B0WAT_4
 230 #endif
 231 #if (flash_EBIU_AMBCTL_WAT == 3)
 232         #define flash_EBIU_AMBCTL0_WAT  B0WAT_3
 233 #endif
 234 #if (flash_EBIU_AMBCTL_WAT == 2)
 235         #define flash_EBIU_AMBCTL0_WAT  B0WAT_2
 236 #endif
 237 #if (flash_EBIU_AMBCTL_WAT == 1)
 238         #define flash_EBIU_AMBCTL0_WAT  B0WAT_1
 239 #endif
 240
 241 #if (flash_EBIU_AMBCTL_RAT > 14)
 242         #define flash_EBIU_AMBCTL0_RAT  B0RAT_15
 243 #endif
 244 #if (flash_EBIU_AMBCTL_RAT == 14)
 245         #define flash_EBIU_AMBCTL0_RAT  B0RAT_14
 246 #endif
 247 #if (flash_EBIU_AMBCTL_RAT == 13)
 248         #define flash_EBIU_AMBCTL0_RAT  B0RAT_13
 249 #endif
 250 #if (flash_EBIU_AMBCTL_RAT == 12)
 251         #define flash_EBIU_AMBCTL0_RAT  B0RAT_12
 252 #endif
 253 #if (flash_EBIU_AMBCTL_RAT == 11)
 254         #define flash_EBIU_AMBCTL0_RAT  B0RAT_11
 255 #endif
 256 #if (flash_EBIU_AMBCTL_RAT == 10)
 257         #define flash_EBIU_AMBCTL0_RAT  B0RAT_10
 258 #endif
 259 #if (flash_EBIU_AMBCTL_RAT == 9)
 260         #define flash_EBIU_AMBCTL0_RAT  B0RAT_9
 261 #endif
 262 #if (flash_EBIU_AMBCTL_RAT == 8)
 263         #define flash_EBIU_AMBCTL0_RAT  B0RAT_8
 264 #endif
 265 #if (flash_EBIU_AMBCTL_RAT == 7)
 266         #define flash_EBIU_AMBCTL0_RAT  B0RAT_7
 267 #endif
 268 #if (flash_EBIU_AMBCTL_RAT == 6)
 269         #define flash_EBIU_AMBCTL0_RAT  B0RAT_6
 270 #endif
 271 #if (flash_EBIU_AMBCTL_RAT == 5)
 272         #define flash_EBIU_AMBCTL0_RAT  B0RAT_5
 273 #endif
 274 #if (flash_EBIU_AMBCTL_RAT == 4)
 275         #define flash_EBIU_AMBCTL0_RAT  B0RAT_4
 276 #endif
 277 #if (flash_EBIU_AMBCTL_RAT == 3)
 278         #define flash_EBIU_AMBCTL0_RAT  B0RAT_3
 279 #endif
 280 #if (flash_EBIU_AMBCTL_RAT == 2)
 281         #define flash_EBIU_AMBCTL0_RAT  B0RAT_2
 282 #endif
 283 #if (flash_EBIU_AMBCTL_RAT == 1)
 284         #define flash_EBIU_AMBCTL0_RAT  B0RAT_1
 285 #endif
 286
 287 #define flash_EBIU_AMBCTL0      flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN