include/asm-ppc/cache.h

   1 /*
   2  * include/asm-ppc/cache.h
   3  */
   4 #ifndef __ARCH_PPC_CACHE_H
   5 #define __ARCH_PPC_CACHE_H
   6
   7 #include <linux/config.h>
   8 #include <asm/processor.h>
   9
  10 /* bytes per L1 cache line */
  11 #if !defined(CONFIG_8xx) || defined(CONFIG_8260)
  12 #if defined(CONFIG_PPC64BRIDGE)
  13 #define L1_CACHE_BYTES  128
  14 #else
  15 #define L1_CACHE_BYTES  32
  16 #endif /* PPC64 */
  17 #else
  18 #define L1_CACHE_BYTES  16
  19 #endif /* !8xx || 8260 */
  20
  21 #define L1_CACHE_ALIGN(x)       (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1))
  22 #define L1_CACHE_PAGES          8
  23
  24 #define SMP_CACHE_BYTES L1_CACHE_BYTES
  25
  26 #ifdef MODULE
  27 #define __cacheline_aligned __attribute__((__aligned__(L1_CACHE_BYTES)))
  28 #else
  29 #define __cacheline_aligned                                     \
  30   __attribute__((__aligned__(L1_CACHE_BYTES),                   \
  31                  __section__(".data.cacheline_aligned")))
  32 #endif
  33
  34 #if defined(__KERNEL__) && !defined(__ASSEMBLY__)
  35 extern void flush_dcache_range(unsigned long start, unsigned long stop);
  36 extern void clean_dcache_range(unsigned long start, unsigned long stop);
  37 extern void invalidate_dcache_range(unsigned long start, unsigned long stop);
  38 #ifdef CFG_INIT_RAM_LOCK
  39 extern void unlock_ram_in_cache(void);
  40 #endif /* CFG_INIT_RAM_LOCK */
  41 #endif /* __ASSEMBLY__ */
  42
  43 /* prep registers for L2 */
  44 #define CACHECRBA       0x80000823      /* Cache configuration register address */
  45 #define L2CACHE_MASK    0x03    /* Mask for 2 L2 Cache bits */
  46 #define L2CACHE_512KB   0x00    /* 512KB */
  47 #define L2CACHE_256KB   0x01    /* 256KB */
  48 #define L2CACHE_1MB     0x02    /* 1MB */
  49 #define L2CACHE_NONE    0x03    /* NONE */
  50 #define L2CACHE_PARITY  0x08    /* Mask for L2 Cache Parity Protected bit */
  51
  52 #ifdef CONFIG_8xx
  53 /* Cache control on the MPC8xx is provided through some additional
  54  * special purpose registers.
  55  */
  56 #define IC_CST          560     /* Instruction cache control/status */
  57 #define IC_ADR          561     /* Address needed for some commands */
  58 #define IC_DAT          562     /* Read-only data register */
  59 #define DC_CST          568     /* Data cache control/status */
  60 #define DC_ADR          569     /* Address needed for some commands */
  61 #define DC_DAT          570     /* Read-only data register */
  62
  63 /* Commands.  Only the first few are available to the instruction cache.
  64 */
  65 #define IDC_ENABLE      0x02000000      /* Cache enable */
  66 #define IDC_DISABLE     0x04000000      /* Cache disable */
  67 #define IDC_LDLCK       0x06000000      /* Load and lock */
  68 #define IDC_UNLINE      0x08000000      /* Unlock line */
  69 #define IDC_UNALL       0x0a000000      /* Unlock all */
  70 #define IDC_INVALL      0x0c000000      /* Invalidate all */
  71
  72 #define DC_FLINE        0x0e000000      /* Flush data cache line */
  73 #define DC_SFWT         0x01000000      /* Set forced writethrough mode */
  74 #define DC_CFWT         0x03000000      /* Clear forced writethrough mode */
  75 #define DC_SLES         0x05000000      /* Set little endian swap mode */
  76 #define DC_CLES         0x07000000      /* Clear little endian swap mode */
  77
  78 /* Status.
  79 */
  80 #define IDC_ENABLED     0x80000000      /* Cache is enabled */
  81 #define IDC_CERR1       0x00200000      /* Cache error 1 */
  82 #define IDC_CERR2       0x00100000      /* Cache error 2 */
  83 #define IDC_CERR3       0x00080000      /* Cache error 3 */
  84
  85 #define DC_DFWT         0x40000000      /* Data cache is forced write through */
  86 #define DC_LES          0x20000000      /* Caches are little endian mode */
  87 #endif /* CONFIG_8xx */
  88
  89 #endif