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to make u-boot work for fat32 filesystem
[jz_uboot.git] / include / asm-ppc / immap_86xx.h
bloba5552c48ee904d4b368433625020e067edb4827b
1 /*
2 * MPC86xx Internal Memory Map
3 *
4 * Copyright(c) 2004 Freescale Semiconductor
5 * Jeff Brown (Jeffrey@freescale.com)
6 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
7 *
8 */
9
10 #ifndef __IMMAP_86xx__
11 #define __IMMAP_86xx__
12
13 #include <asm/types.h>
14 #include <asm/fsl_i2c.h>
15
16 /* Local-Access Registers and MCM Registers(0x0000-0x2000) */
17 typedef struct ccsr_local_mcm {
18 uint ccsrbar; /* 0x0 - Control Configuration Status Registers Base Address Register */
19 char res1[4];
20 uint altcbar; /* 0x8 - Alternate Configuration Base Address Register */
21 char res2[4];
22 uint altcar; /* 0x10 - Alternate Configuration Attribute Register */
23 char res3[12];
24 uint bptr; /* 0x20 - Boot Page Translation Register */
25 char res4[3044];
26 uint lawbar0; /* 0xc08 - Local Access Window 0 Base Address Register */
27 char res5[4];
28 uint lawar0; /* 0xc10 - Local Access Window 0 Attributes Register */
29 char res6[20];
30 uint lawbar1; /* 0xc28 - Local Access Window 1 Base Address Register */
31 char res7[4];
32 uint lawar1; /* 0xc30 - Local Access Window 1 Attributes Register */
33 char res8[20];
34 uint lawbar2; /* 0xc48 - Local Access Window 2 Base Address Register */
35 char res9[4];
36 uint lawar2; /* 0xc50 - Local Access Window 2 Attributes Register */
37 char res10[20];
38 uint lawbar3; /* 0xc68 - Local Access Window 3 Base Address Register */
39 char res11[4];
40 uint lawar3; /* 0xc70 - Local Access Window 3 Attributes Register */
41 char res12[20];
42 uint lawbar4; /* 0xc88 - Local Access Window 4 Base Address Register */
43 char res13[4];
44 uint lawar4; /* 0xc90 - Local Access Window 4 Attributes Register */
45 char res14[20];
46 uint lawbar5; /* 0xca8 - Local Access Window 5 Base Address Register */
47 char res15[4];
48 uint lawar5; /* 0xcb0 - Local Access Window 5 Attributes Register */
49 char res16[20];
50 uint lawbar6; /* 0xcc8 - Local Access Window 6 Base Address Register */
51 char res17[4];
52 uint lawar6; /* 0xcd0 - Local Access Window 6 Attributes Register */
53 char res18[20];
54 uint lawbar7; /* 0xce8 - Local Access Window 7 Base Address Register */
55 char res19[4];
56 uint lawar7; /* 0xcf0 - Local Access Window 7 Attributes Register */
57 char res20[20];
58 uint lawbar8; /* 0xd08 - Local Access Window 8 Base Address Register */
59 char res21[4];
60 uint lawar8; /* 0xd10 - Local Access Window 8 Attributes Register */
61 char res22[20];
62 uint lawbar9; /* 0xd28 - Local Access Window 9 Base Address Register */
63 char res23[4];
64 uint lawar9; /* 0xd30 - Local Access Window 9 Attributes Register */
65 char res24[716];
66 uint abcr; /* 0x1000 - MCM CCB Address Configuration Register */
67 char res25[4];
68 uint dbcr; /* 0x1008 - MCM MPX data bus Configuration Register */
69 char res26[4];
70 uint pcr; /* 0x1010 - MCM CCB Port Configuration Register */
71 char res27[44];
72 uint hpmr0; /* 0x1040 - MCM HPM Threshold Count Register 0 */
73 uint hpmr1; /* 0x1044 - MCM HPM Threshold Count Register 1 */
74 uint hpmr2; /* 0x1048 - MCM HPM Threshold Count Register 2 */
75 uint hpmr3; /* 0x104c - MCM HPM Threshold Count Register 3 */
76 char res28[16];
77 uint hpmr4; /* 0x1060 - MCM HPM Threshold Count Register 4 */
78 uint hpmr5; /* 0x1064 - MCM HPM Threshold Count Register 5 */
79 uint hpmccr; /* 0x1068 - MCM HPM Cycle Count Register */
80 char res29[3476];
81 uint edr; /* 0x1e00 - MCM Error Detect Register */
82 char res30[4];
83 uint eer; /* 0x1e08 - MCM Error Enable Register */
84 uint eatr; /* 0x1e0c - MCM Error Attributes Capture Register */
85 uint eladr; /* 0x1e10 - MCM Error Low Address Capture Register */
86 uint ehadr; /* 0x1e14 - MCM Error High Address Capture Register */
87 char res31[488];
88 } ccsr_local_mcm_t;
89
90 /* DDR memory controller registers(0x2000-0x3000) and (0x6000-0x7000) */
91
92 typedef struct ccsr_ddr {
93 uint cs0_bnds; /* 0x2000 - DDR Chip Select 0 Memory Bounds */
94 char res1[4];
95 uint cs1_bnds; /* 0x2008 - DDR Chip Select 1 Memory Bounds */
96 char res2[4];
97 uint cs2_bnds; /* 0x2010 - DDR Chip Select 2 Memory Bounds */
98 char res3[4];
99 uint cs3_bnds; /* 0x2018 - DDR Chip Select 3 Memory Bounds */
100 char res4[4];
101 uint cs4_bnds; /* 0x2020 - DDR Chip Select 4 Memory Bounds */
102 char res5[4];
103 uint cs5_bnds; /* 0x2028 - DDR Chip Select 5 Memory Bounds */
104 char res6[84];
105 uint cs0_config; /* 0x2080 - DDR Chip Select Configuration */
106 uint cs1_config; /* 0x2084 - DDR Chip Select Configuration */
107 uint cs2_config; /* 0x2088 - DDR Chip Select Configuration */
108 uint cs3_config; /* 0x208c - DDR Chip Select Configuration */
109 uint cs4_config; /* 0x2090 - DDR Chip Select Configuration */
110 uint cs5_config; /* 0x2094 - DDR Chip Select Configuration */
111 char res7[104];
112 uint ext_refrec; /* 0x2100 - DDR SDRAM extended refresh recovery */
113 uint timing_cfg_0; /* 0x2104 - DDR SDRAM Timing Configuration Register 0 */
114 uint timing_cfg_1; /* 0x2108 - DDR SDRAM Timing Configuration Register 1 */
115 uint timing_cfg_2; /* 0x210c - DDR SDRAM Timing Configuration Register 2 */
116 uint sdram_cfg_1; /* 0x2110 - DDR SDRAM Control Configuration 1 */
117 uint sdram_cfg_2; /* 0x2114 - DDR SDRAM Control Configuration 2 */
118 uint sdram_mode_1; /* 0x2118 - DDR SDRAM Mode Configuration 1 */
119 uint sdram_mode_2; /* 0x211c - DDR SDRAM Mode Configuration 2 */
120 uint sdram_mode_cntl; /* 0x2120 - DDR SDRAM Mode Control */
121 uint sdram_interval; /* 0x2124 - DDR SDRAM Interval Configuration */
122 uint sdram_data_init; /* 0x2128 - DDR SDRAM Data Initialization */
123 char res8[4];
124 uint sdram_clk_cntl; /* 0x2130 - DDR SDRAM Clock Control */
125 char res9[12];
126 uint sdram_ocd_cntl; /* 0x2140 - DDR SDRAM OCD Control */
127 uint sdram_ocd_status; /* 0x2144 - DDR SDRAM OCD Status */
128 uint init_addr; /* 0x2148 - DDR training initialzation address */
129 uint init_addr_ext; /* 0x214C - DDR training initialzation extended address */
130 char res10[2728];
131 uint ip_rev1; /* 0x2BF8 - DDR IP Block Revision 1 */
132 uint ip_rev2; /* 0x2BFC - DDR IP Block Revision 2 */
133 char res11[512];
134 uint data_err_inject_hi; /* 0x2e00 - DDR Memory Data Path Error Injection Mask High */
135 uint data_err_inject_lo; /* 0x2e04 - DDR Memory Data Path Error Injection Mask Low */
136 uint ecc_err_inject; /* 0x2e08 - DDR Memory Data Path Error Injection Mask ECC */
137 char res12[20];
138 uint capture_data_hi; /* 0x2e20 - DDR Memory Data Path Read Capture High */
139 uint capture_data_lo; /* 0x2e24 - DDR Memory Data Path Read Capture Low */
140 uint capture_ecc; /* 0x2e28 - DDR Memory Data Path Read Capture ECC */
141 char res13[20];
142 uint err_detect; /* 0x2e40 - DDR Memory Error Detect */
143 uint err_disable; /* 0x2e44 - DDR Memory Error Disable */
144 uint err_int_en; /* 0x2e48 - DDR Memory Error Interrupt Enable */
145 uint capture_attributes; /* 0x2e4c - DDR Memory Error Attributes Capture */
146 uint capture_address; /* 0x2e50 - DDR Memory Error Address Capture */
147 uint capture_ext_address; /* 0x2e54 - DDR Memory Error Extended Address Capture */
148 uint err_sbe; /* 0x2e58 - DDR Memory Single-Bit ECC Error Management */
149 char res14[164];
150 uint debug_1; /* 0x2f00 */
151 uint debug_2;
152 uint debug_3;
153 uint debug_4;
154 uint debug_5;
155 char res15[236];
156 } ccsr_ddr_t;
157
158
159 /* Daul I2C Registers(0x3000-0x4000) */
160 typedef struct ccsr_i2c {
161 struct fsl_i2c i2c[2];
162 u8 res[4096 - 2 * sizeof(struct fsl_i2c)];
163 } ccsr_i2c_t;
164
165 /* DUART Registers(0x4000-0x5000) */
166 typedef struct ccsr_duart {
167 char res1[1280];
168 u_char urbr1_uthr1_udlb1;/* 0x4500 - URBR1, UTHR1, UDLB1 with the same address offset of 0x04500 */
169 u_char uier1_udmb1; /* 0x4501 - UIER1, UDMB1 with the same address offset of 0x04501 */
170 u_char uiir1_ufcr1_uafr1;/* 0x4502 - UIIR1, UFCR1, UAFR1 with the same address offset of 0x04502 */
171 u_char ulcr1; /* 0x4503 - UART1 Line Control Register */
172 u_char umcr1; /* 0x4504 - UART1 Modem Control Register */
173 u_char ulsr1; /* 0x4505 - UART1 Line Status Register */
174 u_char umsr1; /* 0x4506 - UART1 Modem Status Register */
175 u_char uscr1; /* 0x4507 - UART1 Scratch Register */
176 char res2[8];
177 u_char udsr1; /* 0x4510 - UART1 DMA Status Register */
178 char res3[239];
179 u_char urbr2_uthr2_udlb2;/* 0x4600 - URBR2, UTHR2, UDLB2 with the same address offset of 0x04600 */
180 u_char uier2_udmb2; /* 0x4601 - UIER2, UDMB2 with the same address offset of 0x04601 */
181 u_char uiir2_ufcr2_uafr2;/* 0x4602 - UIIR2, UFCR2, UAFR2 with the same address offset of 0x04602 */
182 u_char ulcr2; /* 0x4603 - UART2 Line Control Register */
183 u_char umcr2; /* 0x4604 - UART2 Modem Control Register */
184 u_char ulsr2; /* 0x4605 - UART2 Line Status Register */
185 u_char umsr2; /* 0x4606 - UART2 Modem Status Register */
186 u_char uscr2; /* 0x4607 - UART2 Scratch Register */
187 char res4[8];
188 u_char udsr2; /* 0x4610 - UART2 DMA Status Register */
189 char res5[2543];
190 } ccsr_duart_t;
191
192
193 /* Local Bus Controller Registers(0x5000-0x6000) */
194 typedef struct ccsr_lbc {
195 uint br0; /* 0x5000 - LBC Base Register 0 */
196 uint or0; /* 0x5004 - LBC Options Register 0 */
197 uint br1; /* 0x5008 - LBC Base Register 1 */
198 uint or1; /* 0x500c - LBC Options Register 1 */
199 uint br2; /* 0x5010 - LBC Base Register 2 */
200 uint or2; /* 0x5014 - LBC Options Register 2 */
201 uint br3; /* 0x5018 - LBC Base Register 3 */
202 uint or3; /* 0x501c - LBC Options Register 3 */
203 uint br4; /* 0x5020 - LBC Base Register 4 */
204 uint or4; /* 0x5024 - LBC Options Register 4 */
205 uint br5; /* 0x5028 - LBC Base Register 5 */
206 uint or5; /* 0x502c - LBC Options Register 5 */
207 uint br6; /* 0x5030 - LBC Base Register 6 */
208 uint or6; /* 0x5034 - LBC Options Register 6 */
209 uint br7; /* 0x5038 - LBC Base Register 7 */
210 uint or7; /* 0x503c - LBC Options Register 7 */
211 char res1[40];
212 uint mar; /* 0x5068 - LBC UPM Address Register */
213 char res2[4];
214 uint mamr; /* 0x5070 - LBC UPMA Mode Register */
215 uint mbmr; /* 0x5074 - LBC UPMB Mode Register */
216 uint mcmr; /* 0x5078 - LBC UPMC Mode Register */
217 char res3[8];
218 uint mrtpr; /* 0x5084 - LBC Memory Refresh Timer Prescaler Register */
219 uint mdr; /* 0x5088 - LBC UPM Data Register */
220 char res4[8];
221 uint lsdmr; /* 0x5094 - LBC SDRAM Mode Register */
222 char res5[8];
223 uint lurt; /* 0x50a0 - LBC UPM Refresh Timer */
224 uint lsrt; /* 0x50a4 - LBC SDRAM Refresh Timer */
225 char res6[8];
226 uint ltesr; /* 0x50b0 - LBC Transfer Error Status Register */
227 uint ltedr; /* 0x50b4 - LBC Transfer Error Disable Register */
228 uint lteir; /* 0x50b8 - LBC Transfer Error Interrupt Register */
229 uint lteatr; /* 0x50bc - LBC Transfer Error Attributes Register */
230 uint ltear; /* 0x50c0 - LBC Transfer Error Address Register */
231 char res7[12];
232 uint lbcr; /* 0x50d0 - LBC Configuration Register */
233 uint lcrr; /* 0x50d4 - LBC Clock Ratio Register */
234 char res8[3880];
235 } ccsr_lbc_t;
236
237 /* PCI Express Registers(0x8000-0x9000) and (0x9000-0xA000) */
238 typedef struct ccsr_pex {
239 uint cfg_addr; /* 0x8000 - PEX Configuration Address Register */
240 uint cfg_data; /* 0x8004 - PEX Configuration Data Register */
241 char res1[4];
242 uint out_comp_to; /* 0x800C - PEX Outbound Completion Timeout Register */
243 char res2[16];
244 uint pme_msg_det; /* 0x8020 - PEX PME & message detect register */
245 uint pme_msg_int_en; /* 0x8024 - PEX PME & message interrupt enable register */
246 uint pme_msg_dis; /* 0x8028 - PEX PME & message disable register */
247 uint pm_command; /* 0x802c - PEX PM Command register */
248 char res3[3016];
249 uint block_rev1; /* 0x8bf8 - PEX Block Revision register 1 */
250 uint block_rev2; /* 0x8bfc - PEX Block Revision register 2 */
251 uint potar0; /* 0x8c00 - PEX Outbound Transaction Address Register 0 */
252 uint potear0; /* 0x8c04 - PEX Outbound Translation Extended Address Register 0 */
253 char res4[8];
254 uint powar0; /* 0x8c10 - PEX Outbound Window Attributes Register 0 */
255 char res5[12];
256 uint potar1; /* 0x8c20 - PEX Outbound Transaction Address Register 1 */
257 uint potear1; /* 0x8c24 - PEX Outbound Translation Extended Address Register 1 */
258 uint powbar1; /* 0x8c28 - PEX Outbound Window Base Address Register 1 */
259 char res6[4];
260 uint powar1; /* 0x8c30 - PEX Outbound Window Attributes Register 1 */
261 char res7[12];
262 uint potar2; /* 0x8c40 - PEX Outbound Transaction Address Register 2 */
263 uint potear2; /* 0x8c44 - PEX Outbound Translation Extended Address Register 2 */
264 uint powbar2; /* 0x8c48 - PEX Outbound Window Base Address Register 2 */
265 char res8[4];
266 uint powar2; /* 0x8c50 - PEX Outbound Window Attributes Register 2 */
267 char res9[12];
268 uint potar3; /* 0x8c60 - PEX Outbound Transaction Address Register 3 */
269 uint potear3; /* 0x8c64 - PEX Outbound Translation Extended Address Register 3 */
270 uint powbar3; /* 0x8c68 - PEX Outbound Window Base Address Register 3 */
271 char res10[4];
272 uint powar3; /* 0x8c70 - PEX Outbound Window Attributes Register 3 */
273 char res11[12];
274 uint potar4; /* 0x8c80 - PEX Outbound Transaction Address Register 4 */
275 uint potear4; /* 0x8c84 - PEX Outbound Translation Extended Address Register 4 */
276 uint powbar4; /* 0x8c88 - PEX Outbound Window Base Address Register 4 */
277 char res12[4];
278 uint powar4; /* 0x8c90 - PEX Outbound Window Attributes Register 4 */
279 char res13[12];
280 char res14[256];
281 uint pitar3; /* 0x8da0 - PEX Inbound Translation Address Register 3 */
282 char res15[4];
283 uint piwbar3; /* 0x8da8 - PEX Inbound Window Base Address Register 3 */
284 uint piwbear3; /* 0x8dac - PEX Inbound Window Base Extended Address Register 3 */
285 uint piwar3; /* 0x8db0 - PEX Inbound Window Attributes Register 3 */
286 char res16[12];
287 uint pitar2; /* 0x8dc0 - PEX Inbound Translation Address Register 2 */
288 char res17[4];
289 uint piwbar2; /* 0x8dc8 - PEX Inbound Window Base Address Register 2 */
290 uint piwbear2; /* 0x8dcc - PEX Inbound Window Base Extended Address Register 2 */
291 uint piwar2; /* 0x8dd0 - PEX Inbound Window Attributes Register 2 */
292 char res18[12];
293 uint pitar1; /* 0x8de0 - PEX Inbound Translation Address Register 1 */
294 char res19[4];
295 uint piwbar1; /* 0x8de8 - PEX Inbound Window Base Address Register 1 */
296 uint piwbear1;
297 uint piwar1; /* 0x8df0 - PEX Inbound Window Attributes Register 1 */
298 char res20[12];
299 uint pedr; /* 0x8e00 - PEX Error Detect Register */
300 char res21[4];
301 uint peer; /* 0x8e08 - PEX Error Interrupt Enable Register */
302 char res22[4];
303 uint pecdr; /* 0x8e10 - PEX Error Disable Register */
304 char res23[12];
305 uint peer_stat; /* 0x8e20 - PEX Error Capture Status Register */
306 char res24[4];
307 uint perr_cap0; /* 0x8e28 - PEX Error Capture Register 0 */
308 uint perr_cap1; /* 0x8e2c - PEX Error Capture Register 1 */
309 uint perr_cap2; /* 0x8e30 - PEX Error Capture Register 2 */
310 uint perr_cap3; /* 0x8e34 - PEX Error Capture Register 3 */
311 char res25[452];
312 char res26[4];
313 } ccsr_pex_t;
314
315 /* Hyper Transport Register Block (0xA000-0xB000) */
316 typedef struct ccsr_ht {
317 uint hcfg_addr; /* 0xa000 - HT Configuration Address register */
318 uint hcfg_data; /* 0xa004 - HT Configuration Data register */
319 char res1[3064];
320 uint howtar0; /* 0xac00 - HT Outbound Window 0 Translation register */
321 char res2[12];
322 uint howar0; /* 0xac10 - HT Outbound Window 0 Attributes register */
323 char res3[12];
324 uint howtar1; /* 0xac20 - HT Outbound Window 1 Translation register */
325 char res4[4];
326 uint howbar1; /* 0xac28 - HT Outbound Window 1 Base Address register */
327 char res5[4];
328 uint howar1; /* 0xac30 - HT Outbound Window 1 Attributes register */
329 char res6[12];
330 uint howtar2; /* 0xac40 - HT Outbound Window 2 Translation register */
331 char res7[4];
332 uint howbar2; /* 0xac48 - HT Outbound Window 2 Base Address register */
333 char res8[4];
334 uint howar2; /* 0xac50 - HT Outbound Window 2 Attributes register */
335 char res9[12];
336 uint howtar3; /* 0xac60 - HT Outbound Window 3 Translation register */
337 char res10[4];
338 uint howbar3; /* 0xac68 - HT Outbound Window 3 Base Address register */
339 char res11[4];
340 uint howar3; /* 0xac70 - HT Outbound Window 3 Attributes register */
341 char res12[12];
342 uint howtar4; /* 0xac80 - HT Outbound Window 4 Translation register */
343 char res13[4];
344 uint howbar4; /* 0xac88 - HT Outbound Window 4 Base Address register */
345 char res14[4];
346 uint howar4; /* 0xac90 - HT Outbound Window 4 Attributes register */
347 char res15[236];
348 uint hiwtar4; /* 0xad80 - HT Inbound Window 4 Translation register */
349 char res16[4];
350 uint hiwbar4; /* 0xad88 - HT Inbound Window 4 Base Address register */
351 char res17[4];
352 uint hiwar4; /* 0xad90 - HT Inbound Window 4 Attributes register */
353 char res18[12];
354 uint hiwtar3; /* 0xada0 - HT Inbound Window 3 Translation register */
355 char res19[4];
356 uint hiwbar3; /* 0xada8 - HT Inbound Window 3 Base Address register */
357 char res20[4];
358 uint hiwar3; /* 0xadb0 - HT Inbound Window 3 Attributes register */
359 char res21[12];
360 uint hiwtar2; /* 0xadc0 - HT Inbound Window 2 Translation register */
361 char res22[4];
362 uint hiwbar2; /* 0xadc8 - HT Inbound Window 2 Base Address register */
363 char res23[4];
364 uint hiwar2; /* 0xadd0 - HT Inbound Window 2 Attributes register */
365 char res24[12];
366 uint hiwtar1; /* 0xade0 - HT Inbound Window 1 Translation register */
367 char res25[4];
368 uint hiwbar1; /* 0xade8 - HT Inbound Window 1 Base Address register */
369 char res26[4];
370 uint hiwar1; /* 0xadf0 - HT Inbound Window 1 Attributes register */
371 char res27[12];
372 uint hedr; /* 0xae00 - HT Error Detect register */
373 char res28[4];
374 uint heier; /* 0xae08 - HT Error Interrupt Enable register */
375 char res29[4];
376 uint hecdr; /* 0xae10 - HT Error Capture Disbale register */
377 char res30[12];
378 uint hecsr; /* 0xae20 - HT Error Capture Status register */
379 char res31[4];
380 uint hec0; /* 0xae28 - HT Error Capture 0 register */
381 uint hec1; /* 0xae2c - HT Error Capture 1 register */
382 uint hec2; /* 0xae30 - HT Error Capture 2 register */
383 char res32[460];
384 } ccsr_ht_t;
385
386 /* DMA Registers(0x2_1000-0x2_2000) */
387 typedef struct ccsr_dma {
388 char res1[256];
389 uint mr0; /* 0x21100 - DMA 0 Mode Register */
390 uint sr0; /* 0x21104 - DMA 0 Status Register */
391 char res2[4];
392 uint clndar0; /* 0x2110c - DMA 0 Current Link Descriptor Address Register */
393 uint satr0; /* 0x21110 - DMA 0 Source Attributes Register */
394 uint sar0; /* 0x21114 - DMA 0 Source Address Register */
395 uint datr0; /* 0x21118 - DMA 0 Destination Attributes Register */
396 uint dar0; /* 0x2111c - DMA 0 Destination Address Register */
397 uint bcr0; /* 0x21120 - DMA 0 Byte Count Register */
398 char res3[4];
399 uint nlndar0; /* 0x21128 - DMA 0 Next Link Descriptor Address Register */
400 char res4[8];
401 uint clabdar0; /* 0x21134 - DMA 0 Current List - Alternate Base Descriptor Address Register */
402 char res5[4];
403 uint nlsdar0; /* 0x2113c - DMA 0 Next List Descriptor Address Register */
404 uint ssr0; /* 0x21140 - DMA 0 Source Stride Register */
405 uint dsr0; /* 0x21144 - DMA 0 Destination Stride Register */
406 char res6[56];
407 uint mr1; /* 0x21180 - DMA 1 Mode Register */
408 uint sr1; /* 0x21184 - DMA 1 Status Register */
409 char res7[4];
410 uint clndar1; /* 0x2118c - DMA 1 Current Link Descriptor Address Register */
411 uint satr1; /* 0x21190 - DMA 1 Source Attributes Register */
412 uint sar1; /* 0x21194 - DMA 1 Source Address Register */
413 uint datr1; /* 0x21198 - DMA 1 Destination Attributes Register */
414 uint dar1; /* 0x2119c - DMA 1 Destination Address Register */
415 uint bcr1; /* 0x211a0 - DMA 1 Byte Count Register */
416 char res8[4];
417 uint nlndar1; /* 0x211a8 - DMA 1 Next Link Descriptor Address Register */
418 char res9[8];
419 uint clabdar1; /* 0x211b4 - DMA 1 Current List - Alternate Base Descriptor Address Register */
420 char res10[4];
421 uint nlsdar1; /* 0x211bc - DMA 1 Next List Descriptor Address Register */
422 uint ssr1; /* 0x211c0 - DMA 1 Source Stride Register */
423 uint dsr1; /* 0x211c4 - DMA 1 Destination Stride Register */
424 char res11[56];
425 uint mr2; /* 0x21200 - DMA 2 Mode Register */
426 uint sr2; /* 0x21204 - DMA 2 Status Register */
427 char res12[4];
428 uint clndar2; /* 0x2120c - DMA 2 Current Link Descriptor Address Register */
429 uint satr2; /* 0x21210 - DMA 2 Source Attributes Register */
430 uint sar2; /* 0x21214 - DMA 2 Source Address Register */
431 uint datr2; /* 0x21218 - DMA 2 Destination Attributes Register */
432 uint dar2; /* 0x2121c - DMA 2 Destination Address Register */
433 uint bcr2; /* 0x21220 - DMA 2 Byte Count Register */
434 char res13[4];
435 uint nlndar2; /* 0x21228 - DMA 2 Next Link Descriptor Address Register */
436 char res14[8];
437 uint clabdar2; /* 0x21234 - DMA 2 Current List - Alternate Base Descriptor Address Register */
438 char res15[4];
439 uint nlsdar2; /* 0x2123c - DMA 2 Next List Descriptor Address Register */
440 uint ssr2; /* 0x21240 - DMA 2 Source Stride Register */
441 uint dsr2; /* 0x21244 - DMA 2 Destination Stride Register */
442 char res16[56];
443 uint mr3; /* 0x21280 - DMA 3 Mode Register */
444 uint sr3; /* 0x21284 - DMA 3 Status Register */
445 char res17[4];
446 uint clndar3; /* 0x2128c - DMA 3 Current Link Descriptor Address Register */
447 uint satr3; /* 0x21290 - DMA 3 Source Attributes Register */
448 uint sar3; /* 0x21294 - DMA 3 Source Address Register */
449 uint datr3; /* 0x21298 - DMA 3 Destination Attributes Register */
450 uint dar3; /* 0x2129c - DMA 3 Destination Address Register */
451 uint bcr3; /* 0x212a0 - DMA 3 Byte Count Register */
452 char res18[4];
453 uint nlndar3; /* 0x212a8 - DMA 3 Next Link Descriptor Address Register */
454 char res19[8];
455 uint clabdar3; /* 0x212b4 - DMA 3 Current List - Alternate Base Descriptor Address Register */
456 char res20[4];
457 uint nlsdar3; /* 0x212bc - DMA 3 Next List Descriptor Address Register */
458 uint ssr3; /* 0x212c0 - DMA 3 Source Stride Register */
459 uint dsr3; /* 0x212c4 - DMA 3 Destination Stride Register */
460 char res21[56];
461 uint dgsr; /* 0x21300 - DMA General Status Register */
462 char res22[3324];
463 } ccsr_dma_t;
464
465 /* tsec1-4: 24000-28000 */
466 typedef struct ccsr_tsec {
467 uint id; /* 0x24000 - Controller ID Register */
468 char res1[12];
469 uint ievent; /* 0x24010 - Interrupt Event Register */
470 uint imask; /* 0x24014 - Interrupt Mask Register */
471 uint edis; /* 0x24018 - Error Disabled Register */
472 char res2[4];
473 uint ecntrl; /* 0x24020 - Ethernet Control Register */
474 char res2_1[4];
475 uint ptv; /* 0x24028 - Pause Time Value Register */
476 uint dmactrl; /* 0x2402c - DMA Control Register */
477 uint tbipa; /* 0x24030 - TBI PHY Address Register */
478 char res3[88];
479 uint fifo_tx_thr; /* 0x2408c - FIFO transmit threshold register */
480 char res4[8];
481 uint fifo_tx_starve; /* 0x24098 - FIFO transmit starve register */
482 uint fifo_tx_starve_shutoff;/* 0x2409c - FIFO transmit starve shutoff register */
483 char res4_1[4];
484 uint fifo_rx_pause; /* 0x240a4 - FIFO receive pause threshold register */
485 uint fifo_rx_alarm; /* 0x240a8 - FIFO receive alarm threshold register */
486 char res5[84];
487 uint tctrl; /* 0x24100 - Transmit Control Register */
488 uint tstat; /* 0x24104 - Transmit Status Register */
489 uint dfvlan; /* 0x24108 - Default VLAN control word */
490 char res6[4];
491 uint txic; /* 0x24110 - Transmit interrupt coalescing Register */
492 uint tqueue; /* 0x24114 - Transmit Queue Control Register */
493 char res7[40];
494 uint tr03wt; /* 0x24140 - TxBD Rings 0-3 round-robin weightings */
495 uint tw47wt; /* 0x24144 - TxBD Rings 4-7 round-robin weightings */
496 char res8[52];
497 uint tbdbph; /* 0x2417c - Transmit Data Buffer Pointer High Register */
498 char res9[4];
499 uint tbptr0; /* 0x24184 - Transmit Buffer Descriptor Pointer for Ring 0 */
500 char res10[4];
501 uint tbptr1; /* 0x2418C - Transmit Buffer Descriptor Pointer for Ring 1 */
502 char res11[4];
503 uint tbptr2; /* 0x24194 - Transmit Buffer Descriptor Pointer for Ring 2 */
504 char res12[4];
505 uint tbptr3; /* 0x2419C - Transmit Buffer Descriptor Pointer for Ring 3 */
506 char res13[4];
507 uint tbptr4; /* 0x241A4 - Transmit Buffer Descriptor Pointer for Ring 4 */
508 char res14[4];
509 uint tbptr5; /* 0x241AC - Transmit Buffer Descriptor Pointer for Ring 5 */
510 char res15[4];
511 uint tbptr6; /* 0x241B4 - Transmit Buffer Descriptor Pointer for Ring 6 */
512 char res16[4];
513 uint tbptr7; /* 0x241BC - Transmit Buffer Descriptor Pointer for Ring 7 */
514 char res17[64];
515 uint tbaseh; /* 0x24200 - Transmit Descriptor Base Address High Register */
516 uint tbase0; /* 0x24204 - Transmit Descriptor Base Address Register of Ring 0 */
517 char res18[4];
518 uint tbase1; /* 0x2420C - Transmit Descriptor base address of Ring 1 */
519 char res19[4];
520 uint tbase2; /* 0x24214 - Transmit Descriptor base address of Ring 2 */
521 char res20[4];
522 uint tbase3; /* 0x2421C - Transmit Descriptor base address of Ring 3 */
523 char res21[4];
524 uint tbase4; /* 0x24224 - Transmit Descriptor base address of Ring 4 */
525 char res22[4];
526 uint tbase5; /* 0x2422C - Transmit Descriptor base address of Ring 5 */
527 char res23[4];
528 uint tbase6; /* 0x24234 - Transmit Descriptor base address of Ring 6 */
529 char res24[4];
530 uint tbase7; /* 0x2423C - Transmit Descriptor base address of Ring 7 */
531 char res25[192];
532 uint rctrl; /* 0x24300 - Receive Control Register */
533 uint rstat; /* 0x24304 - Receive Status Register */
534 char res26[8];
535 uint rxic; /* 0x24310 - Receive Interrupt Coalecing Register */
536 uint rqueue; /* 0x24314 - Receive queue control register */
537 char res27[24];
538 uint rbifx; /* 0x24330 - Receive bit field extract control Register */
539 uint rqfar; /* 0x24334 - Receive queue filing table address Register */
540 uint rqfcr; /* 0x24338 - Receive queue filing table control Register */
541 uint rqfpr; /* 0x2433c - Receive queue filing table property Register */
542 uint mrblr; /* 0x24340 - Maximum Receive Buffer Length Register */
543 char res28[56];
544 uint rbdbph; /* 0x2437C - Receive Data Buffer Pointer High */
545 char res29[4];
546 uint rbptr0; /* 0x24384 - Receive Buffer Descriptor Pointer for Ring 0 */
547 char res30[4];
548 uint rbptr1; /* 0x2438C - Receive Buffer Descriptor Pointer for Ring 1 */
549 char res31[4];
550 uint rbptr2; /* 0x24394 - Receive Buffer Descriptor Pointer for Ring 2 */
551 char res32[4];
552 uint rbptr3; /* 0x2439C - Receive Buffer Descriptor Pointer for Ring 3 */
553 char res33[4];
554 uint rbptr4; /* 0x243A4 - Receive Buffer Descriptor Pointer for Ring 4 */
555 char res34[4];
556 uint rbptr5; /* 0x243AC - Receive Buffer Descriptor Pointer for Ring 5 */
557 char res35[4];
558 uint rbptr6; /* 0x243B4 - Receive Buffer Descriptor Pointer for Ring 6 */
559 char res36[4];
560 uint rbptr7; /* 0x243BC - Receive Buffer Descriptor Pointer for Ring 7 */
561 char res37[64];
562 uint rbaseh; /* 0x24400 - Receive Descriptor Base Address High 0 */
563 uint rbase0; /* 0x24404 - Receive Descriptor Base Address of Ring 0 */
564 char res38[4];
565 uint rbase1; /* 0x2440C - Receive Descriptor Base Address of Ring 1 */
566 char res39[4];
567 uint rbase2; /* 0x24414 - Receive Descriptor Base Address of Ring 2 */
568 char res40[4];
569 uint rbase3; /* 0x2441C - Receive Descriptor Base Address of Ring 3 */
570 char res41[4];
571 uint rbase4; /* 0x24424 - Receive Descriptor Base Address of Ring 4 */
572 char res42[4];
573 uint rbase5; /* 0x2442C - Receive Descriptor Base Address of Ring 5 */
574 char res43[4];
575 uint rbase6; /* 0x24434 - Receive Descriptor Base Address of Ring 6 */
576 char res44[4];
577 uint rbase7; /* 0x2443C - Receive Descriptor Base Address of Ring 7 */
578 char res45[192];
579 uint maccfg1; /* 0x24500 - MAC Configuration 1 Register */
580 uint maccfg2; /* 0x24504 - MAC Configuration 2 Register */
581 uint ipgifg; /* 0x24508 - Inter Packet Gap/Inter Frame Gap Register */
582 uint hafdup; /* 0x2450c - Half Duplex Register */
583 uint maxfrm; /* 0x24510 - Maximum Frame Length Register */
584 char res46[12];
585 uint miimcfg; /* 0x24520 - MII Management Configuration Register */
586 uint miimcom; /* 0x24524 - MII Management Command Register */
587 uint miimadd; /* 0x24528 - MII Management Address Register */
588 uint miimcon; /* 0x2452c - MII Management Control Register */
589 uint miimstat; /* 0x24530 - MII Management Status Register */
590 uint miimind; /* 0x24534 - MII Management Indicator Register */
591 uint ifctrl; /* 0x24538 - Interface Contrl Register */
592 uint ifstat; /* 0x2453c - Interface Status Register */
593 uint macstnaddr1; /* 0x24540 - Station Address Part 1 Register */
594 uint macstnaddr2; /* 0x24544 - Station Address Part 2 Register */
595 uint mac01addr1; /* 0x24548 - MAC exact match address 1, part 1 */
596 uint mac01addr2; /* 0x2454C - MAC exact match address 1, part 2 */
597 uint mac02addr1; /* 0x24550 - MAC exact match address 2, part 1 */
598 uint mac02addr2; /* 0x24554 - MAC exact match address 2, part 2 */
599 uint mac03addr1; /* 0x24558 - MAC exact match address 3, part 1 */
600 uint mac03addr2; /* 0x2455C - MAC exact match address 3, part 2 */
601 uint mac04addr1; /* 0x24560 - MAC exact match address 4, part 1 */
602 uint mac04addr2; /* 0x24564 - MAC exact match address 4, part 2 */
603 uint mac05addr1; /* 0x24568 - MAC exact match address 5, part 1 */
604 uint mac05addr2; /* 0x2456C - MAC exact match address 5, part 2 */
605 uint mac06addr1; /* 0x24570 - MAC exact match address 6, part 1 */
606 uint mac06addr2; /* 0x24574 - MAC exact match address 6, part 2 */
607 uint mac07addr1; /* 0x24578 - MAC exact match address 7, part 1 */
608 uint mac07addr2; /* 0x2457C - MAC exact match address 7, part 2 */
609 uint mac08addr1; /* 0x24580 - MAC exact match address 8, part 1 */
610 uint mac08addr2; /* 0x24584 - MAC exact match address 8, part 2 */
611 uint mac09addr1; /* 0x24588 - MAC exact match address 9, part 1 */
612 uint mac09addr2; /* 0x2458C - MAC exact match address 9, part 2 */
613 uint mac10addr1; /* 0x24590 - MAC exact match address 10, part 1 */
614 uint mac10addr2; /* 0x24594 - MAC exact match address 10, part 2 */
615 uint mac11addr1; /* 0x24598 - MAC exact match address 11, part 1 */
616 uint mac11addr2; /* 0x2459C - MAC exact match address 11, part 2 */
617 uint mac12addr1; /* 0x245A0 - MAC exact match address 12, part 1 */
618 uint mac12addr2; /* 0x245A4 - MAC exact match address 12, part 2 */
619 uint mac13addr1; /* 0x245A8 - MAC exact match address 13, part 1 */
620 uint mac13addr2; /* 0x245AC - MAC exact match address 13, part 2 */
621 uint mac14addr1; /* 0x245B0 - MAC exact match address 14, part 1 */
622 uint mac14addr2; /* 0x245B4 - MAC exact match address 14, part 2 */
623 uint mac15addr1; /* 0x245B8 - MAC exact match address 15, part 1 */
624 uint mac15addr2; /* 0x245BC - MAC exact match address 15, part 2 */
625 char res48[192];
626 uint tr64; /* 0x24680 - Transmit and Receive 64-byte Frame Counter */
627 uint tr127; /* 0x24684 - Transmit and Receive 65-127 byte Frame Counter */
628 uint tr255; /* 0x24688 - Transmit and Receive 128-255 byte Frame Counter */
629 uint tr511; /* 0x2468c - Transmit and Receive 256-511 byte Frame Counter */
630 uint tr1k; /* 0x24690 - Transmit and Receive 512-1023 byte Frame Counter */
631 uint trmax; /* 0x24694 - Transmit and Receive 1024-1518 byte Frame Counter */
632 uint trmgv; /* 0x24698 - Transmit and Receive 1519-1522 byte Good VLAN Frame */
633 uint rbyt; /* 0x2469c - Receive Byte Counter */
634 uint rpkt; /* 0x246a0 - Receive Packet Counter */
635 uint rfcs; /* 0x246a4 - Receive FCS Error Counter */
636 uint rmca; /* 0x246a8 - Receive Multicast Packet Counter */
637 uint rbca; /* 0x246ac - Receive Broadcast Packet Counter */
638 uint rxcf; /* 0x246b0 - Receive Control Frame Packet Counter */
639 uint rxpf; /* 0x246b4 - Receive Pause Frame Packet Counter */
640 uint rxuo; /* 0x246b8 - Receive Unknown OP Code Counter */
641 uint raln; /* 0x246bc - Receive Alignment Error Counter */
642 uint rflr; /* 0x246c0 - Receive Frame Length Error Counter */
643 uint rcde; /* 0x246c4 - Receive Code Error Counter */
644 uint rcse; /* 0x246c8 - Receive Carrier Sense Error Counter */
645 uint rund; /* 0x246cc - Receive Undersize Packet Counter */
646 uint rovr; /* 0x246d0 - Receive Oversize Packet Counter */
647 uint rfrg; /* 0x246d4 - Receive Fragments Counter */
648 uint rjbr; /* 0x246d8 - Receive Jabber Counter */
649 uint rdrp; /* 0x246dc - Receive Drop Counter */
650 uint tbyt; /* 0x246e0 - Transmit Byte Counter Counter */
651 uint tpkt; /* 0x246e4 - Transmit Packet Counter */
652 uint tmca; /* 0x246e8 - Transmit Multicast Packet Counter */
653 uint tbca; /* 0x246ec - Transmit Broadcast Packet Counter */
654 uint txpf; /* 0x246f0 - Transmit Pause Control Frame Counter */
655 uint tdfr; /* 0x246f4 - Transmit Deferral Packet Counter */
656 uint tedf; /* 0x246f8 - Transmit Excessive Deferral Packet Counter */
657 uint tscl; /* 0x246fc - Transmit Single Collision Packet Counter */
658 uint tmcl; /* 0x24700 - Transmit Multiple Collision Packet Counter */
659 uint tlcl; /* 0x24704 - Transmit Late Collision Packet Counter */
660 uint txcl; /* 0x24708 - Transmit Excessive Collision Packet Counter */
661 uint tncl; /* 0x2470c - Transmit Total Collision Counter */
662 char res49[4];
663 uint tdrp; /* 0x24714 - Transmit Drop Frame Counter */
664 uint tjbr; /* 0x24718 - Transmit Jabber Frame Counter */
665 uint tfcs; /* 0x2471c - Transmit FCS Error Counter */
666 uint txcf; /* 0x24720 - Transmit Control Frame Counter */
667 uint tovr; /* 0x24724 - Transmit Oversize Frame Counter */
668 uint tund; /* 0x24728 - Transmit Undersize Frame Counter */
669 uint tfrg; /* 0x2472c - Transmit Fragments Frame Counter */
670 uint car1; /* 0x24730 - Carry Register One */
671 uint car2; /* 0x24734 - Carry Register Two */
672 uint cam1; /* 0x24738 - Carry Mask Register One */
673 uint cam2; /* 0x2473c - Carry Mask Register Two */
674 uint rrej; /* 0x24740 - Receive filer rejected packet counter */
675 char res50[188];
676 uint iaddr0; /* 0x24800 - Indivdual address register 0 */
677 uint iaddr1; /* 0x24804 - Indivdual address register 1 */
678 uint iaddr2; /* 0x24808 - Indivdual address register 2 */
679 uint iaddr3; /* 0x2480c - Indivdual address register 3 */
680 uint iaddr4; /* 0x24810 - Indivdual address register 4 */
681 uint iaddr5; /* 0x24814 - Indivdual address register 5 */
682 uint iaddr6; /* 0x24818 - Indivdual address register 6 */
683 uint iaddr7; /* 0x2481c - Indivdual address register 7 */
684 char res51[96];
685 uint gaddr0; /* 0x24880 - Global address register 0 */
686 uint gaddr1; /* 0x24884 - Global address register 1 */
687 uint gaddr2; /* 0x24888 - Global address register 2 */
688 uint gaddr3; /* 0x2488c - Global address register 3 */
689 uint gaddr4; /* 0x24890 - Global address register 4 */
690 uint gaddr5; /* 0x24894 - Global address register 5 */
691 uint gaddr6; /* 0x24898 - Global address register 6 */
692 uint gaddr7; /* 0x2489c - Global address register 7 */
693 char res52[352];
694 uint fifocfg; /* 0x24A00 - FIFO interface configuration register */
695 char res53[500];
696 uint attr; /* 0x24BF8 - DMA Attribute register */
697 uint attreli; /* 0x24BFC - DMA Attribute extract length and index register */
698 char res54[1024];
699 } ccsr_tsec_t;
700
701 /* PIC Registers(0x4_0000-0x6_1000) */
702
703 typedef struct ccsr_pic {
704 char res1[64];
705 uint ipidr0; /* 0x40040 - Interprocessor Interrupt Dispatch Register 0 */
706 char res2[12];
707 uint ipidr1; /* 0x40050 - Interprocessor Interrupt Dispatch Register 1 */
708 char res3[12];
709 uint ipidr2; /* 0x40060 - Interprocessor Interrupt Dispatch Register 2 */
710 char res4[12];
711 uint ipidr3; /* 0x40070 - Interprocessor Interrupt Dispatch Register 3 */
712 char res5[12];
713 uint ctpr; /* 0x40080 - Current Task Priority Register */
714 char res6[12];
715 uint whoami; /* 0x40090 - Who Am I Register */
716 char res7[12];
717 uint iack; /* 0x400a0 - Interrupt Acknowledge Register */
718 char res8[12];
719 uint eoi; /* 0x400b0 - End Of Interrupt Register */
720 char res9[3916];
721 uint frr; /* 0x41000 - Feature Reporting Register */
722 char res10[28];
723 uint gcr; /* 0x41020 - Global Configuration Register */
724 char res11[92];
725 uint vir; /* 0x41080 - Vendor Identification Register */
726 char res12[12];
727 uint pir; /* 0x41090 - Processor Initialization Register */
728 char res13[12];
729 uint ipivpr0; /* 0x410a0 - IPI Vector/Priority Register 0 */
730 char res14[12];
731 uint ipivpr1; /* 0x410b0 - IPI Vector/Priority Register 1 */
732 char res15[12];
733 uint ipivpr2; /* 0x410c0 - IPI Vector/Priority Register 2 */
734 char res16[12];
735 uint ipivpr3; /* 0x410d0 - IPI Vector/Priority Register 3 */
736 char res17[12];
737 uint svr; /* 0x410e0 - Spurious Vector Register */
738 char res18[12];
739 uint tfrr; /* 0x410f0 - Timer Frequency Reporting Register */
740 char res19[12];
741 uint gtccr0; /* 0x41100 - Global Timer Current Count Register 0 */
742 char res20[12];
743 uint gtbcr0; /* 0x41110 - Global Timer Base Count Register 0 */
744 char res21[12];
745 uint gtvpr0; /* 0x41120 - Global Timer Vector/Priority Register 0 */
746 char res22[12];
747 uint gtdr0; /* 0x41130 - Global Timer Destination Register 0 */
748 char res23[12];
749 uint gtccr1; /* 0x41140 - Global Timer Current Count Register 1 */
750 char res24[12];
751 uint gtbcr1; /* 0x41150 - Global Timer Base Count Register 1 */
752 char res25[12];
753 uint gtvpr1; /* 0x41160 - Global Timer Vector/Priority Register 1 */
754 char res26[12];
755 uint gtdr1; /* 0x41170 - Global Timer Destination Register 1 */
756 char res27[12];
757 uint gtccr2; /* 0x41180 - Global Timer Current Count Register 2 */
758 char res28[12];
759 uint gtbcr2; /* 0x41190 - Global Timer Base Count Register 2 */
760 char res29[12];
761 uint gtvpr2; /* 0x411a0 - Global Timer Vector/Priority Register 2 */
762 char res30[12];
763 uint gtdr2; /* 0x411b0 - Global Timer Destination Register 2 */
764 char res31[12];
765 uint gtccr3; /* 0x411c0 - Global Timer Current Count Register 3 */
766 char res32[12];
767 uint gtbcr3; /* 0x411d0 - Global Timer Base Count Register 3 */
768 char res33[12];
769 uint gtvpr3; /* 0x411e0 - Global Timer Vector/Priority Register 3 */
770 char res34[12];
771 uint gtdr3; /* 0x411f0 - Global Timer Destination Register 3 */
772 char res35[268];
773 uint tcr; /* 0x41300 - Timer Control Register */
774 char res36[12];
775 uint irqsr0; /* 0x41310 - IRQ_OUT Summary Register 0 */
776 char res37[12];
777 uint irqsr1; /* 0x41320 - IRQ_OUT Summary Register 1 */
778 char res38[12];
779 uint cisr0; /* 0x41330 - Critical Interrupt Summary Register 0 */
780 char res39[12];
781 uint cisr1; /* 0x41340 - Critical Interrupt Summary Register 1 */
782 char res40[12];
783 uint pm0mr0; /* 0x41350 - Performance monitor 0 mask register 0 */
784 char res41[12];
785 uint pm0mr1; /* 0x41360 - Performance monitor 0 mask register 1 */
786 char res42[12];
787 uint pm1mr0; /* 0x41370 - Performance monitor 1 mask register 0 */
788 char res43[12];
789 uint pm1mr1; /* 0x41380 - Performance monitor 1 mask register 1 */
790 char res44[12];
791 uint pm2mr0; /* 0x41390 - Performance monitor 2 mask register 0 */
792 char res45[12];
793 uint pm2mr1; /* 0x413A0 - Performance monitor 2 mask register 1 */
794 char res46[12];
795 uint pm3mr0; /* 0x413B0 - Performance monitor 3 mask register 0 */
796 char res47[12];
797 uint pm3mr1; /* 0x413C0 - Performance monitor 3 mask register 1 */
798 char res48[60];
799 uint msgr0; /* 0x41400 - Message Register 0 */
800 char res49[12];
801 uint msgr1; /* 0x41410 - Message Register 1 */
802 char res50[12];
803 uint msgr2; /* 0x41420 - Message Register 2 */
804 char res51[12];
805 uint msgr3; /* 0x41430 - Message Register 3 */
806 char res52[204];
807 uint mer; /* 0x41500 - Message Enable Register */
808 char res53[12];
809 uint msr; /* 0x41510 - Message Status Register */
810 char res54[60140];
811 uint eivpr0; /* 0x50000 - External Interrupt Vector/Priority Register 0 */
812 char res55[12];
813 uint eidr0; /* 0x50010 - External Interrupt Destination Register 0 */
814 char res56[12];
815 uint eivpr1; /* 0x50020 - External Interrupt Vector/Priority Register 1 */
816 char res57[12];
817 uint eidr1; /* 0x50030 - External Interrupt Destination Register 1 */
818 char res58[12];
819 uint eivpr2; /* 0x50040 - External Interrupt Vector/Priority Register 2 */
820 char res59[12];
821 uint eidr2; /* 0x50050 - External Interrupt Destination Register 2 */
822 char res60[12];
823 uint eivpr3; /* 0x50060 - External Interrupt Vector/Priority Register 3 */
824 char res61[12];
825 uint eidr3; /* 0x50070 - External Interrupt Destination Register 3 */
826 char res62[12];
827 uint eivpr4; /* 0x50080 - External Interrupt Vector/Priority Register 4 */
828 char res63[12];
829 uint eidr4; /* 0x50090 - External Interrupt Destination Register 4 */
830 char res64[12];
831 uint eivpr5; /* 0x500a0 - External Interrupt Vector/Priority Register 5 */
832 char res65[12];
833 uint eidr5; /* 0x500b0 - External Interrupt Destination Register 5 */
834 char res66[12];
835 uint eivpr6; /* 0x500c0 - External Interrupt Vector/Priority Register 6 */
836 char res67[12];
837 uint eidr6; /* 0x500d0 - External Interrupt Destination Register 6 */
838 char res68[12];
839 uint eivpr7; /* 0x500e0 - External Interrupt Vector/Priority Register 7 */
840 char res69[12];
841 uint eidr7; /* 0x500f0 - External Interrupt Destination Register 7 */
842 char res70[12];
843 uint eivpr8; /* 0x50100 - External Interrupt Vector/Priority Register 8 */
844 char res71[12];
845 uint eidr8; /* 0x50110 - External Interrupt Destination Register 8 */
846 char res72[12];
847 uint eivpr9; /* 0x50120 - External Interrupt Vector/Priority Register 9 */
848 char res73[12];
849 uint eidr9; /* 0x50130 - External Interrupt Destination Register 9 */
850 char res74[12];
851 uint eivpr10; /* 0x50140 - External Interrupt Vector/Priority Register 10 */
852 char res75[12];
853 uint eidr10; /* 0x50150 - External Interrupt Destination Register 10 */
854 char res76[12];
855 uint eivpr11; /* 0x50160 - External Interrupt Vector/Priority Register 11 */
856 char res77[12];
857 uint eidr11; /* 0x50170 - External Interrupt Destination Register 11 */
858 char res78[140];
859 uint iivpr0; /* 0x50200 - Internal Interrupt Vector/Priority Register 0 */
860 char res79[12];
861 uint iidr0; /* 0x50210 - Internal Interrupt Destination Register 0 */
862 char res80[12];
863 uint iivpr1; /* 0x50220 - Internal Interrupt Vector/Priority Register 1 */
864 char res81[12];
865 uint iidr1; /* 0x50230 - Internal Interrupt Destination Register 1 */
866 char res82[12];
867 uint iivpr2; /* 0x50240 - Internal Interrupt Vector/Priority Register 2 */
868 char res83[12];
869 uint iidr2; /* 0x50250 - Internal Interrupt Destination Register 2 */
870 char res84[12];
871 uint iivpr3; /* 0x50260 - Internal Interrupt Vector/Priority Register 3 */
872 char res85[12];
873 uint iidr3; /* 0x50270 - Internal Interrupt Destination Register 3 */
874 char res86[12];
875 uint iivpr4; /* 0x50280 - Internal Interrupt Vector/Priority Register 4 */
876 char res87[12];
877 uint iidr4; /* 0x50290 - Internal Interrupt Destination Register 4 */
878 char res88[12];
879 uint iivpr5; /* 0x502a0 - Internal Interrupt Vector/Priority Register 5 */
880 char res89[12];
881 uint iidr5; /* 0x502b0 - Internal Interrupt Destination Register 5 */
882 char res90[12];
883 uint iivpr6; /* 0x502c0 - Internal Interrupt Vector/Priority Register 6 */
884 char res91[12];
885 uint iidr6; /* 0x502d0 - Internal Interrupt Destination Register 6 */
886 char res92[12];
887 uint iivpr7; /* 0x502e0 - Internal Interrupt Vector/Priority Register 7 */
888 char res93[12];
889 uint iidr7; /* 0x502f0 - Internal Interrupt Destination Register 7 */
890 char res94[12];
891 uint iivpr8; /* 0x50300 - Internal Interrupt Vector/Priority Register 8 */
892 char res95[12];
893 uint iidr8; /* 0x50310 - Internal Interrupt Destination Register 8 */
894 char res96[12];
895 uint iivpr9; /* 0x50320 - Internal Interrupt Vector/Priority Register 9 */
896 char res97[12];
897 uint iidr9; /* 0x50330 - Internal Interrupt Destination Register 9 */
898 char res98[12];
899 uint iivpr10; /* 0x50340 - Internal Interrupt Vector/Priority Register 10 */
900 char res99[12];
901 uint iidr10; /* 0x50350 - Internal Interrupt Destination Register 10 */
902 char res100[12];
903 uint iivpr11; /* 0x50360 - Internal Interrupt Vector/Priority Register 11 */
904 char res101[12];
905 uint iidr11; /* 0x50370 - Internal Interrupt Destination Register 11 */
906 char res102[12];
907 uint iivpr12; /* 0x50380 - Internal Interrupt Vector/Priority Register 12 */
908 char res103[12];
909 uint iidr12; /* 0x50390 - Internal Interrupt Destination Register 12 */
910 char res104[12];
911 uint iivpr13; /* 0x503a0 - Internal Interrupt Vector/Priority Register 13 */
912 char res105[12];
913 uint iidr13; /* 0x503b0 - Internal Interrupt Destination Register 13 */
914 char res106[12];
915 uint iivpr14; /* 0x503c0 - Internal Interrupt Vector/Priority Register 14 */
916 char res107[12];
917 uint iidr14; /* 0x503d0 - Internal Interrupt Destination Register 14 */
918 char res108[12];
919 uint iivpr15; /* 0x503e0 - Internal Interrupt Vector/Priority Register 15 */
920 char res109[12];
921 uint iidr15; /* 0x503f0 - Internal Interrupt Destination Register 15 */
922 char res110[12];
923 uint iivpr16; /* 0x50400 - Internal Interrupt Vector/Priority Register 16 */
924 char res111[12];
925 uint iidr16; /* 0x50410 - Internal Interrupt Destination Register 16 */
926 char res112[12];
927 uint iivpr17; /* 0x50420 - Internal Interrupt Vector/Priority Register 17 */
928 char res113[12];
929 uint iidr17; /* 0x50430 - Internal Interrupt Destination Register 17 */
930 char res114[12];
931 uint iivpr18; /* 0x50440 - Internal Interrupt Vector/Priority Register 18 */
932 char res115[12];
933 uint iidr18; /* 0x50450 - Internal Interrupt Destination Register 18 */
934 char res116[12];
935 uint iivpr19; /* 0x50460 - Internal Interrupt Vector/Priority Register 19 */
936 char res117[12];
937 uint iidr19; /* 0x50470 - Internal Interrupt Destination Register 19 */
938 char res118[12];
939 uint iivpr20; /* 0x50480 - Internal Interrupt Vector/Priority Register 20 */
940 char res119[12];
941 uint iidr20; /* 0x50490 - Internal Interrupt Destination Register 20 */
942 char res120[12];
943 uint iivpr21; /* 0x504a0 - Internal Interrupt Vector/Priority Register 21 */
944 char res121[12];
945 uint iidr21; /* 0x504b0 - Internal Interrupt Destination Register 21 */
946 char res122[12];
947 uint iivpr22; /* 0x504c0 - Internal Interrupt Vector/Priority Register 22 */
948 char res123[12];
949 uint iidr22; /* 0x504d0 - Internal Interrupt Destination Register 22 */
950 char res124[12];
951 uint iivpr23; /* 0x504e0 - Internal Interrupt Vector/Priority Register 23 */
952 char res125[12];
953 uint iidr23; /* 0x504f0 - Internal Interrupt Destination Register 23 */
954 char res126[12];
955 uint iivpr24; /* 0x50500 - Internal Interrupt Vector/Priority Register 24 */
956 char res127[12];
957 uint iidr24; /* 0x50510 - Internal Interrupt Destination Register 24 */
958 char res128[12];
959 uint iivpr25; /* 0x50520 - Internal Interrupt Vector/Priority Register 25 */
960 char res129[12];
961 uint iidr25; /* 0x50530 - Internal Interrupt Destination Register 25 */
962 char res130[12];
963 uint iivpr26; /* 0x50540 - Internal Interrupt Vector/Priority Register 26 */
964 char res131[12];
965 uint iidr26; /* 0x50550 - Internal Interrupt Destination Register 26 */
966 char res132[12];
967 uint iivpr27; /* 0x50560 - Internal Interrupt Vector/Priority Register 27 */
968 char res133[12];
969 uint iidr27; /* 0x50570 - Internal Interrupt Destination Register 27 */
970 char res134[12];
971 uint iivpr28; /* 0x50580 - Internal Interrupt Vector/Priority Register 28 */
972 char res135[12];
973 uint iidr28; /* 0x50590 - Internal Interrupt Destination Register 28 */
974 char res136[12];
975 uint iivpr29; /* 0x505a0 - Internal Interrupt Vector/Priority Register 29 */
976 char res137[12];
977 uint iidr29; /* 0x505b0 - Internal Interrupt Destination Register 29 */
978 char res138[12];
979 uint iivpr30; /* 0x505c0 - Internal Interrupt Vector/Priority Register 30 */
980 char res139[12];
981 uint iidr30; /* 0x505d0 - Internal Interrupt Destination Register 30 */
982 char res140[12];
983 uint iivpr31; /* 0x505e0 - Internal Interrupt Vector/Priority Register 31 */
984 char res141[12];
985 uint iidr31; /* 0x505f0 - Internal Interrupt Destination Register 31 */
986 char res142[4108];
987 uint mivpr0; /* 0x51600 - Messaging Interrupt Vector/Priority Register 0 */
988 char res143[12];
989 uint midr0; /* 0x51610 - Messaging Interrupt Destination Register 0 */
990 char res144[12];
991 uint mivpr1; /* 0x51620 - Messaging Interrupt Vector/Priority Register 1 */
992 char res145[12];
993 uint midr1; /* 0x51630 - Messaging Interrupt Destination Register 1 */
994 char res146[12];
995 uint mivpr2; /* 0x51640 - Messaging Interrupt Vector/Priority Register 2 */
996 char res147[12];
997 uint midr2; /* 0x51650 - Messaging Interrupt Destination Register 2 */
998 char res148[12];
999 uint mivpr3; /* 0x51660 - Messaging Interrupt Vector/Priority Register 3 */
1000 char res149[12];
1001 uint midr3; /* 0x51670 - Messaging Interrupt Destination Register 3 */
1002 char res150[59852];
1003 uint ipi0dr0; /* 0x60040 - Processor 0 Interprocessor Interrupt Dispatch Register 0 */
1004 char res151[12];
1005 uint ipi0dr1; /* 0x60050 - Processor 0 Interprocessor Interrupt Dispatch Register 1 */
1006 char res152[12];
1007 uint ipi0dr2; /* 0x60060 - Processor 0 Interprocessor Interrupt Dispatch Register 2 */
1008 char res153[12];
1009 uint ipi0dr3; /* 0x60070 - Processor 0 Interprocessor Interrupt Dispatch Register 3 */
1010 char res154[12];
1011 uint ctpr0; /* 0x60080 - Current Task Priority Register for Processor 0 */
1012 char res155[12];
1013 uint whoami0; /* 0x60090 - Who Am I Register for Processor 0 */
1014 char res156[12];
1015 uint iack0; /* 0x600a0 - Interrupt Acknowledge Register for Processor 0 */
1016 char res157[12];
1017 uint eoi0; /* 0x600b0 - End Of Interrupt Register for Processor 0 */
1018 char res158[3916];
1019 } ccsr_pic_t;
1020
1021 /* RapidIO Registers(0xc_0000-0xe_0000) */
1022
1023 typedef struct ccsr_rio {
1024 uint didcar; /* 0xc0000 - Device Identity Capability Register */
1025 uint dicar; /* 0xc0004 - Device Information Capability Register */
1026 uint aidcar; /* 0xc0008 - Assembly Identity Capability Register */
1027 uint aicar; /* 0xc000c - Assembly Information Capability Register */
1028 uint pefcar; /* 0xc0010 - Processing Element Features Capability Register */
1029 uint spicar; /* 0xc0014 - Switch Port Information Capability Register */
1030 uint socar; /* 0xc0018 - Source Operations Capability Register */
1031 uint docar; /* 0xc001c - Destination Operations Capability Register */
1032 char res1[32];
1033 uint msr; /* 0xc0040 - Mailbox Command And Status Register */
1034 uint pwdcsr; /* 0xc0044 - Port-Write and Doorbell Command And Status Register */
1035 char res2[4];
1036 uint pellccsr; /* 0xc004c - Processing Element Logic Layer Control Command and Status Register */
1037 char res3[12];
1038 uint lcsbacsr; /* 0xc005c - Local Configuration Space Base Address Command and Status Register */
1039 uint bdidcsr; /* 0xc0060 - Base Device ID Command and Status Register */
1040 char res4[4];
1041 uint hbdidlcsr; /* 0xc0068 - Host Base Device ID Lock Command and Status Register */
1042 uint ctcsr; /* 0xc006c - Component Tag Command and Status Register */
1043 char res5[144];
1044 uint pmbh0csr; /* 0xc0100 - 8/16 LP-LVDS Port Maintenance Block Header 0 Command and Status Register */
1045 char res6[28];
1046 uint pltoccsr; /* 0xc0120 - Port Link Time-out Control Command and Status Register */
1047 uint prtoccsr; /* 0xc0124 - Port Response Time-out Control Command and Status Register */
1048 char res7[20];
1049 uint pgccsr; /* 0xc013c - Port General Command and Status Register */
1050 uint plmreqcsr; /* 0xc0140 - Port Link Maintenance Request Command and Status Register */
1051 uint plmrespcsr; /* 0xc0144 - Port Link Maintenance Response Command and Status Register */
1052 uint plascsr; /* 0xc0148 - Port Local Ackid Status Command and Status Register */
1053 char res8[12];
1054 uint pescsr; /* 0xc0158 - Port Error and Status Command and Status Register */
1055 uint pccsr; /* 0xc015c - Port Control Command and Status Register */
1056 char res9[1184];
1057 uint erbh; /* 0xc0600 - Error Reporting Block Header Register */
1058 char res10[4];
1059 uint ltledcsr; /* 0xc0608 - Logical/Transport layer error detect status register */
1060 uint ltleecsr; /* 0xc060c - Logical/Transport layer error enable register */
1061 char res11[4];
1062 uint ltlaccsr; /* 0xc0614 - Logical/Transport layer addresss capture register */
1063 uint ltldidccsr; /* 0xc0618 - Logical/Transport layer device ID capture register */
1064 uint ltlcccsr; /* 0xc061c - Logical/Transport layer control capture register */
1065 char res12[32];
1066 uint edcsr; /* 0xc0640 - Port 0 error detect status register */
1067 uint erecsr; /* 0xc0644 - Port 0 error rate enable status register */
1068 uint ecacsr; /* 0xc0648 - Port 0 error capture attributes register */
1069 uint pcseccsr0; /* 0xc064c - Port 0 packet/control symbol error capture register 0 */
1070 uint peccsr1; /* 0xc0650 - Port 0 error capture command and status register 1 */
1071 uint peccsr2; /* 0xc0654 - Port 0 error capture command and status register 2 */
1072 uint peccsr3; /* 0xc0658 - Port 0 error capture command and status register 3 */
1073 char res13[12];
1074 uint ercsr; /* 0xc0668 - Port 0 error rate command and status register */
1075 uint ertcsr; /* 0xc066C - Port 0 error rate threshold status register*/
1076 char res14[63892];
1077 uint llcr; /* 0xd0004 - Logical Layer Configuration Register */
1078 char res15[12];
1079 uint epwisr; /* 0xd0010 - Error / Port-Write Interrupt Status Register */
1080 char res16[12];
1081 uint lretcr; /* 0xd0020 - Logical Retry Error Threshold Configuration Register */
1082 char res17[92];
1083 uint pretcr; /* 0xd0080 - Physical Retry Erorr Threshold Configuration Register */
1084 char res18[124];
1085 uint adidcsr; /* 0xd0100 - Port 0 Alt. Device ID Command and Status Register */
1086 char res19[28];
1087 uint ptaacr; /* 0xd0120 - Port 0 Pass-Through/Accept-All Configuration Register */
1088 char res20[12];
1089 uint iecsr; /* 0xd0130 - Port 0 Implementation Error Status Register */
1090 char res21[12];
1091 uint pcr; /* 0xd0140 - Port 0 Phsyical Configuration RegisterRegister */
1092 char res22[20];
1093 uint slcsr; /* 0xd0158 - Port 0 Serial Link Command and Status Register */
1094 char res23[4];
1095 uint sleir; /* 0xd0160 - Port 0 Serial Link Error Injection Register */
1096 char res24[2716];
1097 uint rowtar0; /* 0xd0c00 - RapidIO Outbound Window Translation Address Register 0 */
1098 uint rowtear0; /* 0xd0c04 - RapidIO Outbound Window Translation Ext. Address Register 0 */
1099 char res25[8];
1100 uint rowar0; /* 0xd0c10 - RapidIO Outbound Attributes Register 0 */
1101 char res26[12];
1102 uint rowtar1; /* 0xd0c20 - RapidIO Outbound Window Translation Address Register 1 */
1103 uint rowtear1; /* 0xd0c24 - RapidIO Outbound Window Translation Ext. Address Register 1 */
1104 uint rowbar1; /* 0xd0c28 - RapidIO Outbound Window Base Address Register 1 */
1105 char res27[4];
1106 uint rowar1; /* 0xd0c30 - RapidIO Outbound Attributes Register 1 */
1107 uint rows1r1; /* 0xd0c34 - RapidIO Outbound Window Segment 1 Register 1 */
1108 uint rows2r1; /* 0xd0c38 - RapidIO Outbound Window Segment 2 Register 1 */
1109 uint rows3r1; /* 0xd0c3c - RapidIO Outbound Window Segment 3 Register 1 */
1110 uint rowtar2; /* 0xd0c40 - RapidIO Outbound Window Translation Address Register 2 */
1111 uint rowtear2; /* 0xd0c44 - RapidIO Outbound Window Translation Ext. Address Register 2 */
1112 uint rowbar2; /* 0xd0c48 - RapidIO Outbound Window Base Address Register 2 */
1113 char res28[4];
1114 uint rowar2; /* 0xd0c50 - RapidIO Outbound Attributes Register 2 */
1115 uint rows1r2; /* 0xd0c54 - RapidIO Outbound Window Segment 1 Register 2 */
1116 uint rows2r2; /* 0xd0c58 - RapidIO Outbound Window Segment 2 Register 2 */
1117 uint rows3r2; /* 0xd0c5c - RapidIO Outbound Window Segment 3 Register 2 */
1118 uint rowtar3; /* 0xd0c60 - RapidIO Outbound Window Translation Address Register 3 */
1119 uint rowtear3; /* 0xd0c64 - RapidIO Outbound Window Translation Ext. Address Register 3 */
1120 uint rowbar3; /* 0xd0c68 - RapidIO Outbound Window Base Address Register 3 */
1121 char res29[4];
1122 uint rowar3; /* 0xd0c70 - RapidIO Outbound Attributes Register 3 */
1123 uint rows1r3; /* 0xd0c74 - RapidIO Outbound Window Segment 1 Register 3 */
1124 uint rows2r3; /* 0xd0c78 - RapidIO Outbound Window Segment 2 Register 3 */
1125 uint rows3r3; /* 0xd0c7c - RapidIO Outbound Window Segment 3 Register 3 */
1126 uint rowtar4; /* 0xd0c80 - RapidIO Outbound Window Translation Address Register 4 */
1127 uint rowtear4; /* 0xd0c84 - RapidIO Outbound Window Translation Ext. Address Register 4 */
1128 uint rowbar4; /* 0xd0c88 - RapidIO Outbound Window Base Address Register 4 */
1129 char res30[4];
1130 uint rowar4; /* 0xd0c90 - RapidIO Outbound Attributes Register 4 */
1131 uint rows1r4; /* 0xd0c94 - RapidIO Outbound Window Segment 1 Register 4 */
1132 uint rows2r4; /* 0xd0c98 - RapidIO Outbound Window Segment 2 Register 4 */
1133 uint rows3r4; /* 0xd0c9c - RapidIO Outbound Window Segment 3 Register 4 */
1134 uint rowtar5; /* 0xd0ca0 - RapidIO Outbound Window Translation Address Register 5 */
1135 uint rowtear5; /* 0xd0ca4 - RapidIO Outbound Window Translation Ext. Address Register 5 */
1136 uint rowbar5; /* 0xd0ca8 - RapidIO Outbound Window Base Address Register 5 */
1137 char res31[4];
1138 uint rowar5; /* 0xd0cb0 - RapidIO Outbound Attributes Register 5 */
1139 uint rows1r5; /* 0xd0cb4 - RapidIO Outbound Window Segment 1 Register 5 */
1140 uint rows2r5; /* 0xd0cb8 - RapidIO Outbound Window Segment 2 Register 5 */
1141 uint rows3r5; /* 0xd0cbc - RapidIO Outbound Window Segment 3 Register 5 */
1142 uint rowtar6; /* 0xd0cc0 - RapidIO Outbound Window Translation Address Register 6 */
1143 uint rowtear6; /* 0xd0cc4 - RapidIO Outbound Window Translation Ext. Address Register 6 */
1144 uint rowbar6; /* 0xd0cc8 - RapidIO Outbound Window Base Address Register 6 */
1145 char res32[4];
1146 uint rowar6; /* 0xd0cd0 - RapidIO Outbound Attributes Register 6 */
1147 uint rows1r6; /* 0xd0cd4 - RapidIO Outbound Window Segment 1 Register 6 */
1148 uint rows2r6; /* 0xd0cd8 - RapidIO Outbound Window Segment 2 Register 6 */
1149 uint rows3r6; /* 0xd0cdc - RapidIO Outbound Window Segment 3 Register 6 */
1150 uint rowtar7; /* 0xd0ce0 - RapidIO Outbound Window Translation Address Register 7 */
1151 uint rowtear7; /* 0xd0ce4 - RapidIO Outbound Window Translation Ext. Address Register 7 */
1152 uint rowbar7; /* 0xd0ce8 - RapidIO Outbound Window Base Address Register 7 */
1153 char res33[4];
1154 uint rowar7; /* 0xd0cf0 - RapidIO Outbound Attributes Register 7 */
1155 uint rows1r7; /* 0xd0cf4 - RapidIO Outbound Window Segment 1 Register 7 */
1156 uint rows2r7; /* 0xd0cf8 - RapidIO Outbound Window Segment 2 Register 7 */
1157 uint rows3r7; /* 0xd0cfc - RapidIO Outbound Window Segment 3 Register 7 */
1158 uint rowtar8; /* 0xd0d00 - RapidIO Outbound Window Translation Address Register 8 */
1159 uint rowtear8; /* 0xd0d04 - RapidIO Outbound Window Translation Ext. Address Register 8 */
1160 uint rowbar8; /* 0xd0d08 - RapidIO Outbound Window Base Address Register 8 */
1161 char res34[4];
1162 uint rowar8; /* 0xd0d10 - RapidIO Outbound Attributes Register 8 */
1163 uint rows1r8; /* 0xd0d14 - RapidIO Outbound Window Segment 1 Register 8 */
1164 uint rows2r8; /* 0xd0d18 - RapidIO Outbound Window Segment 2 Register 8 */
1165 uint rows3r8; /* 0xd0d1c - RapidIO Outbound Window Segment 3 Register 8 */
1166 char res35[64];
1167 uint riwtar4; /* 0xd0d60 - RapidIO Inbound Window Translation Address Register 4 */
1168 uint riwbar4; /* 0xd0d68 - RapidIO Inbound Window Base Address Register 4 */
1169 char res36[4];
1170 uint riwar4; /* 0xd0d70 - RapidIO Inbound Attributes Register 4 */
1171 char res37[12];
1172 uint riwtar3; /* 0xd0d80 - RapidIO Inbound Window Translation Address Register 3 */
1173 char res38[4];
1174 uint riwbar3; /* 0xd0d88 - RapidIO Inbound Window Base Address Register 3 */
1175 char res39[4];
1176 uint riwar3; /* 0xd0d90 - RapidIO Inbound Attributes Register 3 */
1177 char res40[12];
1178 uint riwtar2; /* 0xd0da0 - RapidIO Inbound Window Translation Address Register 2 */
1179 char res41[4];
1180 uint riwbar2; /* 0xd0da8 - RapidIO Inbound Window Base Address Register 2 */
1181 char res42[4];
1182 uint riwar2; /* 0xd0db0 - RapidIO Inbound Attributes Register 2 */
1183 char res43[12];
1184 uint riwtar1; /* 0xd0dc0 - RapidIO Inbound Window Translation Address Register 1 */
1185 char res44[4];
1186 uint riwbar1; /* 0xd0dc8 - RapidIO Inbound Window Base Address Register 1 */
1187 char res45[4];
1188 uint riwar1; /* 0xd0dd0 - RapidIO Inbound Attributes Register 1 */
1189 char res46[12];
1190 uint riwtar0; /* 0xd0de0 - RapidIO Inbound Window Translation Address Register 0 */
1191 char res47[12];
1192 uint riwar0; /* 0xd0df0 - RapidIO Inbound Attributes Register 0 */
1193 char res48[12];
1194 uint pnfedr; /* 0xd0e00 - Port Notification/Fatal Error Detect Register */
1195 uint pnfedir; /* 0xd0e04 - Port Notification/Fatal Error Detect Register */
1196 uint pnfeier; /* 0xd0e08 - Port Notification/Fatal Error Interrupt Enable Register */
1197 uint pecr; /* 0xd0e0c - Port Error Control Register */
1198 uint pepcsr0; /* 0xd0e10 - Port Error Packet/Control Symbol Register 0 */
1199 uint pepr1; /* 0xd0e14 - Port Error Packet Register 1 */
1200 uint pepr2; /* 0xd0e18 - Port Error Packet Register 2 */
1201 char res49[4];
1202 uint predr; /* 0xd0e20 - Port Recoverable Error Detect Register */
1203 char res50[4];
1204 uint pertr; /* 0xd0e28 - Port Error Recovery Threshold Register */
1205 uint prtr; /* 0xd0e2c - Port Retry Threshold Register */
1206 char res51[8656];
1207 uint omr; /* 0xd3000 - Outbound Mode Register */
1208 uint osr; /* 0xd3004 - Outbound Status Register */
1209 uint eodqtpar; /* 0xd3008 - Extended Outbound Descriptor Queue Tail Pointer Address Register */
1210 uint odqtpar; /* 0xd300c - Outbound Descriptor Queue Tail Pointer Address Register */
1211 uint eosar; /* 0xd3010 - Extended Outbound Unit Source Address Register */
1212 uint osar; /* 0xd3014 - Outbound Unit Source Address Register */
1213 uint odpr; /* 0xd3018 - Outbound Destination Port Register */
1214 uint odatr; /* 0xd301c - Outbound Destination Attributes Register */
1215 uint odcr; /* 0xd3020 - Outbound Doubleword Count Register */
1216 uint eodqhpar; /* 0xd3024 - Extended Outbound Descriptor Queue Head Pointer Address Register */
1217 uint odqhpar; /* 0xd3028 - Outbound Descriptor Queue Head Pointer Address Register */
1218 uint oretr; /* 0xd302C - Outbound Retry Error Threshold Register */
1219 uint omgr; /* 0xd3030 - Outbound Multicast Group Register */
1220 uint omlr; /* 0xd3034 - Outbound Multicast List Register */
1221 char res52[40];
1222 uint imr; /* 0xd3060 - Outbound Mode Register */
1223 uint isr; /* 0xd3064 - Inbound Status Register */
1224 uint eidqtpar; /* 0xd3068 - Extended Inbound Descriptor Queue Tail Pointer Address Register */
1225 uint idqtpar; /* 0xd306c - Inbound Descriptor Queue Tail Pointer Address Register */
1226 uint eifqhpar; /* 0xd3070 - Extended Inbound Frame Queue Head Pointer Address Register */
1227 uint ifqhpar; /* 0xd3074 - Inbound Frame Queue Head Pointer Address Register */
1228 uint imirir; /* 0xd3078 - Inbound Maximum Interrutp Report Interval Register */
1229 char res53[900];
1230 uint oddmr; /* 0xd3400 - Outbound Doorbell Mode Register */
1231 uint oddsr; /* 0xd3404 - Outbound Doorbell Status Register */
1232 char res54[16];
1233 uint oddpr; /* 0xd3418 - Outbound Doorbell Destination Port Register */
1234 uint oddatr; /* 0xd341C - Outbound Doorbell Destination Attributes Register */
1235 char res55[12];
1236 uint oddretr; /* 0xd342C - Outbound Doorbell Retry Threshold Configuration Register */
1237 char res56[48];
1238 uint idmr; /* 0xd3460 - Inbound Doorbell Mode Register */
1239 uint idsr; /* 0xd3464 - Inbound Doorbell Status Register */
1240 uint iedqtpar; /* 0xd3468 - Extended Inbound Doorbell Queue Tail Pointer Address Register */
1241 uint iqtpar; /* 0xd346c - Inbound Doorbell Queue Tail Pointer Address Register */
1242 uint iedqhpar; /* 0xd3470 - Extended Inbound Doorbell Queue Head Pointer Address Register */
1243 uint idqhpar; /* 0xd3474 - Inbound Doorbell Queue Head Pointer Address Register */
1244 uint idmirir; /* 0xd3478 - Inbound Doorbell Max Interrupt Report Interval Register */
1245 char res57[100];
1246 uint pwmr; /* 0xd34e0 - Port-Write Mode Register */
1247 uint pwsr; /* 0xd34e4 - Port-Write Status Register */
1248 uint epwqbar; /* 0xd34e8 - Extended Port-Write Queue Base Address Register */
1249 uint pwqbar; /* 0xd34ec - Port-Write Queue Base Address Register */
1250 char res58[51984];
1251 } ccsr_rio_t;
1252
1253 /* Global Utilities Register Block(0xe_0000-0xf_ffff) */
1254 typedef struct ccsr_gur {
1255 uint porpllsr; /* 0xe0000 - POR PLL ratio status register */
1256 uint porbmsr; /* 0xe0004 - POR boot mode status register */
1257 #define MPC86xx_PORBMSR_HA 0x00060000
1258 uint porimpscr; /* 0xe0008 - POR I/O impedance status and control register */
1259 uint pordevsr; /* 0xe000c - POR I/O device status regsiter */
1260 #define MPC86xx_PORDEVSR_IO_SEL 0x000F0000
1261 uint pordbgmsr; /* 0xe0010 - POR debug mode status register */
1262 char res1[12];
1263 uint gpporcr; /* 0xe0020 - General-purpose POR configuration register */
1264 char res2[12];
1265 uint gpiocr; /* 0xe0030 - GPIO control register */
1266 char res3[12];
1267 uint gpoutdr; /* 0xe0040 - General-purpose output data register */
1268 char res4[12];
1269 uint gpindr; /* 0xe0050 - General-purpose input data register */
1270 char res5[12];
1271 uint pmuxcr; /* 0xe0060 - Alternate function signal multiplex control */
1272 char res6[12];
1273 uint devdisr; /* 0xe0070 - Device disable control */
1274 #define MPC86xx_DEVDISR_PCIEX1 0x80000000
1275 #define MPC86xx_DEVDISR_PCIEX2 0x40000000
1276 char res7[12];
1277 uint powmgtcsr; /* 0xe0080 - Power management status and control register */
1278 char res8[12];
1279 uint mcpsumr; /* 0xe0090 - Machine check summary register */
1280 char res9[12];
1281 uint pvr; /* 0xe00a0 - Processor version register */
1282 uint svr; /* 0xe00a4 - System version register */
1283 char res10[3416];
1284 uint clkocr; /* 0xe0e00 - Clock out select register */
1285 char res11[12];
1286 uint ddrdllcr; /* 0xe0e10 - DDR DLL control register */
1287 char res12[12];
1288 uint lbcdllcr; /* 0xe0e20 - LBC DLL control register */
1289 int res13[57];
1290 uint lynxdcr1; /* 0xe0f08 - Lynx debug control register 1*/
1291 int res14[6];
1292 uint ddrioovcr; /* 0xe0f24 - DDR IO Overdrive Control register */
1293 char res15[61656];
1294 } ccsr_gur_t;
1295
1296 typedef struct immap {
1297 ccsr_local_mcm_t im_local_mcm;
1298 ccsr_ddr_t im_ddr1;
1299 ccsr_i2c_t im_i2c;
1300 ccsr_duart_t im_duart;
1301 ccsr_lbc_t im_lbc;
1302 ccsr_ddr_t im_ddr2;
1303 char res1[4096];
1304 ccsr_pex_t im_pex1;
1305 ccsr_pex_t im_pex2;
1306 ccsr_ht_t im_ht;
1307 char res2[90112];
1308 ccsr_dma_t im_dma;
1309 char res3[8192];
1310 ccsr_tsec_t im_tsec1;
1311 ccsr_tsec_t im_tsec2;
1312 ccsr_tsec_t im_tsec3;
1313 ccsr_tsec_t im_tsec4;
1314 char res4[98304];
1315 ccsr_pic_t im_pic;
1316 char res5[389120];
1317 ccsr_rio_t im_rio;
1318 ccsr_gur_t im_gur;
1319 } immap_t;
1320
1321 extern immap_t *immr;
1322
1323 #endif /*__IMMAP_86xx__*/
uboot for JZ soc