cpu/arm920t/s3c24x0/usb_ohci.h

   1 /*
   2  * URB OHCI HCD (Host Controller Driver) for USB.
   3  *
   4  * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
   5  * (C) Copyright 2000-2001 David Brownell <dbrownell@users.sourceforge.net>
   6  *
   7  * usb-ohci.h
   8  */
   9
  10
  11 static int cc_to_error[16] = {
  12
  13 /* mapping of the OHCI CC status to error codes */
  14         /* No  Error  */               0,
  15         /* CRC Error  */               USB_ST_CRC_ERR,
  16         /* Bit Stuff  */               USB_ST_BIT_ERR,
  17         /* Data Togg  */               USB_ST_CRC_ERR,
  18         /* Stall      */               USB_ST_STALLED,
  19         /* DevNotResp */               -1,
  20         /* PIDCheck   */               USB_ST_BIT_ERR,
  21         /* UnExpPID   */               USB_ST_BIT_ERR,
  22         /* DataOver   */               USB_ST_BUF_ERR,
  23         /* DataUnder  */               USB_ST_BUF_ERR,
  24         /* reservd    */               -1,
  25         /* reservd    */               -1,
  26         /* BufferOver */               USB_ST_BUF_ERR,
  27         /* BuffUnder  */               USB_ST_BUF_ERR,
  28         /* Not Access */               -1,
  29         /* Not Access */               -1
  30 };
  31
  32 /* ED States */
  33 #define ED_NEW          0x00
  34 #define ED_UNLINK       0x01
  35 #define ED_OPER         0x02
  36 #define ED_DEL          0x04
  37 #define ED_URB_DEL      0x08
  38
  39 /* usb_ohci_ed */
  40 struct ed {
  41         __u32 hwINFO;
  42         __u32 hwTailP;
  43         __u32 hwHeadP;
  44         __u32 hwNextED;
  45
  46         struct ed *ed_prev;
  47         __u8 int_period;
  48         __u8 int_branch;
  49         __u8 int_load;
  50         __u8 int_interval;
  51         __u8 state;
  52         __u8 type;
  53         __u16 last_iso;
  54         struct ed *ed_rm_list;
  55
  56         struct usb_device *usb_dev;
  57         __u32 unused[3];
  58 } __attribute((aligned(16)));
  59 typedef struct ed ed_t;
  60
  61
  62 /* TD info field */
  63 #define TD_CC       0xf0000000
  64 #define TD_CC_GET(td_p) ((td_p >>28) & 0x0f)
  65 #define TD_CC_SET(td_p, cc) (td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28)
  66 #define TD_EC       0x0C000000
  67 #define TD_T        0x03000000
  68 #define TD_T_DATA0  0x02000000
  69 #define TD_T_DATA1  0x03000000
  70 #define TD_T_TOGGLE 0x00000000
  71 #define TD_R        0x00040000
  72 #define TD_DI       0x00E00000
  73 #define TD_DI_SET(X) (((X) & 0x07)<< 21)
  74 #define TD_DP       0x00180000
  75 #define TD_DP_SETUP 0x00000000
  76 #define TD_DP_IN    0x00100000
  77 #define TD_DP_OUT   0x00080000
  78
  79 #define TD_ISO      0x00010000
  80 #define TD_DEL      0x00020000
  81
  82 /* CC Codes */
  83 #define TD_CC_NOERROR      0x00
  84 #define TD_CC_CRC          0x01
  85 #define TD_CC_BITSTUFFING  0x02
  86 #define TD_CC_DATATOGGLEM  0x03
  87 #define TD_CC_STALL        0x04
  88 #define TD_DEVNOTRESP      0x05
  89 #define TD_PIDCHECKFAIL    0x06
  90 #define TD_UNEXPECTEDPID   0x07
  91 #define TD_DATAOVERRUN     0x08
  92 #define TD_DATAUNDERRUN    0x09
  93 #define TD_BUFFEROVERRUN   0x0C
  94 #define TD_BUFFERUNDERRUN  0x0D
  95 #define TD_NOTACCESSED     0x0F
  96
  97
  98 #define MAXPSW 1
  99
 100 struct td {
 101         __u32 hwINFO;
 102         __u32 hwCBP;            /* Current Buffer Pointer */
 103         __u32 hwNextTD;         /* Next TD Pointer */
 104         __u32 hwBE;             /* Memory Buffer End Pointer */
 105
 106         __u8 unused;
 107         __u8 index;
 108         struct ed *ed;
 109         struct td *next_dl_td;
 110         struct usb_device *usb_dev;
 111         int transfer_len;
 112         __u32 data;
 113
 114         __u32 unused2[2];
 115 } __attribute((aligned(32)));
 116 typedef struct td td_t;
 117
 118 #define OHCI_ED_SKIP    (1 << 14)
 119
 120 /*
 121  * The HCCA (Host Controller Communications Area) is a 256 byte
 122  * structure defined in the OHCI spec. that the host controller is
 123  * told the base address of.  It must be 256-byte aligned.
 124  */
 125
 126 #define NUM_INTS 32     /* part of the OHCI standard */
 127 struct ohci_hcca {
 128         __u32   int_table[NUM_INTS];    /* Interrupt ED table */
 129         __u16   frame_no;               /* current frame number */
 130         __u16   pad1;                   /* set to 0 on each frame_no change */
 131         __u32   done_head;              /* info returned for an interrupt */
 132         u8              reserved_for_hc[116];
 133 } __attribute((aligned(256)));
 134
 135
 136 /*
 137  * Maximum number of root hub ports.
 138  */
 139 #define MAX_ROOT_PORTS  15      /* maximum OHCI root hub ports */
 140
 141 /*
 142  * This is the structure of the OHCI controller's memory mapped I/O
 143  * region.  This is Memory Mapped I/O.  You must use the readl() and
 144  * writel() macros defined in asm/io.h to access these!!
 145  */
 146 struct ohci_regs {
 147         /* control and status registers */
 148         __u32   revision;
 149         __u32   control;
 150         __u32   cmdstatus;
 151         __u32   intrstatus;
 152         __u32   intrenable;
 153         __u32   intrdisable;
 154         /* memory pointers */
 155         __u32   hcca;
 156         __u32   ed_periodcurrent;
 157         __u32   ed_controlhead;
 158         __u32   ed_controlcurrent;
 159         __u32   ed_bulkhead;
 160         __u32   ed_bulkcurrent;
 161         __u32   donehead;
 162         /* frame counters */
 163         __u32   fminterval;
 164         __u32   fmremaining;
 165         __u32   fmnumber;
 166         __u32   periodicstart;
 167         __u32   lsthresh;
 168         /* Root hub ports */
 169         struct  ohci_roothub_regs {
 170                 __u32   a;
 171                 __u32   b;
 172                 __u32   status;
 173                 __u32   portstatus[MAX_ROOT_PORTS];
 174         } roothub;
 175 } __attribute((aligned(32)));
 176
 177
 178 /* OHCI CONTROL AND STATUS REGISTER MASKS */
 179
 180 /*
 181  * HcControl (control) register masks
 182  */
 183 #define OHCI_CTRL_CBSR  (3 << 0)        /* control/bulk service ratio */
 184 #define OHCI_CTRL_PLE   (1 << 2)        /* periodic list enable */
 185 #define OHCI_CTRL_IE    (1 << 3)        /* isochronous enable */
 186 #define OHCI_CTRL_CLE   (1 << 4)        /* control list enable */
 187 #define OHCI_CTRL_BLE   (1 << 5)        /* bulk list enable */
 188 #define OHCI_CTRL_HCFS  (3 << 6)        /* host controller functional state */
 189 #define OHCI_CTRL_IR    (1 << 8)        /* interrupt routing */
 190 #define OHCI_CTRL_RWC   (1 << 9)        /* remote wakeup connected */
 191 #define OHCI_CTRL_RWE   (1 << 10)       /* remote wakeup enable */
 192
 193 /* pre-shifted values for HCFS */
 194 #       define OHCI_USB_RESET   (0 << 6)
 195 #       define OHCI_USB_RESUME  (1 << 6)
 196 #       define OHCI_USB_OPER    (2 << 6)
 197 #       define OHCI_USB_SUSPEND (3 << 6)
 198
 199 /*
 200  * HcCommandStatus (cmdstatus) register masks
 201  */
 202 #define OHCI_HCR        (1 << 0)        /* host controller reset */
 203 #define OHCI_CLF        (1 << 1)        /* control list filled */
 204 #define OHCI_BLF        (1 << 2)        /* bulk list filled */
 205 #define OHCI_OCR        (1 << 3)        /* ownership change request */
 206 #define OHCI_SOC        (3 << 16)       /* scheduling overrun count */
 207
 208 /*
 209  * masks used with interrupt registers:
 210  * HcInterruptStatus (intrstatus)
 211  * HcInterruptEnable (intrenable)
 212  * HcInterruptDisable (intrdisable)
 213  */
 214 #define OHCI_INTR_SO    (1 << 0)        /* scheduling overrun */
 215 #define OHCI_INTR_WDH   (1 << 1)        /* writeback of done_head */
 216 #define OHCI_INTR_SF    (1 << 2)        /* start frame */
 217 #define OHCI_INTR_RD    (1 << 3)        /* resume detect */
 218 #define OHCI_INTR_UE    (1 << 4)        /* unrecoverable error */
 219 #define OHCI_INTR_FNO   (1 << 5)        /* frame number overflow */
 220 #define OHCI_INTR_RHSC  (1 << 6)        /* root hub status change */
 221 #define OHCI_INTR_OC    (1 << 30)       /* ownership change */
 222 #define OHCI_INTR_MIE   (1 << 31)       /* master interrupt enable */
 223
 224
 225 /* Virtual Root HUB */
 226 struct virt_root_hub {
 227         int devnum; /* Address of Root Hub endpoint */
 228         void *dev;  /* was urb */
 229         void *int_addr;
 230         int send;
 231         int interval;
 232 };
 233
 234 /* USB HUB CONSTANTS (not OHCI-specific; see hub.h) */
 235
 236 /* destination of request */
 237 #define RH_INTERFACE               0x01
 238 #define RH_ENDPOINT                0x02
 239 #define RH_OTHER                   0x03
 240
 241 #define RH_CLASS                   0x20
 242 #define RH_VENDOR                  0x40
 243
 244 /* Requests: bRequest << 8 | bmRequestType */
 245 #define RH_GET_STATUS           0x0080
 246 #define RH_CLEAR_FEATURE        0x0100
 247 #define RH_SET_FEATURE          0x0300
 248 #define RH_SET_ADDRESS          0x0500
 249 #define RH_GET_DESCRIPTOR       0x0680
 250 #define RH_SET_DESCRIPTOR       0x0700
 251 #define RH_GET_CONFIGURATION    0x0880
 252 #define RH_SET_CONFIGURATION    0x0900
 253 #define RH_GET_STATE            0x0280
 254 #define RH_GET_INTERFACE        0x0A80
 255 #define RH_SET_INTERFACE        0x0B00
 256 #define RH_SYNC_FRAME           0x0C80
 257 /* Our Vendor Specific Request */
 258 #define RH_SET_EP               0x2000
 259
 260
 261 /* Hub port features */
 262 #define RH_PORT_CONNECTION         0x00
 263 #define RH_PORT_ENABLE             0x01
 264 #define RH_PORT_SUSPEND            0x02
 265 #define RH_PORT_OVER_CURRENT       0x03
 266 #define RH_PORT_RESET              0x04
 267 #define RH_PORT_POWER              0x08
 268 #define RH_PORT_LOW_SPEED          0x09
 269
 270 #define RH_C_PORT_CONNECTION       0x10
 271 #define RH_C_PORT_ENABLE           0x11
 272 #define RH_C_PORT_SUSPEND          0x12
 273 #define RH_C_PORT_OVER_CURRENT     0x13
 274 #define RH_C_PORT_RESET            0x14
 275
 276 /* Hub features */
 277 #define RH_C_HUB_LOCAL_POWER       0x00
 278 #define RH_C_HUB_OVER_CURRENT      0x01
 279
 280 #define RH_DEVICE_REMOTE_WAKEUP    0x00
 281 #define RH_ENDPOINT_STALL          0x01
 282
 283 #define RH_ACK                     0x01
 284 #define RH_REQ_ERR                 -1
 285 #define RH_NACK                    0x00
 286
 287
 288 /* OHCI ROOT HUB REGISTER MASKS */
 289
 290 /* roothub.portstatus [i] bits */
 291 #define RH_PS_CCS            0x00000001         /* current connect status */
 292 #define RH_PS_PES            0x00000002         /* port enable status*/
 293 #define RH_PS_PSS            0x00000004         /* port suspend status */
 294 #define RH_PS_POCI           0x00000008         /* port over current indicator */
 295 #define RH_PS_PRS            0x00000010         /* port reset status */
 296 #define RH_PS_PPS            0x00000100         /* port power status */
 297 #define RH_PS_LSDA           0x00000200         /* low speed device attached */
 298 #define RH_PS_CSC            0x00010000         /* connect status change */
 299 #define RH_PS_PESC           0x00020000         /* port enable status change */
 300 #define RH_PS_PSSC           0x00040000         /* port suspend status change */
 301 #define RH_PS_OCIC           0x00080000         /* over current indicator change */
 302 #define RH_PS_PRSC           0x00100000         /* port reset status change */
 303
 304 /* roothub.status bits */
 305 #define RH_HS_LPS            0x00000001         /* local power status */
 306 #define RH_HS_OCI            0x00000002         /* over current indicator */
 307 #define RH_HS_DRWE           0x00008000         /* device remote wakeup enable */
 308 #define RH_HS_LPSC           0x00010000         /* local power status change */
 309 #define RH_HS_OCIC           0x00020000         /* over current indicator change */
 310 #define RH_HS_CRWE           0x80000000         /* clear remote wakeup enable */
 311
 312 /* roothub.b masks */
 313 #define RH_B_DR         0x0000ffff              /* device removable flags */
 314 #define RH_B_PPCM       0xffff0000              /* port power control mask */
 315
 316 /* roothub.a masks */
 317 #define RH_A_NDP        (0xff << 0)             /* number of downstream ports */
 318 #define RH_A_PSM        (1 << 8)                /* power switching mode */
 319 #define RH_A_NPS        (1 << 9)                /* no power switching */
 320 #define RH_A_DT         (1 << 10)               /* device type (mbz) */
 321 #define RH_A_OCPM       (1 << 11)               /* over current protection mode */
 322 #define RH_A_NOCP       (1 << 12)               /* no over current protection */
 323 #define RH_A_POTPGT     (0xff << 24)            /* power on to power good time */
 324
 325 /* urb */
 326 #define N_URB_TD 48
 327 typedef struct
 328 {
 329         ed_t *ed;
 330         __u16 length;   /* number of tds associated with this request */
 331         __u16 td_cnt;   /* number of tds already serviced */
 332         int   state;
 333         unsigned long pipe;
 334         int actual_length;
 335         td_t *td[N_URB_TD];     /* list pointer to all corresponding TDs associated with this request */
 336 } urb_priv_t;
 337 #define URB_DEL 1
 338
 339 /*
 340  * This is the full ohci controller description
 341  *
 342  * Note how the "proper" USB information is just
 343  * a subset of what the full implementation needs. (Linus)
 344  */
 345
 346
 347 typedef struct ohci {
 348         struct ohci_hcca *hcca;         /* hcca */
 349         /*dma_addr_t hcca_dma;*/
 350
 351         int irq;
 352         int disabled;                   /* e.g. got a UE, we're hung */
 353         int sleeping;
 354         unsigned long flags;            /* for HC bugs */
 355
 356         struct ohci_regs *regs; /* OHCI controller's memory */
 357
 358         ed_t *ed_rm_list[2];     /* lists of all endpoints to be removed */
 359         ed_t *ed_bulktail;       /* last endpoint of bulk list */
 360         ed_t *ed_controltail;    /* last endpoint of control list */
 361         int intrstatus;
 362         __u32 hc_control;               /* copy of the hc control reg */
 363         struct usb_device *dev[32];
 364         struct virt_root_hub rh;
 365
 366         const char      *slot_name;
 367 } ohci_t;
 368
 369 #define NUM_EDS 8               /* num of preallocated endpoint descriptors */
 370
 371 struct ohci_device {
 372         ed_t    ed[NUM_EDS];
 373         int ed_cnt;
 374 };
 375
 376 /* hcd */
 377 /* endpoint */
 378 static int ep_link(ohci_t * ohci, ed_t * ed);
 379 static int ep_unlink(ohci_t * ohci, ed_t * ed);
 380 static ed_t * ep_add_ed(struct usb_device * usb_dev, unsigned long pipe);
 381
 382 /*-------------------------------------------------------------------------*/
 383
 384 /* we need more TDs than EDs */
 385 #define NUM_TD 64
 386
 387 /* +1 so we can align the storage */
 388 td_t gtd[NUM_TD+1];
 389 /* pointers to aligned storage */
 390 td_t *ptd;
 391
 392 /* TDs ... */
 393 static inline struct td *
 394 td_alloc (struct usb_device *usb_dev)
 395 {
 396         int i;
 397         struct td       *td;
 398
 399         td = NULL;
 400         for (i = 0; i < NUM_TD; i++)
 401         {
 402                 if (ptd[i].usb_dev == NULL)
 403                 {
 404                         td = &ptd[i];
 405                         td->usb_dev = usb_dev;
 406                         break;
 407                 }
 408         }
 409
 410         return td;
 411 }
 412
 413 static inline void
 414 ed_free (struct ed *ed)
 415 {
 416         ed->usb_dev = NULL;
 417 }