cpu/ixp/npe/IxEthAcc.c

   1 /**
   2  * @file IxEthAcc.c
   3  *
   4  * @author Intel Corporation
   5  * @date 20-Feb-2001
   6  *
   7  * @brief This file contains the implementation of the IXP425 Ethernet Access Component
   8  *
   9  * Design Notes:
  10  *
  11  * @par
  12  * IXP400 SW Release version 2.0
  13  *
  14  * -- Copyright Notice --
  15  *
  16  * @par
  17  * Copyright 2001-2005, Intel Corporation.
  18  * All rights reserved.
  19  *
  20  * @par
  21  * Redistribution and use in source and binary forms, with or without
  22  * modification, are permitted provided that the following conditions
  23  * are met:
  24  * 1. Redistributions of source code must retain the above copyright
  25  *    notice, this list of conditions and the following disclaimer.
  26  * 2. Redistributions in binary form must reproduce the above copyright
  27  *    notice, this list of conditions and the following disclaimer in the
  28  *    documentation and/or other materials provided with the distribution.
  29  * 3. Neither the name of the Intel Corporation nor the names of its contributors
  30  *    may be used to endorse or promote products derived from this software
  31  *    without specific prior written permission.
  32  *
  33  * @par
  34  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
  35  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  36  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  37  * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
  38  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  39  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  40  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  41  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  42  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  43  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  44  * SUCH DAMAGE.
  45  *
  46  * @par
  47  * -- End of Copyright Notice --
  48  */
  49
  50
  51
  52 #include "IxEthAcc.h"
  53 #ifdef CONFIG_IXP425_COMPONENT_ETHDB
  54 #include "IxEthDB.h"
  55 #endif
  56 #include "IxFeatureCtrl.h"
  57
  58 #include "IxEthAcc_p.h"
  59 #include "IxEthAccMac_p.h"
  60 #include "IxEthAccMii_p.h"
  61
  62 /**
  63  * @addtogroup IxEthAcc
  64  *@{
  65  */
  66
  67
  68 /**
  69  * @brief System-wide information data strucure.
  70  *
  71  * @ingroup IxEthAccPri
  72  *
  73  */
  74
  75 IxEthAccInfo ixEthAccDataInfo;
  76 extern PUBLIC IxEthAccMacState ixEthAccMacState[];
  77 extern PUBLIC IxOsalMutex ixEthAccControlInterfaceMutex;
  78
  79 /**
  80  * @brief System-wide information
  81  *
  82  * @ingroup IxEthAccPri
  83  *
  84  */
  85 BOOL ixEthAccServiceInit = FALSE;
  86
  87 /* global filtering bit mask */
  88 PUBLIC UINT32 ixEthAccNewSrcMask;
  89
  90 /**
  91  * @brief Per port information data strucure.
  92  *
  93  * @ingroup IxEthAccPri
  94  *
  95  */
  96
  97 IxEthAccPortDataInfo ixEthAccPortData[IX_ETH_ACC_NUMBER_OF_PORTS];
  98
  99 PUBLIC IxEthAccStatus ixEthAccInit()
 100 {
 101 #ifdef CONFIG_IXP425_COMPONENT_ETHDB
 102   /*
 103    * Initialize Control plane
 104    */
 105   if (ixEthDBInit() != IX_ETH_ACC_SUCCESS)
 106   {
 107       IX_ETH_ACC_WARNING_LOG("ixEthAccInit: EthDB init failed\n", 0, 0, 0, 0, 0, 0);
 108
 109       return IX_ETH_ACC_FAIL;
 110   }
 111 #endif
 112
 113   if (IX_FEATURE_CTRL_SWCONFIG_ENABLED == ixFeatureCtrlSwConfigurationCheck (IX_FEATURECTRL_ETH_LEARNING))
 114   {
 115       ixEthAccNewSrcMask = (~0); /* want all the bits */
 116   }
 117   else
 118   {
 119       ixEthAccNewSrcMask = (~IX_ETHACC_NE_NEWSRCMASK); /* want all but the NewSrc bit */
 120   }
 121
 122   /*
 123    * Initialize Data plane
 124    */
 125    if ( ixEthAccInitDataPlane()  != IX_ETH_ACC_SUCCESS )
 126    {
 127       IX_ETH_ACC_WARNING_LOG("ixEthAccInit: data plane init failed\n", 0, 0, 0, 0, 0, 0);
 128
 129        return IX_ETH_ACC_FAIL;
 130    }
 131
 132
 133    if ( ixEthAccQMgrQueuesConfig() != IX_ETH_ACC_SUCCESS )
 134    {
 135       IX_ETH_ACC_WARNING_LOG("ixEthAccInit: queue config failed\n", 0, 0, 0, 0, 0, 0);
 136
 137        return IX_ETH_ACC_FAIL;
 138    }
 139
 140    /*
 141     * Initialize MII
 142     */
 143    if ( ixEthAccMiiInit() != IX_ETH_ACC_SUCCESS )
 144    {
 145       IX_ETH_ACC_WARNING_LOG("ixEthAccInit: Mii init failed\n", 0, 0, 0, 0, 0, 0);
 146
 147        return IX_ETH_ACC_FAIL;
 148    }
 149
 150    /*
 151     * Initialize MAC I/O memory
 152     */
 153    if (ixEthAccMacMemInit() != IX_ETH_ACC_SUCCESS)
 154    {
 155       IX_ETH_ACC_WARNING_LOG("ixEthAccInit: Mac init failed\n", 0, 0, 0, 0, 0, 0);
 156
 157      return IX_ETH_ACC_FAIL;
 158    }
 159
 160    /*
 161     * Initialize control plane interface lock
 162     */
 163    if (ixOsalMutexInit(&ixEthAccControlInterfaceMutex) != IX_SUCCESS)
 164    {
 165        IX_ETH_ACC_WARNING_LOG("ixEthAccInit: Control plane interface lock initialization failed\n", 0, 0, 0, 0, 0, 0);
 166
 167        return IX_ETH_ACC_FAIL;
 168    }
 169
 170    /* initialiasation is complete */
 171    ixEthAccServiceInit = TRUE;
 172
 173    return IX_ETH_ACC_SUCCESS;
 174
 175 }
 176
 177 PUBLIC void ixEthAccUnload(void)
 178 {
 179     IxEthAccPortId portId;
 180
 181     if ( IX_ETH_ACC_IS_SERVICE_INITIALIZED() )
 182     {
 183        /* check none of the port is still active */
 184        for (portId = 0; portId < IX_ETH_ACC_NUMBER_OF_PORTS; portId++)
 185        {
 186            if ( IX_ETH_IS_PORT_INITIALIZED(portId) )
 187            {
 188                if (ixEthAccMacState[portId].portDisableState == ACTIVE)
 189                {
 190                    IX_ETH_ACC_WARNING_LOG("ixEthAccUnload: port %u still active, bail out\n", portId, 0, 0, 0, 0, 0);
 191                    return;
 192                }
 193            }
 194        }
 195
 196        /* unmap the memory areas */
 197        ixEthAccMiiUnload();
 198        ixEthAccMacUnload();
 199
 200        /* set all ports as uninitialized */
 201        for (portId = 0; portId < IX_ETH_ACC_NUMBER_OF_PORTS; portId++)
 202        {
 203                ixEthAccPortData[portId].portInitialized = FALSE;
 204        }
 205
 206        /* uninitialize the service */
 207        ixEthAccServiceInit = FALSE;
 208    }
 209 }
 210
 211 PUBLIC IxEthAccStatus ixEthAccPortInit( IxEthAccPortId portId)
 212 {
 213
 214   IxEthAccStatus ret=IX_ETH_ACC_SUCCESS;
 215
 216    if ( ! IX_ETH_ACC_IS_SERVICE_INITIALIZED() )
 217    {
 218         return(IX_ETH_ACC_FAIL);
 219    }
 220
 221    /*
 222     * Check for valid port
 223     */
 224
 225    if ( ! IX_ETH_ACC_IS_PORT_VALID(portId) )
 226    {
 227        return (IX_ETH_ACC_INVALID_PORT);
 228    }
 229
 230    if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
 231    {
 232        IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot initialize Eth port.\n",(INT32) portId,0,0,0,0,0);
 233        return IX_ETH_ACC_SUCCESS ;
 234    }
 235
 236    if ( IX_ETH_IS_PORT_INITIALIZED(portId) )
 237    {
 238         /* Already initialized */
 239         return(IX_ETH_ACC_FAIL);
 240    }
 241
 242    if(ixEthAccMacInit(portId)!=IX_ETH_ACC_SUCCESS)
 243    {
 244        return IX_ETH_ACC_FAIL;
 245    }
 246
 247    /*
 248      * Set the port init flag.
 249      */
 250
 251     ixEthAccPortData[portId].portInitialized = TRUE;
 252
 253 #ifdef CONFIG_IXP425_COMPONENT_ETHDB
 254     /* init learning/filtering database structures for this port */
 255     ixEthDBPortInit(portId);
 256 #endif
 257
 258     return(ret);
 259 }
 260
 261