change console=tty0 to enable linux framebuffer console
[jz_uboot.git] / cpu / mcf52x2 / cpu.c
blobaa6b2bd670cea9c61025ccbe1478fb55c4446df7
1 /*
2 * (C) Copyright 2003
3 * Josef Baumgartner <josef.baumgartner@telex.de>
5 * MCF5282 additionals
6 * (C) Copyright 2005
7 * BuS Elektronik GmbH & Co. KG <esw@bus-elektronik.de>
9 * See file CREDITS for list of people who contributed to this
10 * project.
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
28 #include <common.h>
29 #include <watchdog.h>
30 #include <command.h>
32 #ifdef CONFIG_M5271
33 #include <asm/immap_5271.h>
34 #include <asm/m5271.h>
35 #endif
37 #ifdef CONFIG_M5272
38 #include <asm/immap_5272.h>
39 #include <asm/m5272.h>
40 #endif
42 #ifdef CONFIG_M5282
43 #include <asm/m5282.h>
44 #include <asm/immap_5282.h>
45 #endif
47 #ifdef CONFIG_M5249
48 #include <asm/m5249.h>
49 #endif
51 #ifdef CONFIG_M5271
52 int checkcpu (void)
54 char buf[32];
56 printf ("CPU: Freescale Coldfire MCF5271 at %s MHz\n", strmhz(buf, CFG_CLK));
57 return 0;
60 int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) {
61 mbar_writeByte(MCF_RCM_RCR,
62 MCF_RCM_RCR_SOFTRST | MCF_RCM_RCR_FRCRSTOUT);
63 return 0;
66 #if defined(CONFIG_WATCHDOG)
67 void watchdog_reset (void)
69 mbar_writeShort(MCF_WTM_WSR, 0x5555);
70 mbar_writeShort(MCF_WTM_WSR, 0xAAAA);
73 int watchdog_disable (void)
75 mbar_writeShort(MCF_WTM_WCR, 0);
76 return (0);
79 int watchdog_init (void)
81 mbar_writeShort(MCF_WTM_WCR, MCF_WTM_WCR_EN);
82 return (0);
84 #endif /* #ifdef CONFIG_WATCHDOG */
86 #endif
88 #ifdef CONFIG_M5272
89 int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) {
90 volatile wdog_t * wdp = (wdog_t *)(CFG_MBAR + MCFSIM_WRRR);
92 wdp->wdog_wrrr = 0;
93 udelay (1000);
95 /* enable watchdog, set timeout to 0 and wait */
96 wdp->wdog_wrrr = 1;
97 while (1);
99 /* we don't return! */
100 return 0;
103 int checkcpu(void) {
104 ulong *dirp = (ulong *)(CFG_MBAR + MCFSIM_DIR);
105 uchar msk;
106 char *suf;
108 puts ("CPU: ");
109 msk = (*dirp > 28) & 0xf;
110 switch (msk) {
111 case 0x2: suf = "1K75N"; break;
112 case 0x4: suf = "3K75N"; break;
113 default:
114 suf = NULL;
115 printf ("Freescale MCF5272 (Mask:%01x)\n", msk);
116 break;
119 if (suf)
120 printf ("Freescale MCF5272 %s\n", suf);
121 return 0;
124 #if defined(CONFIG_WATCHDOG)
125 /* Called by macro WATCHDOG_RESET */
126 void watchdog_reset (void)
128 volatile immap_t * regp = (volatile immap_t *)CFG_MBAR;
129 regp->wdog_reg.wdog_wcr = 0;
132 int watchdog_disable (void)
134 volatile immap_t *regp = (volatile immap_t *)CFG_MBAR;
136 regp->wdog_reg.wdog_wcr = 0; /* reset watchdog counter */
137 regp->wdog_reg.wdog_wirr = 0; /* disable watchdog interrupt */
138 regp->wdog_reg.wdog_wrrr = 0; /* disable watchdog timer */
140 puts ("WATCHDOG:disabled\n");
141 return (0);
144 int watchdog_init (void)
146 volatile immap_t *regp = (volatile immap_t *)CFG_MBAR;
148 regp->wdog_reg.wdog_wirr = 0; /* disable watchdog interrupt */
150 /* set timeout and enable watchdog */
151 regp->wdog_reg.wdog_wrrr = ((CONFIG_WATCHDOG_TIMEOUT * CFG_HZ) / (32768 * 1000)) - 1;
152 regp->wdog_reg.wdog_wcr = 0; /* reset watchdog counter */
154 puts ("WATCHDOG:enabled\n");
155 return (0);
157 #endif /* #ifdef CONFIG_WATCHDOG */
159 #endif /* #ifdef CONFIG_M5272 */
162 #ifdef CONFIG_M5282
163 int checkcpu (void)
165 unsigned char resetsource = MCFRESET_RSR;
167 printf ("CPU: Freescale Coldfire MCF5282 (PIN: %2.2x REV: %2.2x)\n",
168 MCFCCM_CIR>>8,MCFCCM_CIR & MCFCCM_CIR_PRN_MASK);
169 printf ("Reset:%s%s%s%s%s%s%s\n",
170 (resetsource & MCFRESET_RSR_LOL) ? " Loss of Lock" : "",
171 (resetsource & MCFRESET_RSR_LOC) ? " Loss of Clock" : "",
172 (resetsource & MCFRESET_RSR_EXT) ? " External" : "",
173 (resetsource & MCFRESET_RSR_POR) ? " Power On" : "",
174 (resetsource & MCFRESET_RSR_WDR) ? " Watchdog" : "",
175 (resetsource & MCFRESET_RSR_SOFT) ? " Software" : "",
176 (resetsource & MCFRESET_RSR_LVD) ? " Low Voltage" : ""
178 return 0;
181 int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
183 MCFRESET_RCR = MCFRESET_RCR_SOFTRST;
184 return 0;
186 #endif
188 #ifdef CONFIG_M5249 /* test-only: todo... */
189 int checkcpu (void)
191 char buf[32];
193 printf ("CPU: Freescale Coldfire MCF5249 at %s MHz\n", strmhz(buf, CFG_CLK));
194 return 0;
197 int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) {
198 /* enable watchdog, set timeout to 0 and wait */
199 mbar_writeByte(MCFSIM_SYPCR, 0xc0);
200 while (1);
202 /* we don't return! */
203 return 0;
205 #endif