cpu/mcf52x2/fec.c

   1 /*
   2  * (C) Copyright 2000-2004
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <malloc.h>
  26 #include <asm/fec.h>
  27
  28 #ifdef  CONFIG_M5271
  29 #include <asm/m5271.h>
  30 #include <asm/immap_5271.h>
  31 #endif
  32
  33 #ifdef  CONFIG_M5272
  34 #include <asm/m5272.h>
  35 #include <asm/immap_5272.h>
  36 #endif
  37
  38 #ifdef  CONFIG_M5282
  39 #include <asm/m5282.h>
  40 #include <asm/immap_5282.h>
  41 #endif
  42
  43 #include <net.h>
  44 #include <command.h>
  45
  46 #ifdef  CONFIG_M5272
  47 #define FEC_ADDR                (CFG_MBAR + 0x840)
  48 #endif
  49 #if defined(CONFIG_M5282) || defined(CONFIG_M5271)
  50 #define FEC_ADDR                (CFG_MBAR + 0x1000)
  51 #endif
  52
  53 #undef  ET_DEBUG
  54 #undef  MII_DEBUG
  55
  56 #if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(FEC_ENET)
  57
  58 #ifdef CFG_DISCOVER_PHY
  59 #include <miiphy.h>
  60 static void mii_discover_phy (void);
  61 #endif
  62
  63 /* Ethernet Transmit and Receive Buffers */
  64 #define DBUF_LENGTH  1520
  65
  66 #define TX_BUF_CNT 2
  67
  68 #define TOUT_LOOP 100
  69
  70 #define PKT_MAXBUF_SIZE         1518
  71 #define PKT_MINBUF_SIZE         64
  72 #define PKT_MAXBLR_SIZE         1520
  73
  74
  75 static char txbuf[DBUF_LENGTH];
  76
  77 static uint rxIdx;              /* index of the current RX buffer */
  78 static uint txIdx;              /* index of the current TX buffer */
  79
  80 /*
  81   * FEC Ethernet Tx and Rx buffer descriptors allocated at the
  82   *  immr->udata_bd address on Dual-Port RAM
  83   * Provide for Double Buffering
  84   */
  85
  86 typedef volatile struct CommonBufferDescriptor {
  87         cbd_t rxbd[PKTBUFSRX];  /* Rx BD */
  88         cbd_t txbd[TX_BUF_CNT]; /* Tx BD */
  89 } RTXBD;
  90
  91 static RTXBD *rtx = NULL;
  92
  93 int eth_send (volatile void *packet, int length)
  94 {
  95         int j, rc;
  96         volatile fec_t *fecp = (fec_t *) (FEC_ADDR);
  97
  98         /* section 16.9.23.3
  99          * Wait for ready
 100          */
 101         j = 0;
 102         while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY)
 103                && (j < TOUT_LOOP)) {
 104                 udelay (1);
 105                 j++;
 106         }
 107         if (j >= TOUT_LOOP) {
 108                 printf ("TX not ready\n");
 109         }
 110
 111         rtx->txbd[txIdx].cbd_bufaddr = (uint) packet;
 112         rtx->txbd[txIdx].cbd_datlen = length;
 113         rtx->txbd[txIdx].cbd_sc |= BD_ENET_TX_READY | BD_ENET_TX_LAST;
 114
 115         /* Activate transmit Buffer Descriptor polling */
 116         fecp->fec_x_des_active = 0x01000000;    /* Descriptor polling active    */
 117
 118         j = 0;
 119         while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY)
 120                && (j < TOUT_LOOP)) {
 121                 udelay (1);
 122                 j++;
 123         }
 124         if (j >= TOUT_LOOP) {
 125                 printf ("TX timeout\n");
 126         }
 127 #ifdef ET_DEBUG
 128         printf ("%s[%d] %s: cycles: %d    status: %x  retry cnt: %d\n",
 129                 __FILE__, __LINE__, __FUNCTION__, j, rtx->txbd[txIdx].cbd_sc,
 130                 (rtx->txbd[txIdx].cbd_sc & 0x003C) >> 2);
 131 #endif
 132
 133         /* return only status bits */ ;
 134         rc = (rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_STATS);
 135
 136         txIdx = (txIdx + 1) % TX_BUF_CNT;
 137
 138         return rc;
 139 }
 140
 141 int eth_rx (void)
 142 {
 143         int length;
 144         volatile fec_t *fecp = (fec_t *) FEC_ADDR;
 145
 146         for (;;) {
 147                 /* section 16.9.23.2 */
 148                 if (rtx->rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
 149                         length = -1;
 150                         break;  /* nothing received - leave for() loop */
 151                 }
 152
 153                 length = rtx->rxbd[rxIdx].cbd_datlen;
 154
 155                 if (rtx->rxbd[rxIdx].cbd_sc & 0x003f) {
 156 #ifdef ET_DEBUG
 157                         printf ("%s[%d] err: %x\n",
 158                                 __FUNCTION__, __LINE__,
 159                                 rtx->rxbd[rxIdx].cbd_sc);
 160 #endif
 161                 } else {
 162                         /* Pass the packet up to the protocol layers. */
 163                         NetReceive (NetRxPackets[rxIdx], length - 4);
 164                 }
 165
 166                 /* Give the buffer back to the FEC. */
 167                 rtx->rxbd[rxIdx].cbd_datlen = 0;
 168
 169                 /* wrap around buffer index when necessary */
 170                 if ((rxIdx + 1) >= PKTBUFSRX) {
 171                         rtx->rxbd[PKTBUFSRX - 1].cbd_sc =
 172                                 (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
 173                         rxIdx = 0;
 174                 } else {
 175                         rtx->rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
 176                         rxIdx++;
 177                 }
 178
 179                 /* Try to fill Buffer Descriptors */
 180                 fecp->fec_r_des_active = 0x01000000;    /* Descriptor polling active    */
 181         }
 182
 183         return length;
 184 }
 185
 186 /**************************************************************
 187  *
 188  * FEC Ethernet Initialization Routine
 189  *
 190  *************************************************************/
 191 #define FEC_ECNTRL_ETHER_EN     0x00000002
 192 #define FEC_ECNTRL_RESET        0x00000001
 193
 194 #define FEC_RCNTRL_BC_REJ       0x00000010
 195 #define FEC_RCNTRL_PROM         0x00000008
 196 #define FEC_RCNTRL_MII_MODE     0x00000004
 197 #define FEC_RCNTRL_DRT          0x00000002
 198 #define FEC_RCNTRL_LOOP         0x00000001
 199
 200 #define FEC_TCNTRL_FDEN         0x00000004
 201 #define FEC_TCNTRL_HBC          0x00000002
 202 #define FEC_TCNTRL_GTS          0x00000001
 203
 204 #define FEC_RESET_DELAY         50000
 205
 206 int eth_init (bd_t * bd)
 207 {
 208 #ifndef CFG_ENET_BD_BASE
 209         DECLARE_GLOBAL_DATA_PTR;
 210 #endif
 211         int i;
 212         volatile fec_t *fecp = (fec_t *) (FEC_ADDR);
 213
 214         /* Whack a reset.
 215          * A delay is required between a reset of the FEC block and
 216          * initialization of other FEC registers because the reset takes
 217          * some time to complete. If you don't delay, subsequent writes
 218          * to FEC registers might get killed by the reset routine which is
 219          * still in progress.
 220          */
 221         fecp->fec_ecntrl = FEC_ECNTRL_RESET;
 222         for (i = 0;
 223              (fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY);
 224              ++i) {
 225                 udelay (1);
 226         }
 227         if (i == FEC_RESET_DELAY) {
 228                 printf ("FEC_RESET_DELAY timeout\n");
 229                 return 0;
 230         }
 231
 232         /* We use strictly polling mode only
 233          */
 234         fecp->fec_imask = 0;
 235
 236         /* Clear any pending interrupt */
 237         fecp->fec_ievent = 0xffffffff;
 238
 239         /* Set station address   */
 240 #define ea bd->bi_enetaddr
 241         fecp->fec_addr_low = (ea[0] << 24) | (ea[1] << 16) |
 242                 (ea[2] << 8) | (ea[3]);
 243         fecp->fec_addr_high = (ea[4] << 24) | (ea[5] << 16);
 244 #ifdef ET_DEBUG
 245         printf ("Eth Addrs: %02x:%02x:%02x:%02x:%02x:%02x\n",
 246                 ea[0], ea[1], ea[2], ea[3], ea[4], ea[5]);
 247 #endif
 248 #undef ea
 249
 250 #ifdef CONFIG_M5271
 251         /* Clear multicast address hash table
 252          */
 253         fecp->fec_ghash_table_high = 0;
 254         fecp->fec_ghash_table_low = 0;
 255
 256         /* Clear individual address hash table
 257          */
 258         fecp->fec_ihash_table_high = 0;
 259         fecp->fec_ihash_table_low = 0;
 260 #else
 261         /* Clear multicast address hash table
 262          */
 263 #ifdef  CONFIG_M5282
 264         fecp->fec_ihash_table_high = 0;
 265         fecp->fec_ihash_table_low = 0;
 266 #else
 267         fecp->fec_hash_table_high = 0;
 268         fecp->fec_hash_table_low = 0;
 269 #endif
 270 #endif
 271
 272         /* Set maximum receive buffer size.
 273          */
 274         fecp->fec_r_buff_size = PKT_MAXBLR_SIZE;
 275
 276         /*
 277          * Setup Buffers and Buffer Desriptors
 278          */
 279         rxIdx = 0;
 280         txIdx = 0;
 281
 282         if (!rtx) {
 283 #ifdef CFG_ENET_BD_BASE
 284                 rtx = (RTXBD *) CFG_ENET_BD_BASE;
 285 #else
 286                 rtx = (RTXBD *) (CFG_MONITOR_BASE+gd->reloc_off -
 287                                  (((PKTBUFSRX+TX_BUF_CNT)*+sizeof(cbd_t)
 288                                   +0xFF)
 289                                   & ~0xFF)
 290                                 );
 291                 debug("set ENET_DB_BASE to %lX\n",(long) rtx);
 292 #endif
 293         }
 294
 295         /*
 296          * Setup Receiver Buffer Descriptors (13.14.24.18)
 297          * Settings:
 298          *     Empty, Wrap
 299          */
 300         for (i = 0; i < PKTBUFSRX; i++) {
 301                 rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
 302                 rtx->rxbd[i].cbd_datlen = 0;    /* Reset */
 303                 rtx->rxbd[i].cbd_bufaddr = (uint) NetRxPackets[i];
 304         }
 305         rtx->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
 306
 307         /*
 308          * Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
 309          * Settings:
 310          *    Last, Tx CRC
 311          */
 312         for (i = 0; i < TX_BUF_CNT; i++) {
 313                 rtx->txbd[i].cbd_sc = BD_ENET_TX_LAST | BD_ENET_TX_TC;
 314                 rtx->txbd[i].cbd_datlen = 0;    /* Reset */
 315                 rtx->txbd[i].cbd_bufaddr = (uint) (&txbuf[0]);
 316         }
 317         rtx->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
 318
 319         /* Set receive and transmit descriptor base
 320          */
 321         fecp->fec_r_des_start = (unsigned int) (&rtx->rxbd[0]);
 322         fecp->fec_x_des_start = (unsigned int) (&rtx->txbd[0]);
 323
 324         /* Enable MII mode
 325          */
 326
 327 #if 0   /* Full duplex mode */
 328         fecp->fec_r_cntrl = FEC_RCNTRL_MII_MODE;
 329         fecp->fec_x_cntrl = FEC_TCNTRL_FDEN;
 330 #else   /* Half duplex mode */
 331         fecp->fec_r_cntrl = (PKT_MAXBUF_SIZE << 16); /* set max frame length */
 332         fecp->fec_r_cntrl |= FEC_RCNTRL_MII_MODE | FEC_RCNTRL_DRT;
 333         fecp->fec_x_cntrl = 0;
 334 #endif
 335         /* Set MII speed */
 336         fecp->fec_mii_speed = (((CFG_CLK / 2) / (2500000 / 10)) + 5) / 10;
 337         fecp->fec_mii_speed *= 2;
 338
 339         /* Configure port B for MII.
 340          */
 341         /* port initialization was already made in cpu_init_f() */
 342
 343         /* Now enable the transmit and receive processing
 344          */
 345         fecp->fec_ecntrl = FEC_ECNTRL_ETHER_EN;
 346
 347 #ifdef CFG_DISCOVER_PHY
 348         /* wait for the PHY to wake up after reset */
 349         mii_discover_phy ();
 350 #endif
 351
 352         /* And last, try to fill Rx Buffer Descriptors */
 353         fecp->fec_r_des_active = 0x01000000;    /* Descriptor polling active    */
 354
 355         return 1;
 356 }
 357
 358 void eth_halt (void)
 359 {
 360         volatile fec_t *fecp = (fec_t *) FEC_ADDR;
 361
 362         fecp->fec_ecntrl = 0;
 363 }
 364
 365
 366 #if defined(CFG_DISCOVER_PHY) || (CONFIG_COMMANDS & CFG_CMD_MII)
 367
 368 static int phyaddr = -1;        /* didn't find a PHY yet */
 369 static uint phytype;
 370
 371 /* Make MII read/write commands for the FEC.
 372 */
 373
 374 #define mk_mii_read(ADDR, REG)  (0x60020000 | ((ADDR << 23) | \
 375                                                 (REG & 0x1f) << 18))
 376
 377 #define mk_mii_write(ADDR, REG, VAL)    (0x50020000 | ((ADDR << 23) | \
 378                                                 (REG & 0x1f) << 18) | \
 379                                                 (VAL & 0xffff))
 380
 381 /* Interrupt events/masks.
 382 */
 383 #define FEC_ENET_HBERR  ((uint)0x80000000)      /* Heartbeat error */
 384 #define FEC_ENET_BABR   ((uint)0x40000000)      /* Babbling receiver */
 385 #define FEC_ENET_BABT   ((uint)0x20000000)      /* Babbling transmitter */
 386 #define FEC_ENET_GRA    ((uint)0x10000000)      /* Graceful stop complete */
 387 #define FEC_ENET_TXF    ((uint)0x08000000)      /* Full frame transmitted */
 388 #define FEC_ENET_TXB    ((uint)0x04000000)      /* A buffer was transmitted */
 389 #define FEC_ENET_RXF    ((uint)0x02000000)      /* Full frame received */
 390 #define FEC_ENET_RXB    ((uint)0x01000000)      /* A buffer was received */
 391 #define FEC_ENET_MII    ((uint)0x00800000)      /* MII interrupt */
 392 #define FEC_ENET_EBERR  ((uint)0x00400000)      /* SDMA bus error */
 393
 394 /* PHY identification
 395  */
 396 #define PHY_ID_LXT970           0x78100000      /* LXT970 */
 397 #define PHY_ID_LXT971           0x001378e0      /* LXT971 and 972 */
 398 #define PHY_ID_82555            0x02a80150      /* Intel 82555 */
 399 #define PHY_ID_QS6612           0x01814400      /* QS6612 */
 400 #define PHY_ID_AMD79C784        0x00225610      /* AMD 79C784 */
 401 #define PHY_ID_LSI80225         0x0016f870      /* LSI 80225 */
 402 #define PHY_ID_LSI80225B        0x0016f880      /* LSI 80225/B */
 403
 404 /* send command to phy using mii, wait for result */
 405 static uint mii_send (uint mii_cmd)
 406 {
 407         uint mii_reply;
 408         volatile fec_t *ep = (fec_t *) (FEC_ADDR);
 409
 410         ep->fec_mii_data = mii_cmd;     /* command to phy */
 411
 412         /* wait for mii complete */
 413         while (!(ep->fec_ievent & FEC_ENET_MII));       /* spin until done */
 414         mii_reply = ep->fec_mii_data;   /* result from phy */
 415         ep->fec_ievent = FEC_ENET_MII;  /* clear MII complete */
 416 #ifdef ET_DEBUG
 417         printf ("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
 418                 __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
 419 #endif
 420         return (mii_reply & 0xffff);    /* data read from phy */
 421 }
 422 #endif /* CFG_DISCOVER_PHY || (CONFIG_COMMANDS & CFG_CMD_MII) */
 423
 424 #if defined(CFG_DISCOVER_PHY)
 425 static void mii_discover_phy (void)
 426 {
 427 #define MAX_PHY_PASSES 11
 428         uint phyno;
 429         int pass;
 430
 431         phyaddr = -1;           /* didn't find a PHY yet */
 432         for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
 433                 if (pass > 1) {
 434                         /* PHY may need more time to recover from reset.
 435                          * The LXT970 needs 50ms typical, no maximum is
 436                          * specified, so wait 10ms before try again.
 437                          * With 11 passes this gives it 100ms to wake up.
 438                          */
 439                         udelay (10000); /* wait 10ms */
 440                 }
 441                 for (phyno = 1; phyno < 32 && phyaddr < 0; ++phyno) {
 442                         phytype = mii_send (mk_mii_read (phyno, PHY_PHYIDR1));
 443 #ifdef ET_DEBUG
 444                         printf ("PHY type 0x%x pass %d type ", phytype, pass);
 445 #endif
 446                         if (phytype != 0xffff) {
 447                                 phyaddr = phyno;
 448                                 phytype <<= 16;
 449                                 phytype |= mii_send (mk_mii_read (phyno,
 450                                                                   PHY_PHYIDR2));
 451
 452 #ifdef ET_DEBUG
 453                                 printf ("PHY @ 0x%x pass %d type ", phyno,
 454                                         pass);
 455                                 switch (phytype & 0xfffffff0) {
 456                                 case PHY_ID_LXT970:
 457                                         printf ("LXT970\n");
 458                                         break;
 459                                 case PHY_ID_LXT971:
 460                                         printf ("LXT971\n");
 461                                         break;
 462                                 case PHY_ID_82555:
 463                                         printf ("82555\n");
 464                                         break;
 465                                 case PHY_ID_QS6612:
 466                                         printf ("QS6612\n");
 467                                         break;
 468                                 case PHY_ID_AMD79C784:
 469                                         printf ("AMD79C784\n");
 470                                         break;
 471                                 case PHY_ID_LSI80225B:
 472                                         printf ("LSI L80225/B\n");
 473                                         break;
 474                                 default:
 475                                         printf ("0x%08x\n", phytype);
 476                                         break;
 477                                 }
 478 #endif
 479                         }
 480                 }
 481         }
 482         if (phyaddr < 0) {
 483                 printf ("No PHY device found.\n");
 484         }
 485 }
 486 #endif /* CFG_DISCOVER_PHY */
 487
 488 #if (CONFIG_COMMANDS & CFG_CMD_MII) && !defined(CONFIG_BITBANGMII)
 489
 490 static int mii_init_done = 0;
 491
 492 /****************************************************************************
 493  * mii_init -- Initialize the MII for MII command without ethernet
 494  * This function is a subset of eth_init
 495  ****************************************************************************
 496  */
 497 void mii_init (void)
 498 {
 499         volatile fec_t *fecp = (fec_t *) (FEC_ADDR);
 500
 501         int i;
 502
 503         if (mii_init_done != 0) {
 504                 return;
 505         }
 506
 507         /* Whack a reset.
 508          * A delay is required between a reset of the FEC block and
 509          * initialization of other FEC registers because the reset takes
 510          * some time to complete. If you don't delay, subsequent writes
 511          * to FEC registers might get killed by the reset routine which is
 512          * still in progress.
 513          */
 514
 515         fecp->fec_ecntrl = FEC_ECNTRL_RESET;
 516         for (i = 0;
 517              (fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY);
 518              ++i) {
 519                 udelay (1);
 520         }
 521         if (i == FEC_RESET_DELAY) {
 522                 printf ("FEC_RESET_DELAY timeout\n");
 523                 return;
 524         }
 525
 526         /* We use strictly polling mode only
 527          */
 528         fecp->fec_imask = 0;
 529
 530         /* Clear any pending interrupt
 531          */
 532         fecp->fec_ievent = 0xffffffff;
 533
 534         /* Set MII speed */
 535         fecp->fec_mii_speed = 0x0e;
 536
 537         /* Configure port B for MII.
 538          */
 539         /* port initialization was already made in cpu_init_f() */
 540
 541         /* Now enable the transmit and receive processing */
 542         fecp->fec_ecntrl = FEC_ECNTRL_ETHER_EN;
 543
 544         mii_init_done = 1;
 545 }
 546
 547 /*****************************************************************************
 548  * Read and write a MII PHY register, routines used by MII Utilities
 549  *
 550  * FIXME: These routines are expected to return 0 on success, but mii_send
 551  *        does _not_ return an error code. Maybe 0xFFFF means error, i.e.
 552  *        no PHY connected...
 553  *        For now always return 0.
 554  * FIXME: These routines only work after calling eth_init() at least once!
 555  *        Otherwise they hang in mii_send() !!! Sorry!
 556  *****************************************************************************/
 557
 558 int mcf52x2_miiphy_read (char *devname, unsigned char addr,
 559                 unsigned char reg, unsigned short *value)
 560 {
 561         short rdreg;            /* register working value */
 562
 563 #ifdef MII_DEBUG
 564         printf ("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
 565 #endif
 566         rdreg = mii_send (mk_mii_read (addr, reg));
 567
 568         *value = rdreg;
 569
 570 #ifdef MII_DEBUG
 571         printf ("0x%04x\n", *value);
 572 #endif
 573
 574         return 0;
 575 }
 576
 577 int mcf52x2_miiphy_write (char *devname, unsigned char addr,
 578                 unsigned char reg, unsigned short value)
 579 {
 580         short rdreg;            /* register working value */
 581
 582 #ifdef MII_DEBUG
 583         printf ("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
 584 #endif
 585
 586         rdreg = mii_send (mk_mii_write (addr, reg, value));
 587
 588 #ifdef MII_DEBUG
 589         printf ("0x%04x\n", value);
 590 #endif
 591
 592         return 0;
 593 }
 594 #endif /* (CONFIG_COMMANDS & CFG_CMD_MII) && !defined(CONFIG_BITBANGMII) */
 595 #endif /* CFG_CMD_NET, FEC_ENET */
 596
 597 int mcf52x2_miiphy_initialize(bd_t *bis)
 598 {
 599 #if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(FEC_ENET)
 600 #if (CONFIG_COMMANDS & CFG_CMD_MII) && !defined(CONFIG_BITBANGMII)
 601         miiphy_register("mcf52x2phy", mcf52x2_miiphy_read, mcf52x2_miiphy_write);
 602 #endif
 603 #endif
 604         return 0;
 605 }