cpu/mips/jz_cs8900.c

   1 /*
   2  * Cirrus Logic CS8900A Ethernet
   3  *
   4  * (C) 2003 Wolfgang Denk, wd@denx.de
   5  *     Extension to synchronize ethaddr environment variable
   6  *     against value in EEPROM
   7  *
   8  * (C) Copyright 2002
   9  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  10  * Marius Groeger <mgroeger@sysgo.de>
  11  *
  12  * Copyright (C) 1999 Ben Williamson <benw@pobox.com>
  13  *
  14  * See file CREDITS for list of people who contributed to this
  15  * project.
  16  *
  17  * This program is loaded into SRAM in bootstrap mode, where it waits
  18  * for commands on UART1 to read and write memory, jump to code etc.
  19  * A design goal for this program is to be entirely independent of the
  20  * target board.  Anything with a CL-PS7111 or EP7211 should be able to run
  21  * this code in bootstrap mode.  All the board specifics can be handled on
  22  * the host.
  23  *
  24  * This program is free software; you can redistribute it and/or modify
  25  * it under the terms of the GNU General Public License as published by
  26  * the Free Software Foundation; either version 2 of the License, or
  27  * (at your option) any later version.
  28  *
  29  * This program is distributed in the hope that it will be useful,
  30  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  31  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  32  * GNU General Public License for more details.
  33  *
  34  * You should have received a copy of the GNU General Public License
  35  * along with this program; if not, write to the Free Software
  36  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  37  */
  38 #include <config.h>
  39 #ifndef CONFIG_FPGA
  40 #ifdef CONFIG_JZ4740
  41 #include <common.h>
  42 #include <malloc.h>
  43 #include <asm/jz4740.h>
  44 #include <net.h>
  45 struct eth_device *dev;
  46 #define CS8900_BASE ((u32)(dev->iobase))
  47 #define CONFIG_DRIVER_CS8900
  48 #define CS8900_BUS16
  49 #include <command.h>
  50 #include <asm/io.h>
  51
  52 #include "jz_cs8900.h"
  53
  54 #ifdef CONFIG_DRIVER_CS8900
  55
  56 #if (CONFIG_COMMANDS & CFG_CMD_NET)
  57
  58 #undef DEBUG
  59
  60 /* packet page register access functions */
  61
  62 #ifdef CS8900_BUS32
  63 /* we don't need 16 bit initialisation on 32 bit bus */
  64 #define get_reg_init_bus(x) get_reg((x))
  65 #else
  66 static unsigned short get_reg_init_bus (int regno)
  67 {
  68         /* force 16 bit busmode */
  69         volatile unsigned char c;
  70     //c = CS8900_BUS16_0;
  71         //c = CS8900_BUS16_1;
  72         //c = CS8900_BUS16_0;
  73         //c = CS8900_BUS16_1;
  74         //c = CS8900_BUS16_0;
  75
  76         CS8900_PPTR = regno;
  77     //udelay(100);
  78
  79         return (unsigned short) CS8900_PDATA;
  80 }
  81 #endif
  82
  83 static unsigned short get_reg (int regno)
  84 {
  85         CS8900_PPTR = regno;
  86         return (unsigned short) CS8900_PDATA;
  87 }
  88
  89
  90 static void put_reg (int regno, unsigned short val)
  91 {
  92         CS8900_PPTR = regno;
  93         CS8900_PDATA = val;
  94 }
  95
  96 static void eth_reset (void)
  97 {
  98         int tmo;
  99         unsigned short us;
 100
 101         /* reset NIC */
 102         put_reg (PP_SelfCTL, get_reg (PP_SelfCTL) | PP_SelfCTL_Reset);
 103
 104         /* wait for 200ms */
 105         udelay (200000);
 106         /* Wait until the chip is reset */
 107
 108         tmo = get_timer (0) + 1 * CFG_HZ;
 109         while ((((us = get_reg_init_bus (PP_SelfSTAT)) & PP_SelfSTAT_InitD) == 0)
 110                    && tmo < get_timer (0))
 111                 /*NOP*/;
 112 }
 113
 114 static void eth_reginit (void)
 115 {
 116         /* receive only error free packets addressed to this card */
 117         put_reg (PP_RxCTL, PP_RxCTL_IA | PP_RxCTL_Broadcast | PP_RxCTL_RxOK);
 118         /* do not generate any interrupts on receive operations */
 119         put_reg (PP_RxCFG, 0);
 120         /* do not generate any interrupts on transmit operations */
 121         put_reg (PP_TxCFG, 0);
 122         /* do not generate any interrupts on buffer operations */
 123         put_reg (PP_BufCFG, 0);
 124         /* enable transmitter/receiver mode */
 125         put_reg (PP_LineCTL, PP_LineCTL_Rx | PP_LineCTL_Tx);
 126 }
 127
 128 static void cs8900_get_enetaddr (uchar * addr)
 129 {
 130         int i;
 131         unsigned char env_enetaddr[6];
 132         char *tmp = getenv ("ethaddr");
 133         char *end;
 134
 135         for (i=0; i<6; i++) {
 136                 env_enetaddr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0;
 137                 if (tmp)
 138                         tmp = (*end) ? end+1 : end;
 139         }
 140
 141         /* verify chip id */
 142         if (get_reg_init_bus (PP_ChipID) != 0x630e)
 143                 return;
 144         eth_reset ();
 145         if ((get_reg (PP_SelfST) & (PP_SelfSTAT_EEPROM | PP_SelfSTAT_EEPROM_OK)) ==
 146                         (PP_SelfSTAT_EEPROM | PP_SelfSTAT_EEPROM_OK)) {
 147
 148                 /* Load the MAC from EEPROM */
 149                 for (i = 0; i < 6 / 2; i++) {
 150                         unsigned int Addr;
 151
 152                         Addr = get_reg (PP_IA + i * 2);
 153                         addr[i * 2] = Addr & 0xFF;
 154                         addr[i * 2 + 1] = Addr >> 8;
 155                 }
 156
 157                 if (memcmp(env_enetaddr, "\0\0\0\0\0\0", 6) != 0 &&
 158                     memcmp(env_enetaddr, addr, 6) != 0) {
 159                         printf ("\nWarning: MAC addresses don't match:\n");
 160                         printf ("\tHW MAC address:  "
 161                                 "%02X:%02X:%02X:%02X:%02X:%02X\n",
 162                                 addr[0], addr[1],
 163                                 addr[2], addr[3],
 164                                 addr[4], addr[5] );
 165                         printf ("\t\"ethaddr\" value: "
 166                                 "%02X:%02X:%02X:%02X:%02X:%02X\n",
 167                                 env_enetaddr[0], env_enetaddr[1],
 168                                 env_enetaddr[2], env_enetaddr[3],
 169                                 env_enetaddr[4], env_enetaddr[5]) ;
 170                         debug ("### Set MAC addr from environment\n");
 171                         memcpy (addr, env_enetaddr, 6);
 172                 }
 173                 if (!tmp) {
 174                         char ethaddr[20];
 175                         sprintf (ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X",
 176                                  addr[0], addr[1],
 177                                  addr[2], addr[3],
 178                                  addr[4], addr[5]) ;
 179                         debug ("### Set environment from HW MAC addr = \"%s\"\n",                               ethaddr);
 180                         setenv ("ethaddr", ethaddr);
 181                 }
 182
 183         }
 184 }
 185
 186 static void jz_eth_halt (struct eth_device *dev)
 187 {
 188         /* disable transmitter/receiver mode */
 189         put_reg (PP_LineCTL, 0);
 190
 191         /* "shutdown" to show ChipID or kernel wouldn't find he cs8900 ... */
 192         get_reg_init_bus (PP_ChipID);
 193 }
 194
 195 static int jz_eth_init (struct eth_device* dev, bd_t * bd)
 196 {
 197     u16 id;
 198
 199     dev = dev;
 200
 201
 202     /* verify chip id */
 203         id = get_reg_init_bus (PP_ChipID);
 204         if (id != 0x630e) {
 205                 printf ("CS8900 jz_eth_init error!\n");
 206                 return 0;
 207         }
 208
 209         eth_reset ();
 210         /* set the ethernet address */
 211         //printf("MAC = %02x:%02x:%02x:%02x:%02x:%02x\r\n",
 212         //         bd->bi_enetaddr[5],bd->bi_enetaddr[4],
 213         //         bd->bi_enetaddr[3],bd->bi_enetaddr[2],
 214         //         bd->bi_enetaddr[1],bd->bi_enetaddr[0]);
 215
 216         put_reg (PP_IA + 0, bd->bi_enetaddr[0] | (bd->bi_enetaddr[1] << 8));
 217         put_reg (PP_IA + 2, bd->bi_enetaddr[2] | (bd->bi_enetaddr[3] << 8));
 218         put_reg (PP_IA + 4, bd->bi_enetaddr[4] | (bd->bi_enetaddr[5] << 8));
 219
 220         eth_reginit ();
 221         return 0;
 222 }
 223
 224 /* Get a data block via Ethernet */
 225 static int jz_eth_rx (struct eth_device* dev)
 226 {
 227         int i;
 228         unsigned short rxlen;
 229         unsigned short *addr;
 230         unsigned short status;
 231     dev = dev;
 232         status = get_reg (PP_RER);
 233
 234         if ((status & PP_RER_RxOK) == 0)
 235                 return 0;
 236
 237         status = CS8900_RTDATA;         /* stat */
 238         rxlen = CS8900_RTDATA;          /* len */
 239
 240 #ifdef DEBUG
 241         if (rxlen > PKTSIZE_ALIGN + PKTALIGN)
 242                 printf ("packet too big!\n");
 243 #endif
 244         for (addr = (unsigned short *) NetRxPackets[0], i = rxlen >> 1; i > 0;
 245                  i--)
 246                 *addr++ = CS8900_RTDATA;
 247         if (rxlen & 1)
 248                 *addr++ = CS8900_RTDATA;
 249
 250         /* Pass the packet up to the protocol layers. */
 251         NetReceive (NetRxPackets[0], rxlen);
 252
 253         return rxlen;
 254 }
 255
 256 /* Send a data block via Ethernet. */
 257 static int jz_eth_send (struct eth_device* dev,volatile void *packet, int length)
 258 {
 259         volatile unsigned short *addr;
 260         int tmo;
 261         unsigned short s;
 262     dev = dev;
 263
 264 retry:
 265         /* initiate a transmit sequence */
 266         CS8900_TxCMD = PP_TxCmd_TxStart_Full;
 267         CS8900_TxLEN = length;
 268
 269         /* Test to see if the chip has allocated memory for the packet */
 270         if ((get_reg (PP_BusSTAT) & PP_BusSTAT_TxRDY) == 0) {
 271                 /* Oops... this should not happen! */
 272 #ifdef DEBUG
 273                 printf ("cs: unable to send packet; retrying...\n");
 274 #endif
 275                 for (tmo = get_timer (0) + 5 * CFG_HZ; get_timer (0) < tmo;)
 276                         /*NOP*/;
 277                 eth_reset ();
 278                 eth_reginit ();
 279                 goto retry;
 280         }
 281
 282         /* Write the contents of the packet */
 283         /* assume even number of bytes */
 284         for (addr = packet; length > 0; length -= 2)
 285                 CS8900_RTDATA = *addr++;
 286
 287         /* wait for transfer to succeed */
 288         tmo = get_timer (0) + 5 * CFG_HZ;
 289         while ((s = get_reg (PP_TER) & ~0x1F) == 0) {
 290                 if (get_timer (0) >= tmo)
 291                         break;
 292         }
 293
 294         /* nothing */ ;
 295         if ((s & (PP_TER_CRS | PP_TER_TxOK)) != PP_TER_TxOK) {
 296 #ifdef DEBUG
 297                 printf ("\ntransmission error %#x\n", s);
 298 #endif
 299         }
 300
 301         return 0;
 302 }
 303
 304 static void cs8900_e2prom_ready(void)
 305 {
 306         while(get_reg(PP_SelfST) & SI_BUSY);
 307 }
 308
 309 /***********************************************************/
 310 /* read a 16-bit word out of the EEPROM                    */
 311 /***********************************************************/
 312
 313 static int cs8900_e2prom_read(unsigned char addr, unsigned short *value)
 314 {
 315         cs8900_e2prom_ready();
 316         put_reg(PP_EECMD, EEPROM_READ_CMD | addr);
 317         cs8900_e2prom_ready();
 318         *value = get_reg(PP_EEData);
 319
 320         return 0;
 321 }
 322
 323
 324 /***********************************************************/
 325 /* write a 16-bit word into the EEPROM                     */
 326 /***********************************************************/
 327
 328 static int cs8900_e2prom_write(unsigned char addr, unsigned short value)
 329 {
 330         cs8900_e2prom_ready();
 331         put_reg(PP_EECMD, EEPROM_WRITE_EN);
 332         cs8900_e2prom_ready();
 333         put_reg(PP_EEData, value);
 334         put_reg(PP_EECMD, EEPROM_WRITE_CMD | addr);
 335         cs8900_e2prom_ready();
 336         put_reg(PP_EECMD, EEPROM_WRITE_DIS);
 337         cs8900_e2prom_ready();
 338
 339         return 0;
 340 }
 341 int jz_enet_initialize(bd_t *bis)
 342 {
 343
 344     u32 reg;
 345
 346         dev = (struct eth_device *) malloc(sizeof *dev);
 347         memset(dev, 0, sizeof *dev);
 348 #define RD_N_PIN (32 + 29)
 349 #define WE_N_PIN (32 + 30)
 350 #define CS4_PIN (32 + 28)
 351         __gpio_as_func0(CS4_PIN);
 352         __gpio_as_func0(RD_N_PIN);
 353         __gpio_as_func0(WE_N_PIN);
 354
 355     reg = REG_EMC_SMCR4;
 356         reg = (reg & (~EMC_SMCR_BW_MASK)) | EMC_SMCR_BW_16BIT;
 357         REG_EMC_SMCR4 = reg;
 358         sprintf(dev->name, "JZ ETHERNET");
 359         dev->iobase = 0xa8000000;
 360         dev->priv   = 0;
 361         dev->init   = jz_eth_init;
 362         dev->halt   = jz_eth_halt;
 363         dev->send   = jz_eth_send;
 364         dev->recv   = jz_eth_rx;
 365
 366         eth_register(dev);
 367
 368         return 1;
 369 }
 370
 371
 372 #endif  /* COMMANDS & CFG_NET */
 373
 374 #endif  /* CONFIG_DRIVER_CS8900 */
 375 #endif  /* CONFIG_JZ4740 */
 376 #endif  /* !CONFIG_FPGA */