cpu/ppc4xx/ndfc.c

   1 /*
   2  * Overview:
   3  *   Platform independend driver for NDFC (NanD Flash Controller)
   4  *   integrated into EP440 cores
   5  *
   6  * (C) Copyright 2006
   7  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   8  *
   9  * Based on original work by
  10  *      Thomas Gleixner
  11  *      Copyright 2006 IBM
  12  *
  13  * See file CREDITS for list of people who contributed to this
  14  * project.
  15  *
  16  * This program is free software; you can redistribute it and/or
  17  * modify it under the terms of the GNU General Public License as
  18  * published by the Free Software Foundation; either version 2 of
  19  * the License, or (at your option) any later version.
  20  *
  21  * This program is distributed in the hope that it will be useful,
  22  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  23  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  24  * GNU General Public License for more details.
  25  *
  26  * You should have received a copy of the GNU General Public License
  27  * along with this program; if not, write to the Free Software
  28  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  29  * MA 02111-1307 USA
  30  */
  31
  32 #include <common.h>
  33
  34 #if (CONFIG_COMMANDS & CFG_CMD_NAND) && !defined(CFG_NAND_LEGACY) && \
  35         (defined(CONFIG_440EP) || defined(CONFIG_440GR) ||           \
  36          defined(CONFIG_440EPX) || defined(CONFIG_440GRX))
  37
  38 #include <nand.h>
  39 #include <linux/mtd/ndfc.h>
  40 #include <asm/processor.h>
  41 #include <ppc440.h>
  42
  43 static u8 hwctl = 0;
  44
  45 static void ndfc_hwcontrol(struct mtd_info *mtdinfo, int cmd)
  46 {
  47         switch (cmd) {
  48         case NAND_CTL_SETCLE:
  49                 hwctl |= 0x1;
  50                 break;
  51
  52         case NAND_CTL_CLRCLE:
  53                 hwctl &= ~0x1;
  54                 break;
  55
  56         case NAND_CTL_SETALE:
  57                 hwctl |= 0x2;
  58                 break;
  59
  60         case NAND_CTL_CLRALE:
  61                 hwctl &= ~0x2;
  62                 break;
  63         }
  64 }
  65
  66 static void ndfc_write_byte(struct mtd_info *mtdinfo, u_char byte)
  67 {
  68         struct nand_chip *this = mtdinfo->priv;
  69         ulong base = (ulong) this->IO_ADDR_W & 0xfffffffc;
  70
  71         if (hwctl & 0x1)
  72                 out8(base + NDFC_CMD, byte);
  73         else if (hwctl & 0x2)
  74                 out8(base + NDFC_ALE, byte);
  75         else
  76                 out8(base + NDFC_DATA, byte);
  77 }
  78
  79 static u_char ndfc_read_byte(struct mtd_info *mtdinfo)
  80 {
  81         struct nand_chip *this = mtdinfo->priv;
  82         ulong base = (ulong) this->IO_ADDR_W & 0xfffffffc;
  83
  84         return (in8(base + NDFC_DATA));
  85 }
  86
  87 static int ndfc_dev_ready(struct mtd_info *mtdinfo)
  88 {
  89         struct nand_chip *this = mtdinfo->priv;
  90         ulong base = (ulong) this->IO_ADDR_W & 0xfffffffc;
  91
  92         while (!(in32(base + NDFC_STAT) & NDFC_STAT_IS_READY))
  93                 ;
  94
  95         return 1;
  96 }
  97
  98 #ifndef CONFIG_NAND_SPL
  99 /*
 100  * Don't use these speedup functions in NAND boot image, since the image
 101  * has to fit into 4kByte.
 102  */
 103
 104 /*
 105  * Speedups for buffer read/write/verify
 106  *
 107  * NDFC allows 32bit read/write of data. So we can speed up the buffer
 108  * functions. No further checking, as nand_base will always read/write
 109  * page aligned.
 110  */
 111 static void ndfc_read_buf(struct mtd_info *mtdinfo, uint8_t *buf, int len)
 112 {
 113         struct nand_chip *this = mtdinfo->priv;
 114         ulong base = (ulong) this->IO_ADDR_W & 0xfffffffc;
 115         uint32_t *p = (uint32_t *) buf;
 116
 117         for (;len > 0; len -= 4)
 118                 *p++ = in32(base + NDFC_DATA);
 119 }
 120
 121 static void ndfc_write_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len)
 122 {
 123         struct nand_chip *this = mtdinfo->priv;
 124         ulong base = (ulong) this->IO_ADDR_W & 0xfffffffc;
 125         uint32_t *p = (uint32_t *) buf;
 126
 127         for (; len > 0; len -= 4)
 128                 out32(base + NDFC_DATA, *p++);
 129 }
 130
 131 static int ndfc_verify_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len)
 132 {
 133         struct nand_chip *this = mtdinfo->priv;
 134         ulong base = (ulong) this->IO_ADDR_W & 0xfffffffc;
 135         uint32_t *p = (uint32_t *) buf;
 136
 137         for (; len > 0; len -= 4)
 138                 if (*p++ != in32(base + NDFC_DATA))
 139                         return -1;
 140
 141         return 0;
 142 }
 143 #endif /* #ifndef CONFIG_NAND_SPL */
 144
 145 void board_nand_select_device(struct nand_chip *nand, int chip)
 146 {
 147         /*
 148          * Don't use "chip" to address the NAND device,
 149          * generate the cs from the address where it is encoded.
 150          */
 151         int cs = (ulong)nand->IO_ADDR_W & 0x00000003;
 152         ulong base = (ulong)nand->IO_ADDR_W & 0xfffffffc;
 153
 154         /* Set NandFlash Core Configuration Register */
 155         /* 1col x 2 rows */
 156         out32(base + NDFC_CCR, 0x00000000 | (cs << 24));
 157 }
 158
 159 void board_nand_init(struct nand_chip *nand)
 160 {
 161         int cs = (ulong)nand->IO_ADDR_W & 0x00000003;
 162         ulong base = (ulong)nand->IO_ADDR_W & 0xfffffffc;
 163
 164         nand->eccmode = NAND_ECC_SOFT;
 165
 166         nand->hwcontrol  = ndfc_hwcontrol;
 167         nand->read_byte  = ndfc_read_byte;
 168         nand->write_byte = ndfc_write_byte;
 169         nand->dev_ready  = ndfc_dev_ready;
 170
 171 #ifndef CONFIG_NAND_SPL
 172         nand->write_buf  = ndfc_write_buf;
 173         nand->read_buf   = ndfc_read_buf;
 174         nand->verify_buf = ndfc_verify_buf;
 175 #else
 176         /*
 177          * Setup EBC (CS0 only right now)
 178          */
 179         mtdcr(ebccfga, xbcfg);
 180         mtdcr(ebccfgd, 0xb8400000);
 181
 182         mtebc(pb0cr, CFG_EBC_PB0CR);
 183         mtebc(pb0ap, CFG_EBC_PB0AP);
 184 #endif
 185
 186         /*
 187          * Select required NAND chip in NDFC
 188          */
 189         board_nand_select_device(nand, cs);
 190         out32(base + NDFC_BCFG0 + (cs << 2), 0x80002222);
 191 }
 192
 193 #endif