firmware/include/.svn/text-base/openpicc.h.svn-base

   1 #ifndef _OPENPICC_H
   2 #define _OPENPICC_H
   3
   4 /* OpenPICC Register definition
   5  * (C) 2006 by Harald Welte <hwelte@hmw-consulting.de>
   6  */
   7
   8 enum openpicc_register {
   9         OPICC_REG_MODE,                 /* operational mode */
  10         OPICC_REG_ISO14443A_FDT_0,      /* FDT (after 0) in carrier cycles */
  11         OPICC_REG_ISO14443A_FDT_1,      /* FDT (after 1) in carrier cycles */
  12         OPICC_REG_BITCLK_PHASE_CORR,    /* signed 8bit phase correction */
  13         OPICC_REG_SPEED_RX,
  14         OPICC_REG_SPEED_TX,
  15         OPICC_REG_UID_PUPI,             /* UID (14443A) / PUPI (14443B) */
  16 };
  17
  18 enum openpicc_reg_mode {
  19         OPICC_MODE_14443A,
  20         OPICC_MODE_14443B,
  21         OPICC_MODE_LOWLEVEL,            /* low-level bit-transceive mode TBD */
  22 };
  23
  24 enum openpicc_reg_speed {
  25         OPICC_SPEED_14443_106K,
  26         OPICC_SPEED_14443_212K,
  27         OPICC_SPEED_14443_424K,
  28         OPICC_SPEED_14443_848K,
  29 };
  30
  31 #endif /* _OPENPICC_H */