| blob | e7a2af3cb46e6ff81b19b32e058ca7f1320240e0 |
1 1 # 1 "lib/changebit.S"
2 1 /*
3 0
4 0
5 2 * linux/arch/arm/lib/changebit.S
6 3 *
7 4 * Copyright (C) 1995-1996 Russell King
8 5 *
9 6 * This program is free software; you can redistribute it and/or modify
10 7 * it under the terms of the GNU General Public License version 2 as
11 8 * published by the Free Software Foundation.
12 9 */
13 10 #include <asm/linkage.h>
14 1 #ifndef __ASM_LINKAGE_H
15 11 #include <asm/assembler.h>
16 1 /*
17 2 * linux/include/asm-arm/assembler.h
18 3 *
19 4 * Copyright (C) 1996-2000 Russell King
20 5 *
21 6 * This program is free software; you can redistribute it and/or modify
22 7 * it under the terms of the GNU General Public License version 2 as
23 8 * published by the Free Software Foundation.
24 9 *
25 10 * This file contains arm architecture specific defines
26 11 * for the different processors.
27 12 *
28 13 * Do not include any C declarations in this file - it is included by
29 14 * assembler source.
30 15 */
31 16 #ifndef __ASSEMBLY__
32 17 #error "Only include this from assembly code"
33 18 #endif
34 19
35 20 #include <asm/ptrace.h>
36 1 /*
37 21
38 22 #define pull lsl
39 23 #define push lsr
40 24 #define get_byte_0 lsr #24
41 25 #define get_byte_1 lsr #16
42 26 #define get_byte_2 lsr #8
43 27 #define get_byte_3 lsl #0
44 28 #define put_byte_0 lsl #24
45 29 #define put_byte_1 lsl #16
46 30 #define put_byte_2 lsl #8
47 31 #define put_byte_3 lsl #0
48 32
49 33 #define PLD(code...)
50 34
51 35 #define MODE_USR USR_MODE
52 36 #define MODE_FIQ FIQ_MODE
53 37 #define MODE_IRQ IRQ_MODE
54 38 #define MODE_SVC SVC_MODE
55 39
56 40 #define DEFAULT_FIQ MODE_FIQ
57 41
58 42 /*
59 43 * LOADREGS - ldm with PC in register list (eg, ldmfd sp!, {pc})
60 44 */
61 45 #ifdef __STDC__
62 46 #define LOADREGS(cond, base, reglist...)\
63 47 ldm##cond base,reglist
64 48 #else
65 49 #define LOADREGS(cond, base, reglist...)\
66 50 ldm/**/cond base,reglist
67 51 #endif
68 52
69 53 /*
70 54 * Build a return instruction for this processor type.
71 55 */
72 56 #define RETINSTR(instr, regs...)\
73 57 instr regs
74 58
75 59 /*
76 60 * Enable and disable interrupts
77 61 */
78 62 .macro disable_irq
79 63 msr cpsr_c, #PSR_I_BIT | SVC_MODE
80 64 .endm
81 65
82 66 .macro enable_irq
83 67 msr cpsr_c, #SVC_MODE
84 68 .endm
85 69
86 70 /*
87 71 * Save the current IRQ state and disable IRQs. Note that this macro
88 72 * assumes FIQs are enabled, and that the processor is in SVC mode.
89 73 */
90 74 .macro save_and_disable_irqs, oldcpsr
91 75 mrs \oldcpsr, cpsr
92 76 disable_irq
93 77 .endm
94 78
95 79 /*
96 80 * Restore interrupt state previously stored in a register. We don't
97 81 * guarantee that this will preserve the flags.
98 82 */
99 83 .macro restore_irqs, oldcpsr
100 84 msr cpsr_c, \oldcpsr
101 85 .endm
102 86
103 87 /*
104 88 * These two are used to save LR/restore PC over a user-based access.
105 89 * The old 26-bit architecture requires that we do. On 32-bit
106 90 * architecture, we can safely ignore this requirement.
107 91 */
108 92 .macro save_lr
109 93 .endm
110 94
111 95 .macro restore_pc
112 96 mov pc, lr
113 97 .endm
114 98 ...
115 12 #include "bitops.h"
116 1 .macro bitop, instr
117 2 and r2, r0, #7
118 3 mov r3, #1
119 4 mov r3, r3, lsl r2
120 5 save_and_disable_irqs ip
121 6 ldrb r2, [r1, r0, lsr #3]
122 7 \instr r2, r2, r3
123 8 strb r2, [r1, r0, lsr #3]
124 9 restore_irqs ip
125 10 mov pc, lr
126 11 .endm
127 12
128 13 /**
129 14 * testop - implement a test_and_xxx_bit operation.
130 15 * @instr: operational instruction
131 16 * @store: store instruction
132 17 *
133 18 * Note: we can trivially conditionalise the store instruction
134 19 * to avoid dirting the data cache.
135 20 */
136 21 .macro testop, instr, store
137 22 add r1, r1, r0, lsr #3
138 23 and r3, r0, #7
139 24 mov r0, #1
140 25 save_and_disable_irqs ip
141 26 ldrb r2, [r1]
142 27 tst r2, r0, lsl r3
143 28 \instr r2, r2, r0, lsl r3
144 29 \store r2, [r1]
145 30 restore_irqs ip
146 31 moveq r0, #0
147 32 mov pc, lr
148 33 .endm
149 34 ...
150 13 .text
151 14
152 15 /* Purpose : Function to change a bit
153 16 * Prototype: int change_bit(int bit, void *addr)
154 17 */
155 18 ENTRY(_change_bit_be)
156 19 0000 180020E2 eor r0, r0, #0x18 @ big endian byte ordering
157 20 ENTRY(_change_bit_le)
158 21 0004 072000E2 bitop eor
159 21 0130A0E3
160 21 1332A0E1
161 21 00C00FE1
162 21 93F021E3
163 DEFINED SYMBOLS
164 lib/changebit.S:18 .text:0000000000000000 _change_bit_be
165 lib/changebit.S:19 .text:0000000000000000 $a
166 lib/changebit.S:20 .text:0000000000000004 _change_bit_le
168 NO UNDEFINED SYMBOLS