firmware/src/os/.svn/text-base/tc_cdiv.c.svn-base

   1 /* OpenPC TC (Timer / Clock) support code
   2  * (C) 2006 by Harald Welte <hwelte@hmw-consulting.de>
   3  *
   4  *  This program is free software; you can redistribute it and/or modify
   5  *  it under the terms of the GNU General Public License as published by
   6  *  the Free Software Foundation; either version 2 of the License, or
   7  *  (at your option) any later version.
   8  *
   9  *  This program is distributed in the hope that it will be useful,
  10  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  *  GNU General Public License for more details.
  13  *
  14  *  You should have received a copy of the GNU General Public License
  15  *  along with this program; if not, write to the Free Software
  16  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  17  *
  18  * This idea of this code is to feed the 13.56MHz carrier clock of RC632
  19  * into TCLK1, which is routed to XC1.  Then configure TC0 to divide this
  20  * clock by a configurable divider.
  21  *
  22  */
  23
  24 #include <lib_AT91SAM7.h>
  25 #include <AT91SAM7.h>
  26 #include <os/dbgu.h>
  27
  28 #include "../openpcd.h"
  29 #include <os/tc_cdiv.h>
  30
  31 static AT91PS_TCB tcb = AT91C_BASE_TCB;
  32
  33 /* set carrier divider to a specific */
  34 void tc_cdiv_set_divider(u_int16_t div)
  35 {
  36         tcb->TCB_TC0.TC_RC = div;
  37
  38         /* set to 50% duty cycle */
  39         tcb->TCB_TC0.TC_RA = 1;
  40         tcb->TCB_TC0.TC_RB = 1 + (div >> 1);
  41 }
  42
  43 void tc_cdiv_phase_add(int16_t inc)
  44 {
  45         tcb->TCB_TC0.TC_RA = (tcb->TCB_TC0.TC_RA + inc) % tcb->TCB_TC0.TC_RC;
  46         tcb->TCB_TC0.TC_RB = (tcb->TCB_TC0.TC_RB + inc) % tcb->TCB_TC0.TC_RC;
  47
  48         /* FIXME: can this be done more elegantly? */
  49         if (tcb->TCB_TC0.TC_RA == 0) {
  50                 tcb->TCB_TC0.TC_RA += 1;
  51                 tcb->TCB_TC0.TC_RB += 1;
  52         }
  53 }
  54
  55 void tc_cdiv_init(void)
  56 {
  57         /* Cfg PA28(TCLK1), PA0(TIOA0), PA1(TIOB0), PA20(TCLK2) as Periph B */
  58         AT91F_PIO_CfgPeriph(AT91C_BASE_PIOA, 0,
  59                             OPENPCD_PIO_CARRIER_IN |
  60                             OPENPCD_PIO_CARRIER_DIV_OUT |
  61                             OPENPCD_PIO_CDIV_HELP_OUT |
  62                             OPENPCD_PIO_CDIV_HELP_IN);
  63
  64         AT91F_PMC_EnablePeriphClock(AT91C_BASE_PMC,
  65                                     ((unsigned int) 1 << AT91C_ID_TC0));
  66
  67         /* Enable Clock for TC0 */
  68         tcb->TCB_TC0.TC_CCR = AT91C_TC_CLKEN;
  69
  70         /* Connect TCLK1 to XC1, TCLK2 to XC2 */
  71         tcb->TCB_BMR &= ~(AT91C_TCB_TC1XC1S | AT91C_TCB_TC2XC2S);
  72         tcb->TCB_BMR |=  (AT91C_TCB_TC1XC1S_TCLK1 | AT91C_TCB_TC2XC2S_TCLK2);
  73
  74         /* Clock XC1, Wave mode, Reset on RC comp
  75          * TIOA0 on RA comp = set, * TIOA0 on RC comp = clear,
  76          * TIOB0 on EEVT = set, TIOB0 on RB comp = clear,
  77          * EEVT = XC2 (TIOA0) */
  78         tcb->TCB_TC0.TC_CMR = AT91C_TC_CLKS_XC1 | AT91C_TC_WAVE |
  79                               AT91C_TC_WAVESEL_UP_AUTO |
  80                               AT91C_TC_ACPA_SET | AT91C_TC_ACPC_CLEAR |
  81                               AT91C_TC_BEEVT_SET | AT91C_TC_BCPB_CLEAR |
  82                               AT91C_TC_EEVT_XC2 | AT91C_TC_ETRGEDG_RISING |
  83                               AT91C_TC_BSWTRG_CLEAR | AT91C_TC_ASWTRG_CLEAR;
  84
  85         tc_cdiv_set_divider(128);
  86
  87         /* Reset to start timers */
  88         tcb->TCB_BCR = 1;
  89 }
  90
  91 void tc_cdiv_print(void)
  92 {
  93         DEBUGP("TCB_BMR=0x%08x ", tcb->TCB_BMR);
  94         DEBUGP("TC0_CV=0x%08x ", tcb->TCB_TC0.TC_CV);
  95         DEBUGP("TC0_CMR=0x%08x ", tcb->TCB_TC0.TC_CMR);
  96         DEBUGPCR("TC0_SR=0x%08x", tcb->TCB_TC0.TC_SR);
  97
  98         DEBUGPCR("TC0_RA=0x%04x, TC0_RB=0x%04x, TC0_RC=0x%04x",
  99                  tcb->TCB_TC0.TC_RA, tcb->TCB_TC0.TC_RB, tcb->TCB_TC0.TC_RC);
 100 }
 101
 102 void tc_cdiv_fini(void)
 103 {
 104         tcb->TCB_TC0.TC_CCR = AT91C_TC_CLKDIS;
 105         AT91F_PMC_DisablePeriphClock(AT91C_BASE_PMC,
 106                                      ((unsigned int) 1 << AT91C_ID_TC0));
 107 }