firmware/include/.svn/text-base/lib_AT91SAM7.h.svn-base

   1 //* ----------------------------------------------------------------------------
   2 //*         ATMEL Microcontroller Software Support  -  ROUSSET  -
   3 //* ----------------------------------------------------------------------------
   4 //* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
   5 //* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
   6 //* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
   7 //* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
   8 //* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
   9 //* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
  10 //* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  11 //* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  12 //* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
  13 //* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  14 //* ----------------------------------------------------------------------------
  15 //* File Name           : lib_AT91SAM7S64.h
  16 //* Object              : AT91SAM7S64 inlined functions
  17 //* Generated           : AT91 SW Application Group  08/30/2005 (15:52:59)
  18 //*
  19 //* CVS Reference       : /lib_dbgu.h/1.1/Thu Aug 25 12:56:22 2005//
  20 //* CVS Reference       : /lib_pmc_SAM7S.h/1.4/Tue Aug 30 13:00:43 2005//
  21 //* CVS Reference       : /lib_VREG_6085B.h/1.1/Tue Feb  1 16:20:47 2005//
  22 //* CVS Reference       : /lib_rstc_6098A.h/1.1/Wed Oct  6 10:39:20 2004//
  23 //* CVS Reference       : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003//
  24 //* CVS Reference       : /lib_wdtc_6080A.h/1.1/Wed Oct  6 10:38:30 2004//
  25 //* CVS Reference       : /lib_usart.h/1.5/Thu Nov 21 16:01:54 2002//
  26 //* CVS Reference       : /lib_spi2.h/1.2/Tue Aug 23 15:37:28 2005//
  27 //* CVS Reference       : /lib_pitc_6079A.h/1.2/Tue Nov  9 14:43:56 2004//
  28 //* CVS Reference       : /lib_aic_6075b.h/1.2/Thu Jul  7 07:48:22 2005//
  29 //* CVS Reference       : /lib_twi.h/1.3/Mon Jul 19 14:27:58 2004//
  30 //* CVS Reference       : /lib_adc.h/1.6/Fri Oct 17 09:12:38 2003//
  31 //* CVS Reference       : /lib_rttc_6081A.h/1.1/Wed Oct  6 10:39:38 2004//
  32 //* CVS Reference       : /lib_udp.h/1.5/Tue Aug 30 12:13:47 2005//
  33 //* CVS Reference       : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003//
  34 //* CVS Reference       : /lib_MC_SAM7S.h/1.1/Thu Mar 25 15:19:14 2004//
  35 //* CVS Reference       : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003//
  36 //* CVS Reference       : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004//
  37 //* CVS Reference       : /lib_pdc.h/1.2/Tue Jul  2 13:29:40 2002//
  38 //* ----------------------------------------------------------------------------
  39
  40 #ifndef lib_AT91SAM7S64_H
  41 #define lib_AT91SAM7S64_H
  42
  43 #include <AT91SAM7.h>
  44
  45 /* *****************************************************************************
  46                 SOFTWARE API FOR AIC
  47    ***************************************************************************** */
  48 #define AT91C_AIC_BRANCH_OPCODE ((void (*) ()) 0xE51FFF20) // ldr, pc, [pc, #-&F20]
  49
  50 //*----------------------------------------------------------------------------
  51 //* \fn    AT91F_AIC_ConfigureIt
  52 //* \brief Interrupt Handler Initialization
  53 //*----------------------------------------------------------------------------
  54 extern unsigned int AT91F_AIC_ConfigureIt (
  55         AT91PS_AIC pAic,  // \arg pointer to the AIC registers
  56         unsigned int irq_id,     // \arg interrupt number to initialize
  57         unsigned int priority,   // \arg priority to give to the interrupt
  58         unsigned int src_type,   // \arg activation and sense of activation
  59         void (*newHandler) () ); // \arg address of the interrupt handler
  60
  61 //*----------------------------------------------------------------------------
  62 //* \fn    AT91F_AIC_EnableIt
  63 //* \brief Enable corresponding IT number
  64 //*----------------------------------------------------------------------------
  65 static inline void AT91F_AIC_EnableIt (
  66         AT91PS_AIC pAic,      // \arg pointer to the AIC registers
  67         unsigned int irq_id ) // \arg interrupt number to initialize
  68 {
  69     //* Enable the interrupt on the interrupt controller
  70     pAic->AIC_IECR = 0x1 << irq_id ;
  71 }
  72
  73 //*----------------------------------------------------------------------------
  74 //* \fn    AT91F_AIC_DisableIt
  75 //* \brief Disable corresponding IT number
  76 //*----------------------------------------------------------------------------
  77 static inline void AT91F_AIC_DisableIt (
  78         AT91PS_AIC pAic,      // \arg pointer to the AIC registers
  79         unsigned int irq_id ) // \arg interrupt number to initialize
  80 {
  81     unsigned int mask = 0x1 << irq_id;
  82     //* Disable the interrupt on the interrupt controller
  83     pAic->AIC_IDCR = mask ;
  84     //* Clear the interrupt on the Interrupt Controller ( if one is pending )
  85     pAic->AIC_ICCR = mask ;
  86 }
  87
  88 //*----------------------------------------------------------------------------
  89 //* \fn    AT91F_AIC_ClearIt
  90 //* \brief Clear corresponding IT number
  91 //*----------------------------------------------------------------------------
  92 static inline void AT91F_AIC_ClearIt (
  93         AT91PS_AIC pAic,     // \arg pointer to the AIC registers
  94         unsigned int irq_id) // \arg interrupt number to initialize
  95 {
  96     //* Clear the interrupt on the Interrupt Controller ( if one is pending )
  97     pAic->AIC_ICCR = (0x1 << irq_id);
  98 }
  99
 100 //*----------------------------------------------------------------------------
 101 //* \fn    AT91F_AIC_AcknowledgeIt
 102 //* \brief Acknowledge corresponding IT number
 103 //*----------------------------------------------------------------------------
 104 static inline void AT91F_AIC_AcknowledgeIt (
 105         AT91PS_AIC pAic)     // \arg pointer to the AIC registers
 106 {
 107     pAic->AIC_EOICR = pAic->AIC_EOICR;
 108 }
 109
 110 //*----------------------------------------------------------------------------
 111 //* \fn    AT91F_AIC_SetExceptionVector
 112 //* \brief Configure vector handler
 113 //*----------------------------------------------------------------------------
 114 extern unsigned int  AT91F_AIC_SetExceptionVector (
 115         unsigned int *pVector, // \arg pointer to the AIC registers
 116         void (*Handler) () );   // \arg Interrupt Handler
 117
 118 //*----------------------------------------------------------------------------
 119 //* \fn    AT91F_AIC_Trig
 120 //* \brief Trig an IT
 121 //*----------------------------------------------------------------------------
 122 static inline void  AT91F_AIC_Trig (
 123         AT91PS_AIC pAic,     // \arg pointer to the AIC registers
 124         unsigned int irq_id) // \arg interrupt number
 125 {
 126         pAic->AIC_ISCR = (0x1 << irq_id) ;
 127 }
 128
 129 //*----------------------------------------------------------------------------
 130 //* \fn    AT91F_AIC_IsActive
 131 //* \brief Test if an IT is active
 132 //*----------------------------------------------------------------------------
 133 static inline unsigned int  AT91F_AIC_IsActive (
 134         AT91PS_AIC pAic,     // \arg pointer to the AIC registers
 135         unsigned int irq_id) // \arg Interrupt Number
 136 {
 137         return (pAic->AIC_ISR & (0x1 << irq_id));
 138 }
 139
 140 //*----------------------------------------------------------------------------
 141 //* \fn    AT91F_AIC_IsPending
 142 //* \brief Test if an IT is pending
 143 //*----------------------------------------------------------------------------
 144 static inline unsigned int  AT91F_AIC_IsPending (
 145         AT91PS_AIC pAic,     // \arg pointer to the AIC registers
 146         unsigned int irq_id) // \arg Interrupt Number
 147 {
 148         return (pAic->AIC_IPR & (0x1 << irq_id));
 149 }
 150
 151 //*----------------------------------------------------------------------------
 152 //* \fn    AT91F_AIC_Open
 153 //* \brief Set exception vectors and AIC registers to default values
 154 //*----------------------------------------------------------------------------
 155 extern void AT91F_AIC_Open(
 156         AT91PS_AIC pAic,        // \arg pointer to the AIC registers
 157         void (*IrqHandler) (),  // \arg Default IRQ vector exception
 158         void (*FiqHandler) (),  // \arg Default FIQ vector exception
 159         void (*DefaultHandler)  (), // \arg Default Handler set in ISR
 160         void (*SpuriousHandler) (), // \arg Default Spurious Handler
 161         unsigned int protectMode);   // \arg Debug Control Register
 162
 163 /* *****************************************************************************
 164                 SOFTWARE API FOR PDC
 165    ***************************************************************************** */
 166 //*----------------------------------------------------------------------------
 167 //* \fn    AT91F_PDC_SetNextRx
 168 //* \brief Set the next receive transfer descriptor
 169 //*----------------------------------------------------------------------------
 170 static inline void AT91F_PDC_SetNextRx (
 171         AT91PS_PDC pPDC,     // \arg pointer to a PDC controller
 172         unsigned char *address,// \arg address to the next bloc to be received
 173         unsigned int bytes)  // \arg number of bytes to be received
 174 {
 175         pPDC->PDC_RNPR = (unsigned int) address;
 176         pPDC->PDC_RNCR = bytes;
 177 }
 178
 179 //*----------------------------------------------------------------------------
 180 //* \fn    AT91F_PDC_SetNextTx
 181 //* \brief Set the next transmit transfer descriptor
 182 //*----------------------------------------------------------------------------
 183 static inline void AT91F_PDC_SetNextTx (
 184         AT91PS_PDC pPDC,       // \arg pointer to a PDC controller
 185         const unsigned char *address,// \arg address to the next bloc to be transmitted
 186         unsigned int bytes)    // \arg number of bytes to be transmitted
 187 {
 188         pPDC->PDC_TNPR = (unsigned int) address;
 189         pPDC->PDC_TNCR = bytes;
 190 }
 191
 192 //*----------------------------------------------------------------------------
 193 //* \fn    AT91F_PDC_SetRx
 194 //* \brief Set the receive transfer descriptor
 195 //*----------------------------------------------------------------------------
 196 static inline void AT91F_PDC_SetRx (
 197         AT91PS_PDC pPDC,       // \arg pointer to a PDC controller
 198         unsigned char *address,// \arg address to the next bloc to be received
 199         unsigned int bytes)    // \arg number of bytes to be received
 200 {
 201         pPDC->PDC_RPR = (unsigned int) address;
 202         pPDC->PDC_RCR = bytes;
 203 }
 204
 205 //*----------------------------------------------------------------------------
 206 //* \fn    AT91F_PDC_SetTx
 207 //* \brief Set the transmit transfer descriptor
 208 //*----------------------------------------------------------------------------
 209 static inline void AT91F_PDC_SetTx (
 210         AT91PS_PDC pPDC,       // \arg pointer to a PDC controller
 211         const unsigned char *address,// \arg address to the next bloc to be transmitted
 212         unsigned int bytes)    // \arg number of bytes to be transmitted
 213 {
 214         pPDC->PDC_TPR = (unsigned int) address;
 215         pPDC->PDC_TCR = bytes;
 216 }
 217
 218 //*----------------------------------------------------------------------------
 219 //* \fn    AT91F_PDC_EnableTx
 220 //* \brief Enable transmit
 221 //*----------------------------------------------------------------------------
 222 static inline void AT91F_PDC_EnableTx (
 223         AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
 224 {
 225         pPDC->PDC_PTCR = AT91C_PDC_TXTEN;
 226 }
 227
 228 //*----------------------------------------------------------------------------
 229 //* \fn    AT91F_PDC_EnableRx
 230 //* \brief Enable receive
 231 //*----------------------------------------------------------------------------
 232 static inline void AT91F_PDC_EnableRx (
 233         AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
 234 {
 235         pPDC->PDC_PTCR = AT91C_PDC_RXTEN;
 236 }
 237
 238 //*----------------------------------------------------------------------------
 239 //* \fn    AT91F_PDC_DisableTx
 240 //* \brief Disable transmit
 241 //*----------------------------------------------------------------------------
 242 static inline void AT91F_PDC_DisableTx (
 243         AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
 244 {
 245         pPDC->PDC_PTCR = AT91C_PDC_TXTDIS;
 246 }
 247
 248 //*----------------------------------------------------------------------------
 249 //* \fn    AT91F_PDC_DisableRx
 250 //* \brief Disable receive
 251 //*----------------------------------------------------------------------------
 252 static inline void AT91F_PDC_DisableRx (
 253         AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
 254 {
 255         pPDC->PDC_PTCR = AT91C_PDC_RXTDIS;
 256 }
 257
 258 //*----------------------------------------------------------------------------
 259 //* \fn    AT91F_PDC_IsTxEmpty
 260 //* \brief Test if the current transfer descriptor has been sent
 261 //*----------------------------------------------------------------------------
 262 static inline int AT91F_PDC_IsTxEmpty ( // \return return 1 if transfer is complete
 263         AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
 264 {
 265         return !(pPDC->PDC_TCR);
 266 }
 267
 268 //*----------------------------------------------------------------------------
 269 //* \fn    AT91F_PDC_IsNextTxEmpty
 270 //* \brief Test if the next transfer descriptor has been moved to the current td
 271 //*----------------------------------------------------------------------------
 272 static inline int AT91F_PDC_IsNextTxEmpty ( // \return return 1 if transfer is complete
 273         AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
 274 {
 275         return !(pPDC->PDC_TNCR);
 276 }
 277
 278 //*----------------------------------------------------------------------------
 279 //* \fn    AT91F_PDC_IsRxEmpty
 280 //* \brief Test if the current transfer descriptor has been filled
 281 //*----------------------------------------------------------------------------
 282 static inline int AT91F_PDC_IsRxEmpty ( // \return return 1 if transfer is complete
 283         AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
 284 {
 285         return !(pPDC->PDC_RCR);
 286 }
 287
 288 //*----------------------------------------------------------------------------
 289 //* \fn    AT91F_PDC_IsNextRxEmpty
 290 //* \brief Test if the next transfer descriptor has been moved to the current td
 291 //*----------------------------------------------------------------------------
 292 static inline int AT91F_PDC_IsNextRxEmpty ( // \return return 1 if transfer is complete
 293         AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
 294 {
 295         return !(pPDC->PDC_RNCR);
 296 }
 297
 298 //*----------------------------------------------------------------------------
 299 //* \fn    AT91F_PDC_Open
 300 //* \brief Open PDC: disable TX and RX reset transfer descriptors, re-enable RX and TX
 301 //*----------------------------------------------------------------------------
 302 extern void AT91F_PDC_Open(AT91PS_PDC pPDC);      // \arg pointer to a PDC controller
 303
 304 //*----------------------------------------------------------------------------
 305 //* \fn    AT91F_PDC_Close
 306 //* \brief Close PDC: disable TX and RX reset transfer descriptors
 307 //*----------------------------------------------------------------------------
 308 extern void AT91F_PDC_Close(AT91PS_PDC pPDC);       // \arg pointer to a PDC controller
 309
 310 //*----------------------------------------------------------------------------
 311 //* \fn    AT91F_PDC_SendFrame
 312 //* \brief Close PDC: disable TX and RX reset transfer descriptors
 313 //*----------------------------------------------------------------------------
 314 extern unsigned int AT91F_PDC_SendFrame(
 315         AT91PS_PDC pPDC,
 316         const unsigned char *pBuffer,
 317         unsigned int szBuffer,
 318         const unsigned char *pNextBuffer,
 319         unsigned int szNextBuffer);
 320
 321 //*----------------------------------------------------------------------------
 322 //* \fn    AT91F_PDC_ReceiveFrame
 323 //* \brief Close PDC: disable TX and RX reset transfer descriptors
 324 //*----------------------------------------------------------------------------
 325 extern unsigned int AT91F_PDC_ReceiveFrame (
 326         AT91PS_PDC pPDC,
 327         unsigned char *pBuffer,
 328         unsigned int szBuffer,
 329         unsigned char *pNextBuffer,
 330         unsigned int szNextBuffer);
 331
 332 /* *****************************************************************************
 333                 SOFTWARE API FOR DBGU
 334    ***************************************************************************** */
 335 //*----------------------------------------------------------------------------
 336 //* \fn    AT91F_DBGU_InterruptEnable
 337 //* \brief Enable DBGU Interrupt
 338 //*----------------------------------------------------------------------------
 339 static inline void AT91F_DBGU_InterruptEnable(
 340         AT91PS_DBGU pDbgu,   // \arg  pointer to a DBGU controller
 341         unsigned int flag) // \arg  dbgu interrupt to be enabled
 342 {
 343         pDbgu->DBGU_IER = flag;
 344 }
 345
 346 //*----------------------------------------------------------------------------
 347 //* \fn    AT91F_DBGU_InterruptDisable
 348 //* \brief Disable DBGU Interrupt
 349 //*----------------------------------------------------------------------------
 350 static inline void AT91F_DBGU_InterruptDisable(
 351         AT91PS_DBGU pDbgu,   // \arg  pointer to a DBGU controller
 352         unsigned int flag) // \arg  dbgu interrupt to be disabled
 353 {
 354         pDbgu->DBGU_IDR = flag;
 355 }
 356
 357 //*----------------------------------------------------------------------------
 358 //* \fn    AT91F_DBGU_GetInterruptMaskStatus
 359 //* \brief Return DBGU Interrupt Mask Status
 360 //*----------------------------------------------------------------------------
 361 static inline unsigned int AT91F_DBGU_GetInterruptMaskStatus( // \return DBGU Interrupt Mask Status
 362         AT91PS_DBGU pDbgu) // \arg  pointer to a DBGU controller
 363 {
 364         return pDbgu->DBGU_IMR;
 365 }
 366
 367 //*----------------------------------------------------------------------------
 368 //* \fn    AT91F_DBGU_IsInterruptMasked
 369 //* \brief Test if DBGU Interrupt is Masked
 370 //*----------------------------------------------------------------------------
 371 static inline int AT91F_DBGU_IsInterruptMasked(
 372         AT91PS_DBGU pDbgu,   // \arg  pointer to a DBGU controller
 373         unsigned int flag) // \arg  flag to be tested
 374 {
 375         return (AT91F_DBGU_GetInterruptMaskStatus(pDbgu) & flag);
 376 }
 377
 378 /* *****************************************************************************
 379                 SOFTWARE API FOR PIO
 380    ***************************************************************************** */
 381 //*----------------------------------------------------------------------------
 382 //* \fn    AT91F_PIO_CfgPeriph
 383 //* \brief Enable pins to be drived by peripheral
 384 //*----------------------------------------------------------------------------
 385 static inline void AT91F_PIO_CfgPeriph(
 386         AT91PS_PIO pPio,             // \arg pointer to a PIO controller
 387         unsigned int periphAEnable,  // \arg PERIPH A to enable
 388         unsigned int periphBEnable)  // \arg PERIPH B to enable
 389
 390 {
 391         pPio->PIO_ASR = periphAEnable;
 392         pPio->PIO_BSR = periphBEnable;
 393         pPio->PIO_PDR = (periphAEnable | periphBEnable); // Set in Periph mode
 394 }
 395
 396 //*----------------------------------------------------------------------------
 397 //* \fn    AT91F_PIO_CfgOutput
 398 //* \brief Enable PIO in output mode
 399 //*----------------------------------------------------------------------------
 400 static inline void AT91F_PIO_CfgOutput(
 401         AT91PS_PIO pPio,             // \arg pointer to a PIO controller
 402         unsigned int pioEnable)      // \arg PIO to be enabled
 403 {
 404         pPio->PIO_PER = pioEnable; // Set in PIO mode
 405         pPio->PIO_OER = pioEnable; // Configure in Output
 406 }
 407
 408 //*----------------------------------------------------------------------------
 409 //* \fn    AT91F_PIO_CfgInput
 410 //* \brief Enable PIO in input mode
 411 //*----------------------------------------------------------------------------
 412 static inline void AT91F_PIO_CfgInput(
 413         AT91PS_PIO pPio,             // \arg pointer to a PIO controller
 414         unsigned int inputEnable)      // \arg PIO to be enabled
 415 {
 416         // Disable output
 417         pPio->PIO_ODR  = inputEnable;
 418         pPio->PIO_PER  = inputEnable;
 419 }
 420
 421 //*----------------------------------------------------------------------------
 422 //* \fn    AT91F_PIO_CfgOpendrain
 423 //* \brief Configure PIO in open drain
 424 //*----------------------------------------------------------------------------
 425 static inline void AT91F_PIO_CfgOpendrain(
 426         AT91PS_PIO pPio,             // \arg pointer to a PIO controller
 427         unsigned int multiDrvEnable) // \arg pio to be configured in open drain
 428 {
 429         // Configure the multi-drive option
 430         pPio->PIO_MDDR = ~multiDrvEnable;
 431         pPio->PIO_MDER = multiDrvEnable;
 432 }
 433
 434 //*----------------------------------------------------------------------------
 435 //* \fn    AT91F_PIO_CfgPullup
 436 //* \brief Enable pullup on PIO
 437 //*----------------------------------------------------------------------------
 438 static inline void AT91F_PIO_CfgPullup(
 439         AT91PS_PIO pPio,             // \arg pointer to a PIO controller
 440         unsigned int pullupEnable)   // \arg enable pullup on PIO
 441 {
 442                 // Connect or not Pullup
 443         pPio->PIO_PPUDR = ~pullupEnable;
 444         pPio->PIO_PPUER = pullupEnable;
 445 }
 446
 447 //*----------------------------------------------------------------------------
 448 //* \fn    AT91F_PIO_CfgDirectDrive
 449 //* \brief Enable direct drive on PIO
 450 //*----------------------------------------------------------------------------
 451 static inline void AT91F_PIO_CfgDirectDrive(
 452         AT91PS_PIO pPio,             // \arg pointer to a PIO controller
 453         unsigned int directDrive)    // \arg PIO to be configured with direct drive
 454
 455 {
 456         // Configure the Direct Drive
 457         pPio->PIO_OWDR  = ~directDrive;
 458         pPio->PIO_OWER  = directDrive;
 459 }
 460
 461 //*----------------------------------------------------------------------------
 462 //* \fn    AT91F_PIO_CfgInputFilter
 463 //* \brief Enable input filter on input PIO
 464 //*----------------------------------------------------------------------------
 465 static inline void AT91F_PIO_CfgInputFilter(
 466         AT91PS_PIO pPio,             // \arg pointer to a PIO controller
 467         unsigned int inputFilter)    // \arg PIO to be configured with input filter
 468
 469 {
 470         // Configure the Direct Drive
 471         pPio->PIO_IFDR  = ~inputFilter;
 472         pPio->PIO_IFER  = inputFilter;
 473 }
 474
 475 //*----------------------------------------------------------------------------
 476 //* \fn    AT91F_PIO_GetInput
 477 //* \brief Return PIO input value
 478 //*----------------------------------------------------------------------------
 479 static inline unsigned int AT91F_PIO_GetInput( // \return PIO input
 480         AT91PS_PIO pPio) // \arg  pointer to a PIO controller
 481 {
 482         return pPio->PIO_PDSR;
 483 }
 484
 485 //*----------------------------------------------------------------------------
 486 //* \fn    AT91F_PIO_IsInputSet
 487 //* \brief Test if PIO is input flag is active
 488 //*----------------------------------------------------------------------------
 489 static inline int AT91F_PIO_IsInputSet(
 490         AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
 491         unsigned int flag) // \arg  flag to be tested
 492 {
 493         return (AT91F_PIO_GetInput(pPio) & flag);
 494 }
 495
 496
 497 //*----------------------------------------------------------------------------
 498 //* \fn    AT91F_PIO_SetOutput
 499 //* \brief Set to 1 output PIO
 500 //*----------------------------------------------------------------------------
 501 static inline void AT91F_PIO_SetOutput(
 502         const AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
 503         const unsigned int flag) // \arg  output to be set
 504 {
 505         pPio->PIO_SODR = flag;
 506 }
 507
 508 //*----------------------------------------------------------------------------
 509 //* \fn    AT91F_PIO_ClearOutput
 510 //* \brief Set to 0 output PIO
 511 //*----------------------------------------------------------------------------
 512 static inline void AT91F_PIO_ClearOutput(
 513         AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
 514         unsigned int flag) // \arg  output to be cleared
 515 {
 516         pPio->PIO_CODR = flag;
 517 }
 518
 519 //*----------------------------------------------------------------------------
 520 //* \fn    AT91F_PIO_ForceOutput
 521 //* \brief Force output when Direct drive option is enabled
 522 //*----------------------------------------------------------------------------
 523 static inline void AT91F_PIO_ForceOutput(
 524         AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
 525         unsigned int flag) // \arg  output to be forced
 526 {
 527         pPio->PIO_ODSR = flag;
 528 }
 529
 530 //*----------------------------------------------------------------------------
 531 //* \fn    AT91F_PIO_Enable
 532 //* \brief Enable PIO
 533 //*----------------------------------------------------------------------------
 534 static inline void AT91F_PIO_Enable(
 535         AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
 536         unsigned int flag) // \arg  pio to be enabled
 537 {
 538         pPio->PIO_PER = flag;
 539 }
 540
 541 //*----------------------------------------------------------------------------
 542 //* \fn    AT91F_PIO_Disable
 543 //* \brief Disable PIO
 544 //*----------------------------------------------------------------------------
 545 static inline void AT91F_PIO_Disable(
 546         AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
 547         unsigned int flag) // \arg  pio to be disabled
 548 {
 549         pPio->PIO_PDR = flag;
 550 }
 551
 552 //*----------------------------------------------------------------------------
 553 //* \fn    AT91F_PIO_GetStatus
 554 //* \brief Return PIO Status
 555 //*----------------------------------------------------------------------------
 556 static inline unsigned int AT91F_PIO_GetStatus( // \return PIO Status
 557         AT91PS_PIO pPio) // \arg  pointer to a PIO controller
 558 {
 559         return pPio->PIO_PSR;
 560 }
 561
 562 //*----------------------------------------------------------------------------
 563 //* \fn    AT91F_PIO_IsSet
 564 //* \brief Test if PIO is Set
 565 //*----------------------------------------------------------------------------
 566 static inline int AT91F_PIO_IsSet(
 567         AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
 568         unsigned int flag) // \arg  flag to be tested
 569 {
 570         return (AT91F_PIO_GetStatus(pPio) & flag);
 571 }
 572
 573 //*----------------------------------------------------------------------------
 574 //* \fn    AT91F_PIO_OutputEnable
 575 //* \brief Output Enable PIO
 576 //*----------------------------------------------------------------------------
 577 static inline void AT91F_PIO_OutputEnable(
 578         AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
 579         unsigned int flag) // \arg  pio output to be enabled
 580 {
 581         pPio->PIO_OER = flag;
 582 }
 583
 584 //*----------------------------------------------------------------------------
 585 //* \fn    AT91F_PIO_OutputDisable
 586 //* \brief Output Enable PIO
 587 //*----------------------------------------------------------------------------
 588 static inline void AT91F_PIO_OutputDisable(
 589         AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
 590         unsigned int flag) // \arg  pio output to be disabled
 591 {
 592         pPio->PIO_ODR = flag;
 593 }
 594
 595 //*----------------------------------------------------------------------------
 596 //* \fn    AT91F_PIO_GetOutputStatus
 597 //* \brief Return PIO Output Status
 598 //*----------------------------------------------------------------------------
 599 static inline unsigned int AT91F_PIO_GetOutputStatus( // \return PIO Output Status
 600         AT91PS_PIO pPio) // \arg  pointer to a PIO controller
 601 {
 602         return pPio->PIO_OSR;
 603 }
 604
 605 //*----------------------------------------------------------------------------
 606 //* \fn    AT91F_PIO_IsOuputSet
 607 //* \brief Test if PIO Output is Set
 608 //*----------------------------------------------------------------------------
 609 static inline int AT91F_PIO_IsOutputSet(
 610         AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
 611         unsigned int flag) // \arg  flag to be tested
 612 {
 613         return (AT91F_PIO_GetOutputStatus(pPio) & flag);
 614 }
 615
 616 //*----------------------------------------------------------------------------
 617 //* \fn    AT91F_PIO_InputFilterEnable
 618 //* \brief Input Filter Enable PIO
 619 //*----------------------------------------------------------------------------
 620 static inline void AT91F_PIO_InputFilterEnable(
 621         AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
 622         unsigned int flag) // \arg  pio input filter to be enabled
 623 {
 624         pPio->PIO_IFER = flag;
 625 }
 626
 627 //*----------------------------------------------------------------------------
 628 //* \fn    AT91F_PIO_InputFilterDisable
 629 //* \brief Input Filter Disable PIO
 630 //*----------------------------------------------------------------------------
 631 static inline void AT91F_PIO_InputFilterDisable(
 632         AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
 633         unsigned int flag) // \arg  pio input filter to be disabled
 634 {
 635         pPio->PIO_IFDR = flag;
 636 }
 637
 638 //*----------------------------------------------------------------------------
 639 //* \fn    AT91F_PIO_GetInputFilterStatus
 640 //* \brief Return PIO Input Filter Status
 641 //*----------------------------------------------------------------------------
 642 static inline unsigned int AT91F_PIO_GetInputFilterStatus( // \return PIO Input Filter Status
 643         AT91PS_PIO pPio) // \arg  pointer to a PIO controller
 644 {
 645         return pPio->PIO_IFSR;
 646 }
 647
 648 //*----------------------------------------------------------------------------
 649 //* \fn    AT91F_PIO_IsInputFilterSet
 650 //* \brief Test if PIO Input filter is Set
 651 //*----------------------------------------------------------------------------
 652 static inline int AT91F_PIO_IsInputFilterSet(
 653         AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
 654         unsigned int flag) // \arg  flag to be tested
 655 {
 656         return (AT91F_PIO_GetInputFilterStatus(pPio) & flag);
 657 }
 658
 659 //*----------------------------------------------------------------------------
 660 //* \fn    AT91F_PIO_GetOutputDataStatus
 661 //* \brief Return PIO Output Data Status
 662 //*----------------------------------------------------------------------------
 663 static inline unsigned int AT91F_PIO_GetOutputDataStatus( // \return PIO Output Data Status
 664         AT91PS_PIO pPio) // \arg  pointer to a PIO controller
 665 {
 666         return pPio->PIO_ODSR;
 667 }
 668
 669 //*----------------------------------------------------------------------------
 670 //* \fn    AT91F_PIO_InterruptEnable
 671 //* \brief Enable PIO Interrupt
 672 //*----------------------------------------------------------------------------
 673 static inline void AT91F_PIO_InterruptEnable(
 674         AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
 675         unsigned int flag) // \arg  pio interrupt to be enabled
 676 {
 677         pPio->PIO_IER = flag;
 678 }
 679
 680 //*----------------------------------------------------------------------------
 681 //* \fn    AT91F_PIO_InterruptDisable
 682 //* \brief Disable PIO Interrupt
 683 //*----------------------------------------------------------------------------
 684 static inline void AT91F_PIO_InterruptDisable(
 685         AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
 686         unsigned int flag) // \arg  pio interrupt to be disabled
 687 {
 688         pPio->PIO_IDR = flag;
 689 }
 690
 691 //*----------------------------------------------------------------------------
 692 //* \fn    AT91F_PIO_GetInterruptMaskStatus
 693 //* \brief Return PIO Interrupt Mask Status
 694 //*----------------------------------------------------------------------------
 695 static inline unsigned int AT91F_PIO_GetInterruptMaskStatus( // \return PIO Interrupt Mask Status
 696         AT91PS_PIO pPio) // \arg  pointer to a PIO controller
 697 {
 698         return pPio->PIO_IMR;
 699 }
 700
 701 //*----------------------------------------------------------------------------
 702 //* \fn    AT91F_PIO_GetInterruptStatus
 703 //* \brief Return PIO Interrupt Status
 704 //*----------------------------------------------------------------------------
 705 static inline unsigned int AT91F_PIO_GetInterruptStatus( // \return PIO Interrupt Status
 706         AT91PS_PIO pPio) // \arg  pointer to a PIO controller
 707 {
 708         return pPio->PIO_ISR;
 709 }
 710
 711 //*----------------------------------------------------------------------------
 712 //* \fn    AT91F_PIO_IsInterruptMasked
 713 //* \brief Test if PIO Interrupt is Masked
 714 //*----------------------------------------------------------------------------
 715 static inline int AT91F_PIO_IsInterruptMasked(
 716         AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
 717         unsigned int flag) // \arg  flag to be tested
 718 {
 719         return (AT91F_PIO_GetInterruptMaskStatus(pPio) & flag);
 720 }
 721
 722 //*----------------------------------------------------------------------------
 723 //* \fn    AT91F_PIO_IsInterruptSet
 724 //* \brief Test if PIO Interrupt is Set
 725 //*----------------------------------------------------------------------------
 726 static inline int AT91F_PIO_IsInterruptSet(
 727         AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
 728         unsigned int flag) // \arg  flag to be tested
 729 {
 730         return (AT91F_PIO_GetInterruptStatus(pPio) & flag);
 731 }
 732
 733 //*----------------------------------------------------------------------------
 734 //* \fn    AT91F_PIO_MultiDriverEnable
 735 //* \brief Multi Driver Enable PIO
 736 //*----------------------------------------------------------------------------
 737 static inline void AT91F_PIO_MultiDriverEnable(
 738         AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
 739         unsigned int flag) // \arg  pio to be enabled
 740 {
 741         pPio->PIO_MDER = flag;
 742 }
 743
 744 //*----------------------------------------------------------------------------
 745 //* \fn    AT91F_PIO_MultiDriverDisable
 746 //* \brief Multi Driver Disable PIO
 747 //*----------------------------------------------------------------------------
 748 static inline void AT91F_PIO_MultiDriverDisable(
 749         AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
 750         unsigned int flag) // \arg  pio to be disabled
 751 {
 752         pPio->PIO_MDDR = flag;
 753 }
 754
 755 //*----------------------------------------------------------------------------
 756 //* \fn    AT91F_PIO_GetMultiDriverStatus
 757 //* \brief Return PIO Multi Driver Status
 758 //*----------------------------------------------------------------------------
 759 static inline unsigned int AT91F_PIO_GetMultiDriverStatus( // \return PIO Multi Driver Status
 760         AT91PS_PIO pPio) // \arg  pointer to a PIO controller
 761 {
 762         return pPio->PIO_MDSR;
 763 }
 764
 765 //*----------------------------------------------------------------------------
 766 //* \fn    AT91F_PIO_IsMultiDriverSet
 767 //* \brief Test if PIO MultiDriver is Set
 768 //*----------------------------------------------------------------------------
 769 static inline int AT91F_PIO_IsMultiDriverSet(
 770         AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
 771         unsigned int flag) // \arg  flag to be tested
 772 {
 773         return (AT91F_PIO_GetMultiDriverStatus(pPio) & flag);
 774 }
 775
 776 //*----------------------------------------------------------------------------
 777 //* \fn    AT91F_PIO_A_RegisterSelection
 778 //* \brief PIO A Register Selection
 779 //*----------------------------------------------------------------------------
 780 static inline void AT91F_PIO_A_RegisterSelection(
 781         AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
 782         unsigned int flag) // \arg  pio A register selection
 783 {
 784         pPio->PIO_ASR = flag;
 785 }
 786
 787 //*----------------------------------------------------------------------------
 788 //* \fn    AT91F_PIO_B_RegisterSelection
 789 //* \brief PIO B Register Selection
 790 //*----------------------------------------------------------------------------
 791 static inline void AT91F_PIO_B_RegisterSelection(
 792         AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
 793         unsigned int flag) // \arg  pio B register selection
 794 {
 795         pPio->PIO_BSR = flag;
 796 }
 797
 798 //*----------------------------------------------------------------------------
 799 //* \fn    AT91F_PIO_Get_AB_RegisterStatus
 800 //* \brief Return PIO Interrupt Status
 801 //*----------------------------------------------------------------------------
 802 static inline unsigned int AT91F_PIO_Get_AB_RegisterStatus( // \return PIO AB Register Status
 803         AT91PS_PIO pPio) // \arg  pointer to a PIO controller
 804 {
 805         return pPio->PIO_ABSR;
 806 }
 807
 808 //*----------------------------------------------------------------------------
 809 //* \fn    AT91F_PIO_IsAB_RegisterSet
 810 //* \brief Test if PIO AB Register is Set
 811 //*----------------------------------------------------------------------------
 812 static inline int AT91F_PIO_IsAB_RegisterSet(
 813         AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
 814         unsigned int flag) // \arg  flag to be tested
 815 {
 816         return (AT91F_PIO_Get_AB_RegisterStatus(pPio) & flag);
 817 }
 818
 819 //*----------------------------------------------------------------------------
 820 //* \fn    AT91F_PIO_OutputWriteEnable
 821 //* \brief Output Write Enable PIO
 822 //*----------------------------------------------------------------------------
 823 static inline void AT91F_PIO_OutputWriteEnable(
 824         AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
 825         unsigned int flag) // \arg  pio output write to be enabled
 826 {
 827         pPio->PIO_OWER = flag;
 828 }
 829
 830 //*----------------------------------------------------------------------------
 831 //* \fn    AT91F_PIO_OutputWriteDisable
 832 //* \brief Output Write Disable PIO
 833 //*----------------------------------------------------------------------------
 834 static inline void AT91F_PIO_OutputWriteDisable(
 835         AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
 836         unsigned int flag) // \arg  pio output write to be disabled
 837 {
 838         pPio->PIO_OWDR = flag;
 839 }
 840
 841 //*----------------------------------------------------------------------------
 842 //* \fn    AT91F_PIO_GetOutputWriteStatus
 843 //* \brief Return PIO Output Write Status
 844 //*----------------------------------------------------------------------------
 845 static inline unsigned int AT91F_PIO_GetOutputWriteStatus( // \return PIO Output Write Status
 846         AT91PS_PIO pPio) // \arg  pointer to a PIO controller
 847 {
 848         return pPio->PIO_OWSR;
 849 }
 850
 851 //*----------------------------------------------------------------------------
 852 //* \fn    AT91F_PIO_IsOutputWriteSet
 853 //* \brief Test if PIO OutputWrite is Set
 854 //*----------------------------------------------------------------------------
 855 static inline int AT91F_PIO_IsOutputWriteSet(
 856         AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
 857         unsigned int flag) // \arg  flag to be tested
 858 {
 859         return (AT91F_PIO_GetOutputWriteStatus(pPio) & flag);
 860 }
 861
 862 //*----------------------------------------------------------------------------
 863 //* \fn    AT91F_PIO_GetCfgPullup
 864 //* \brief Return PIO Configuration Pullup
 865 //*----------------------------------------------------------------------------
 866 static inline unsigned int AT91F_PIO_GetCfgPullup( // \return PIO Configuration Pullup
 867         AT91PS_PIO pPio) // \arg  pointer to a PIO controller
 868 {
 869         return pPio->PIO_PPUSR;
 870 }
 871
 872 //*----------------------------------------------------------------------------
 873 //* \fn    AT91F_PIO_IsOutputDataStatusSet
 874 //* \brief Test if PIO Output Data Status is Set
 875 //*----------------------------------------------------------------------------
 876 static inline int AT91F_PIO_IsOutputDataStatusSet(
 877         AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
 878         unsigned int flag) // \arg  flag to be tested
 879 {
 880         return (AT91F_PIO_GetOutputDataStatus(pPio) & flag);
 881 }
 882
 883 //*----------------------------------------------------------------------------
 884 //* \fn    AT91F_PIO_IsCfgPullupStatusSet
 885 //* \brief Test if PIO Configuration Pullup Status is Set
 886 //*----------------------------------------------------------------------------
 887 static inline int AT91F_PIO_IsCfgPullupStatusSet(
 888         AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
 889         unsigned int flag) // \arg  flag to be tested
 890 {
 891         return (~AT91F_PIO_GetCfgPullup(pPio) & flag);
 892 }
 893
 894 /* *****************************************************************************
 895                 SOFTWARE API FOR PMC
 896    ***************************************************************************** */
 897 //*----------------------------------------------------------------------------
 898 //* \fn    AT91F_PMC_CfgSysClkEnableReg
 899 //* \brief Configure the System Clock Enable Register of the PMC controller
 900 //*----------------------------------------------------------------------------
 901 static inline void AT91F_PMC_CfgSysClkEnableReg (
 902         AT91PS_PMC pPMC, // \arg pointer to PMC controller
 903         unsigned int mode)
 904 {
 905         //* Write to the SCER register
 906         pPMC->PMC_SCER = mode;
 907 }
 908
 909 //*----------------------------------------------------------------------------
 910 //* \fn    AT91F_PMC_CfgSysClkDisableReg
 911 //* \brief Configure the System Clock Disable Register of the PMC controller
 912 //*----------------------------------------------------------------------------
 913 static inline void AT91F_PMC_CfgSysClkDisableReg (
 914         AT91PS_PMC pPMC, // \arg pointer to PMC controller
 915         unsigned int mode)
 916 {
 917         //* Write to the SCDR register
 918         pPMC->PMC_SCDR = mode;
 919 }
 920
 921 //*----------------------------------------------------------------------------
 922 //* \fn    AT91F_PMC_GetSysClkStatusReg
 923 //* \brief Return the System Clock Status Register of the PMC controller
 924 //*----------------------------------------------------------------------------
 925 static inline unsigned int AT91F_PMC_GetSysClkStatusReg (
 926         AT91PS_PMC pPMC // pointer to a CAN controller
 927         )
 928 {
 929         return pPMC->PMC_SCSR;
 930 }
 931
 932 //*----------------------------------------------------------------------------
 933 //* \fn    AT91F_PMC_EnablePeriphClock
 934 //* \brief Enable peripheral clock
 935 //*----------------------------------------------------------------------------
 936 static inline void AT91F_PMC_EnablePeriphClock (
 937         AT91PS_PMC pPMC, // \arg pointer to PMC controller
 938         unsigned int periphIds)  // \arg IDs of peripherals to enable
 939 {
 940         pPMC->PMC_PCER = periphIds;
 941 }
 942
 943 //*----------------------------------------------------------------------------
 944 //* \fn    AT91F_PMC_DisablePeriphClock
 945 //* \brief Disable peripheral clock
 946 //*----------------------------------------------------------------------------
 947 static inline void AT91F_PMC_DisablePeriphClock (
 948         AT91PS_PMC pPMC, // \arg pointer to PMC controller
 949         unsigned int periphIds)  // \arg IDs of peripherals to enable
 950 {
 951         pPMC->PMC_PCDR = periphIds;
 952 }
 953
 954 //*----------------------------------------------------------------------------
 955 //* \fn    AT91F_PMC_GetPeriphClock
 956 //* \brief Get peripheral clock status
 957 //*----------------------------------------------------------------------------
 958 static inline unsigned int AT91F_PMC_GetPeriphClock (
 959         AT91PS_PMC pPMC) // \arg pointer to PMC controller
 960 {
 961         return pPMC->PMC_PCSR;
 962 }
 963
 964 //*----------------------------------------------------------------------------
 965 //* \fn    AT91F_CKGR_CfgMainOscillatorReg
 966 //* \brief Cfg the main oscillator
 967 //*----------------------------------------------------------------------------
 968 static inline void AT91F_CKGR_CfgMainOscillatorReg (
 969         AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
 970         unsigned int mode)
 971 {
 972         pCKGR->CKGR_MOR = mode;
 973 }
 974
 975 //*----------------------------------------------------------------------------
 976 //* \fn    AT91F_CKGR_GetMainOscillatorReg
 977 //* \brief Cfg the main oscillator
 978 //*----------------------------------------------------------------------------
 979 static inline unsigned int AT91F_CKGR_GetMainOscillatorReg (
 980         AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
 981 {
 982         return pCKGR->CKGR_MOR;
 983 }
 984
 985 //*----------------------------------------------------------------------------
 986 //* \fn    AT91F_CKGR_EnableMainOscillator
 987 //* \brief Enable the main oscillator
 988 //*----------------------------------------------------------------------------
 989 static inline void AT91F_CKGR_EnableMainOscillator(
 990         AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
 991 {
 992         pCKGR->CKGR_MOR |= AT91C_CKGR_MOSCEN;
 993 }
 994
 995 //*----------------------------------------------------------------------------
 996 //* \fn    AT91F_CKGR_DisableMainOscillator
 997 //* \brief Disable the main oscillator
 998 //*----------------------------------------------------------------------------
 999 static inline void AT91F_CKGR_DisableMainOscillator (
1000         AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
1001 {
1002         pCKGR->CKGR_MOR &= ~AT91C_CKGR_MOSCEN;
1003 }
1004
1005 //*----------------------------------------------------------------------------
1006 //* \fn    AT91F_CKGR_CfgMainOscStartUpTime
1007 //* \brief Cfg MOR Register according to the main osc startup time
1008 //*----------------------------------------------------------------------------
1009 static inline void AT91F_CKGR_CfgMainOscStartUpTime (
1010         AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
1011         unsigned int startup_time,  // \arg main osc startup time in microsecond (us)
1012         unsigned int slowClock)  // \arg slowClock in Hz
1013 {
1014         pCKGR->CKGR_MOR &= ~AT91C_CKGR_OSCOUNT;
1015         pCKGR->CKGR_MOR |= ((slowClock * startup_time)/(8*1000000)) << 8;
1016 }
1017
1018 //*----------------------------------------------------------------------------
1019 //* \fn    AT91F_CKGR_GetMainClockFreqReg
1020 //* \brief Cfg the main oscillator
1021 //*----------------------------------------------------------------------------
1022 static inline unsigned int AT91F_CKGR_GetMainClockFreqReg (
1023         AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
1024 {
1025         return pCKGR->CKGR_MCFR;
1026 }
1027
1028 //*----------------------------------------------------------------------------
1029 //* \fn    AT91F_CKGR_GetMainClock
1030 //* \brief Return Main clock in Hz
1031 //*----------------------------------------------------------------------------
1032 static inline unsigned int AT91F_CKGR_GetMainClock (
1033         AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
1034         unsigned int slowClock)  // \arg slowClock in Hz
1035 {
1036         return ((pCKGR->CKGR_MCFR  & AT91C_CKGR_MAINF) * slowClock) >> 4;
1037 }
1038
1039 //*----------------------------------------------------------------------------
1040 //* \fn    AT91F_PMC_CfgMCKReg
1041 //* \brief Cfg Master Clock Register
1042 //*----------------------------------------------------------------------------
1043 static inline void AT91F_PMC_CfgMCKReg (
1044         AT91PS_PMC pPMC, // \arg pointer to PMC controller
1045         unsigned int mode)
1046 {
1047         pPMC->PMC_MCKR = mode;
1048 }
1049
1050 //*----------------------------------------------------------------------------
1051 //* \fn    AT91F_PMC_GetMCKReg
1052 //* \brief Return Master Clock Register
1053 //*----------------------------------------------------------------------------
1054 static inline unsigned int AT91F_PMC_GetMCKReg(
1055         AT91PS_PMC pPMC) // \arg pointer to PMC controller
1056 {
1057         return pPMC->PMC_MCKR;
1058 }
1059
1060 //*------------------------------------------------------------------------------
1061 //* \fn    AT91F_PMC_GetMasterClock
1062 //* \brief Return master clock in Hz which correponds to processor clock for ARM7
1063 //*------------------------------------------------------------------------------
1064 extern unsigned int AT91F_PMC_GetMasterClock (
1065         AT91PS_PMC pPMC, // \arg pointer to PMC controller
1066         AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
1067         unsigned int slowClock);  // \arg slowClock in Hz
1068
1069 //*----------------------------------------------------------------------------
1070 //* \fn    AT91F_PMC_EnablePCK
1071 //* \brief Enable peripheral clock
1072 //*----------------------------------------------------------------------------
1073 static inline void AT91F_PMC_EnablePCK (
1074         AT91PS_PMC pPMC, // \arg pointer to PMC controller
1075         unsigned int pck,  // \arg Peripheral clock identifier 0 .. 7
1076         unsigned int mode)
1077 {
1078         pPMC->PMC_PCKR[pck] = mode;
1079         pPMC->PMC_SCER = (1 << pck) << 8;
1080 }
1081
1082 //*----------------------------------------------------------------------------
1083 //* \fn    AT91F_PMC_DisablePCK
1084 //* \brief Enable peripheral clock
1085 //*----------------------------------------------------------------------------
1086 static inline void AT91F_PMC_DisablePCK (
1087         AT91PS_PMC pPMC, // \arg pointer to PMC controller
1088         unsigned int pck)  // \arg Peripheral clock identifier 0 .. 7
1089 {
1090         pPMC->PMC_SCDR = (1 << pck) << 8;
1091 }
1092
1093 //*----------------------------------------------------------------------------
1094 //* \fn    AT91F_PMC_EnableIt
1095 //* \brief Enable PMC interrupt
1096 //*----------------------------------------------------------------------------
1097 static inline void AT91F_PMC_EnableIt (
1098         AT91PS_PMC pPMC,     // pointer to a PMC controller
1099         unsigned int flag)   // IT to be enabled
1100 {
1101         //* Write to the IER register
1102         pPMC->PMC_IER = flag;
1103 }
1104
1105 //*----------------------------------------------------------------------------
1106 //* \fn    AT91F_PMC_DisableIt
1107 //* \brief Disable PMC interrupt
1108 //*----------------------------------------------------------------------------
1109 static inline void AT91F_PMC_DisableIt (
1110         AT91PS_PMC pPMC, // pointer to a PMC controller
1111         unsigned int flag) // IT to be disabled
1112 {
1113         //* Write to the IDR register
1114         pPMC->PMC_IDR = flag;
1115 }
1116
1117 //*----------------------------------------------------------------------------
1118 //* \fn    AT91F_PMC_GetStatus
1119 //* \brief Return PMC Interrupt Status
1120 //*----------------------------------------------------------------------------
1121 static inline unsigned int AT91F_PMC_GetStatus( // \return PMC Interrupt Status
1122         AT91PS_PMC pPMC) // pointer to a PMC controller
1123 {
1124         return pPMC->PMC_SR;
1125 }
1126
1127 //*----------------------------------------------------------------------------
1128 //* \fn    AT91F_PMC_GetInterruptMaskStatus
1129 //* \brief Return PMC Interrupt Mask Status
1130 //*----------------------------------------------------------------------------
1131 static inline unsigned int AT91F_PMC_GetInterruptMaskStatus( // \return PMC Interrupt Mask Status
1132         AT91PS_PMC pPMC) // pointer to a PMC controller
1133 {
1134         return pPMC->PMC_IMR;
1135 }
1136
1137 //*----------------------------------------------------------------------------
1138 //* \fn    AT91F_PMC_IsInterruptMasked
1139 //* \brief Test if PMC Interrupt is Masked
1140 //*----------------------------------------------------------------------------
1141 static inline unsigned int AT91F_PMC_IsInterruptMasked(
1142         AT91PS_PMC pPMC,   // \arg  pointer to a PMC controller
1143         unsigned int flag) // \arg  flag to be tested
1144 {
1145         return (AT91F_PMC_GetInterruptMaskStatus(pPMC) & flag);
1146 }
1147
1148 //*----------------------------------------------------------------------------
1149 //* \fn    AT91F_PMC_IsStatusSet
1150 //* \brief Test if PMC Status is Set
1151 //*----------------------------------------------------------------------------
1152 static inline unsigned int AT91F_PMC_IsStatusSet(
1153         AT91PS_PMC pPMC,   // \arg  pointer to a PMC controller
1154         unsigned int flag) // \arg  flag to be tested
1155 {
1156         return (AT91F_PMC_GetStatus(pPMC) & flag);
1157 }
1158
1159 // ----------------------------------------------------------------------------
1160 //  \fn    AT91F_CKGR_CfgPLLReg
1161 //  \brief Cfg the PLL Register
1162 // ----------------------------------------------------------------------------
1163 static inline void AT91F_CKGR_CfgPLLReg (
1164         AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
1165         unsigned int mode)
1166 {
1167         pCKGR->CKGR_PLLR = mode;
1168 }
1169
1170 // ----------------------------------------------------------------------------
1171 //  \fn    AT91F_CKGR_GetPLLReg
1172 //  \brief Get the PLL Register
1173 // ----------------------------------------------------------------------------
1174 static inline unsigned int AT91F_CKGR_GetPLLReg (
1175         AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
1176 {
1177         return pCKGR->CKGR_PLLR;
1178 }
1179
1180
1181
1182 /* *****************************************************************************
1183                 SOFTWARE API FOR RSTC
1184    ***************************************************************************** */
1185 //*----------------------------------------------------------------------------
1186 //* \fn    AT91F_RSTSoftReset
1187 //* \brief Start Software Reset
1188 //*----------------------------------------------------------------------------
1189 static inline void AT91F_RSTSoftReset(
1190         AT91PS_RSTC pRSTC,
1191         unsigned int reset)
1192 {
1193         pRSTC->RSTC_RCR = (0xA5000000 | reset);
1194 }
1195
1196 //*----------------------------------------------------------------------------
1197 //* \fn    AT91F_RSTSetMode
1198 //* \brief Set Reset Mode
1199 //*----------------------------------------------------------------------------
1200 static inline void AT91F_RSTSetMode(
1201         AT91PS_RSTC pRSTC,
1202         unsigned int mode)
1203 {
1204         pRSTC->RSTC_RMR = (0xA5000000 | mode);
1205 }
1206
1207 //*----------------------------------------------------------------------------
1208 //* \fn    AT91F_RSTGetMode
1209 //* \brief Get Reset Mode
1210 //*----------------------------------------------------------------------------
1211 static inline unsigned int AT91F_RSTGetMode(
1212         AT91PS_RSTC pRSTC)
1213 {
1214         return (pRSTC->RSTC_RMR);
1215 }
1216
1217 //*----------------------------------------------------------------------------
1218 //* \fn    AT91F_RSTGetStatus
1219 //* \brief Get Reset Status
1220 //*----------------------------------------------------------------------------
1221 static inline unsigned int AT91F_RSTGetStatus(
1222         AT91PS_RSTC pRSTC)
1223 {
1224         return (pRSTC->RSTC_RSR);
1225 }
1226
1227 //*----------------------------------------------------------------------------
1228 //* \fn    AT91F_RSTIsSoftRstActive
1229 //* \brief Return !=0 if software reset is still not completed
1230 //*----------------------------------------------------------------------------
1231 static inline unsigned int AT91F_RSTIsSoftRstActive(
1232         AT91PS_RSTC pRSTC)
1233 {
1234         return ((pRSTC->RSTC_RSR) & AT91C_RSTC_SRCMP);
1235 }
1236 /* *****************************************************************************
1237                 SOFTWARE API FOR RTTC
1238    ***************************************************************************** */
1239 //*--------------------------------------------------------------------------------------
1240 //* \fn     AT91F_SetRTT_TimeBase()
1241 //* \brief  Set the RTT prescaler according to the TimeBase in ms
1242 //*--------------------------------------------------------------------------------------
1243 static inline unsigned int AT91F_RTTSetTimeBase(
1244         AT91PS_RTTC pRTTC,
1245         unsigned int ms)
1246 {
1247         if (ms > 2000)
1248                 return 1;   // AT91C_TIME_OUT_OF_RANGE
1249         pRTTC->RTTC_RTMR &= ~0xFFFF;
1250         pRTTC->RTTC_RTMR |= (((ms << 15) /1000) & 0xFFFF);
1251         return 0;
1252 }
1253
1254 //*--------------------------------------------------------------------------------------
1255 //* \fn     AT91F_RTTSetPrescaler()
1256 //* \brief  Set the new prescaler value
1257 //*--------------------------------------------------------------------------------------
1258 static inline unsigned int AT91F_RTTSetPrescaler(
1259         AT91PS_RTTC pRTTC,
1260         unsigned int rtpres)
1261 {
1262         pRTTC->RTTC_RTMR &= ~0xFFFF;
1263         pRTTC->RTTC_RTMR |= (rtpres & 0xFFFF);
1264         return (pRTTC->RTTC_RTMR);
1265 }
1266
1267 //*--------------------------------------------------------------------------------------
1268 //* \fn     AT91F_RTTRestart()
1269 //* \brief  Restart the RTT prescaler
1270 //*--------------------------------------------------------------------------------------
1271 static inline void AT91F_RTTRestart(
1272         AT91PS_RTTC pRTTC)
1273 {
1274         pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTRST;
1275 }
1276
1277
1278 //*--------------------------------------------------------------------------------------
1279 //* \fn     AT91F_RTT_SetAlarmINT()
1280 //* \brief  Enable RTT Alarm Interrupt
1281 //*--------------------------------------------------------------------------------------
1282 static inline void AT91F_RTTSetAlarmINT(
1283         AT91PS_RTTC pRTTC)
1284 {
1285         pRTTC->RTTC_RTMR |= AT91C_RTTC_ALMIEN;
1286 }
1287
1288 //*--------------------------------------------------------------------------------------
1289 //* \fn     AT91F_RTT_ClearAlarmINT()
1290 //* \brief  Disable RTT Alarm Interrupt
1291 //*--------------------------------------------------------------------------------------
1292 static inline void AT91F_RTTClearAlarmINT(
1293         AT91PS_RTTC pRTTC)
1294 {
1295         pRTTC->RTTC_RTMR &= ~AT91C_RTTC_ALMIEN;
1296 }
1297
1298 //*--------------------------------------------------------------------------------------
1299 //* \fn     AT91F_RTT_SetRttIncINT()
1300 //* \brief  Enable RTT INC Interrupt
1301 //*--------------------------------------------------------------------------------------
1302 static inline void AT91F_RTTSetRttIncINT(
1303         AT91PS_RTTC pRTTC)
1304 {
1305         pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTINCIEN;
1306 }
1307
1308 //*--------------------------------------------------------------------------------------
1309 //* \fn     AT91F_RTT_ClearRttIncINT()
1310 //* \brief  Disable RTT INC Interrupt
1311 //*--------------------------------------------------------------------------------------
1312 static inline void AT91F_RTTClearRttIncINT(
1313         AT91PS_RTTC pRTTC)
1314 {
1315         pRTTC->RTTC_RTMR &= ~AT91C_RTTC_RTTINCIEN;
1316 }
1317
1318 //*--------------------------------------------------------------------------------------
1319 //* \fn     AT91F_RTT_SetAlarmValue()
1320 //* \brief  Set RTT Alarm Value
1321 //*--------------------------------------------------------------------------------------
1322 static inline void AT91F_RTTSetAlarmValue(
1323         AT91PS_RTTC pRTTC, unsigned int _alarm)
1324 {
1325         pRTTC->RTTC_RTAR = _alarm;
1326 }
1327
1328 //*--------------------------------------------------------------------------------------
1329 //* \fn     AT91F_RTT_GetAlarmValue()
1330 //* \brief  Get RTT Alarm Value
1331 //*--------------------------------------------------------------------------------------
1332 static inline unsigned int AT91F_RTTGetAlarmValue(
1333         AT91PS_RTTC pRTTC)
1334 {
1335         return(pRTTC->RTTC_RTAR);
1336 }
1337
1338 //*--------------------------------------------------------------------------------------
1339 //* \fn     AT91F_RTTGetStatus()
1340 //* \brief  Read the RTT status
1341 //*--------------------------------------------------------------------------------------
1342 static inline unsigned int AT91F_RTTGetStatus(
1343         AT91PS_RTTC pRTTC)
1344 {
1345         return(pRTTC->RTTC_RTSR);
1346 }
1347
1348 //*--------------------------------------------------------------------------------------
1349 //* \fn     AT91F_RTT_ReadValue()
1350 //* \brief  Read the RTT value
1351 //*--------------------------------------------------------------------------------------
1352 extern unsigned int AT91F_RTTReadValue(AT91PS_RTTC pRTTC);
1353
1354 /* *****************************************************************************
1355                 SOFTWARE API FOR PITC
1356    ***************************************************************************** */
1357 //*----------------------------------------------------------------------------
1358 //* \fn    AT91F_PITInit
1359 //* \brief System timer init : period in ‘second, system clock freq in MHz
1360 //*----------------------------------------------------------------------------
1361 static inline void AT91F_PITInit(
1362         AT91PS_PITC pPITC,
1363         unsigned int period,
1364         unsigned int pit_frequency)
1365 {
1366         pPITC->PITC_PIMR = period? (period * pit_frequency + 8) >> 4 : 0; // +8 to avoid %10 and /10
1367         pPITC->PITC_PIMR |= AT91C_PITC_PITEN;
1368 }
1369
1370 //*----------------------------------------------------------------------------
1371 //* \fn    AT91F_PITSetPIV
1372 //* \brief Set the PIT Periodic Interval Value
1373 //*----------------------------------------------------------------------------
1374 static inline void AT91F_PITSetPIV(
1375         AT91PS_PITC pPITC,
1376         unsigned int piv)
1377 {
1378         pPITC->PITC_PIMR = piv | (pPITC->PITC_PIMR & (AT91C_PITC_PITEN | AT91C_PITC_PITIEN));
1379 }
1380
1381 //*----------------------------------------------------------------------------
1382 //* \fn    AT91F_PITEnableInt
1383 //* \brief Enable PIT periodic interrupt
1384 //*----------------------------------------------------------------------------
1385 static inline void AT91F_PITEnableInt(
1386         AT91PS_PITC pPITC)
1387 {
1388         pPITC->PITC_PIMR |= AT91C_PITC_PITIEN;
1389 }
1390
1391 //*----------------------------------------------------------------------------
1392 //* \fn    AT91F_PITDisableInt
1393 //* \brief Disable PIT periodic interrupt
1394 //*----------------------------------------------------------------------------
1395 static inline void AT91F_PITDisableInt(
1396         AT91PS_PITC pPITC)
1397 {
1398         pPITC->PITC_PIMR &= ~AT91C_PITC_PITIEN;
1399 }
1400
1401 //*----------------------------------------------------------------------------
1402 //* \fn    AT91F_PITGetMode
1403 //* \brief Read PIT mode register
1404 //*----------------------------------------------------------------------------
1405 static inline unsigned int AT91F_PITGetMode(
1406         AT91PS_PITC pPITC)
1407 {
1408         return(pPITC->PITC_PIMR);
1409 }
1410
1411 //*----------------------------------------------------------------------------
1412 //* \fn    AT91F_PITGetStatus
1413 //* \brief Read PIT status register
1414 //*----------------------------------------------------------------------------
1415 static inline unsigned int AT91F_PITGetStatus(
1416         AT91PS_PITC pPITC)
1417 {
1418         return(pPITC->PITC_PISR);
1419 }
1420
1421 //*----------------------------------------------------------------------------
1422 //* \fn    AT91F_PITGetPIIR
1423 //* \brief Read PIT CPIV and PICNT without ressetting the counters
1424 //*----------------------------------------------------------------------------
1425 static inline unsigned int AT91F_PITGetPIIR(
1426         AT91PS_PITC pPITC)
1427 {
1428         return(pPITC->PITC_PIIR);
1429 }
1430
1431 //*----------------------------------------------------------------------------
1432 //* \fn    AT91F_PITGetPIVR
1433 //* \brief Read System timer CPIV and PICNT without ressetting the counters
1434 //*----------------------------------------------------------------------------
1435 static inline unsigned int AT91F_PITGetPIVR(
1436         AT91PS_PITC pPITC)
1437 {
1438         return(pPITC->PITC_PIVR);
1439 }
1440 /* *****************************************************************************
1441                 SOFTWARE API FOR WDTC
1442    ***************************************************************************** */
1443 //*----------------------------------------------------------------------------
1444 //* \fn    AT91F_WDTSetMode
1445 //* \brief Set Watchdog Mode Register
1446 //*----------------------------------------------------------------------------
1447 static inline void AT91F_WDTSetMode(
1448         AT91PS_WDTC pWDTC,
1449         unsigned int Mode)
1450 {
1451         pWDTC->WDTC_WDMR = Mode;
1452 }
1453
1454 //*----------------------------------------------------------------------------
1455 //* \fn    AT91F_WDTRestart
1456 //* \brief Restart Watchdog
1457 //*----------------------------------------------------------------------------
1458 static inline void AT91F_WDTRestart(
1459         AT91PS_WDTC pWDTC)
1460 {
1461         pWDTC->WDTC_WDCR = 0xA5000001;
1462 }
1463
1464 //*----------------------------------------------------------------------------
1465 //* \fn    AT91F_WDTSGettatus
1466 //* \brief Get Watchdog Status
1467 //*----------------------------------------------------------------------------
1468 static inline unsigned int AT91F_WDTSGettatus(
1469         AT91PS_WDTC pWDTC)
1470 {
1471         return(pWDTC->WDTC_WDSR & 0x3);
1472 }
1473
1474 //*----------------------------------------------------------------------------
1475 //* \fn    AT91F_WDTGetPeriod
1476 //* \brief Translate ms into Watchdog Compatible value
1477 //*----------------------------------------------------------------------------
1478 static inline unsigned int AT91F_WDTGetPeriod(unsigned int ms)
1479 {
1480         if ((ms < 4) || (ms > 16000))
1481                 return 0;
1482         return((ms << 8) / 1000);
1483 }
1484 /* *****************************************************************************
1485                 SOFTWARE API FOR VREG
1486    ***************************************************************************** */
1487 //*----------------------------------------------------------------------------
1488 //* \fn    AT91F_VREG_Enable_LowPowerMode
1489 //* \brief Enable VREG Low Power Mode
1490 //*----------------------------------------------------------------------------
1491 static inline void AT91F_VREG_Enable_LowPowerMode(
1492         AT91PS_VREG pVREG)
1493 {
1494         pVREG->VREG_MR |= AT91C_VREG_PSTDBY;
1495 }
1496
1497 //*----------------------------------------------------------------------------
1498 //* \fn    AT91F_VREG_Disable_LowPowerMode
1499 //* \brief Disable VREG Low Power Mode
1500 //*----------------------------------------------------------------------------
1501 static inline void AT91F_VREG_Disable_LowPowerMode(
1502         AT91PS_VREG pVREG)
1503 {
1504         pVREG->VREG_MR &= ~AT91C_VREG_PSTDBY;
1505 }/* *****************************************************************************
1506                 SOFTWARE API FOR MC
1507    ***************************************************************************** */
1508
1509 #define AT91C_MC_CORRECT_KEY  ((unsigned int) 0x5A << 24) // (MC) Correct Protect Key
1510
1511 //*----------------------------------------------------------------------------
1512 //* \fn    AT91F_MC_Remap
1513 //* \brief Make Remap
1514 //*----------------------------------------------------------------------------
1515 static inline void AT91F_MC_Remap (void)     //
1516 {
1517     AT91PS_MC pMC = (AT91PS_MC) AT91C_BASE_MC;
1518
1519     pMC->MC_RCR = AT91C_MC_RCB;
1520 }
1521
1522 //*----------------------------------------------------------------------------
1523 //* \fn    AT91F_MC_EFC_CfgModeReg
1524 //* \brief Configure the EFC Mode Register of the MC controller
1525 //*----------------------------------------------------------------------------
1526 static inline void AT91F_MC_EFC_CfgModeReg (
1527         AT91PS_MC pMC, // pointer to a MC controller
1528         unsigned int mode)        // mode register
1529 {
1530         // Write to the FMR register
1531         pMC->MC_FMR = mode;
1532 }
1533
1534 //*----------------------------------------------------------------------------
1535 //* \fn    AT91F_MC_EFC_GetModeReg
1536 //* \brief Return MC EFC Mode Regsiter
1537 //*----------------------------------------------------------------------------
1538 static inline unsigned int AT91F_MC_EFC_GetModeReg(
1539         AT91PS_MC pMC) // pointer to a MC controller
1540 {
1541         return pMC->MC_FMR;
1542 }
1543
1544 //*----------------------------------------------------------------------------
1545 //* \fn    AT91F_MC_EFC_ComputeFMCN
1546 //* \brief Return MC EFC Mode Regsiter
1547 //*----------------------------------------------------------------------------
1548 static inline unsigned int AT91F_MC_EFC_ComputeFMCN(
1549         int master_clock) // master clock in Hz
1550 {
1551         return (master_clock/1000000 +2);
1552 }
1553
1554 //*----------------------------------------------------------------------------
1555 //* \fn    AT91F_MC_EFC_PerformCmd
1556 //* \brief Perform EFC Command
1557 //*----------------------------------------------------------------------------
1558 static inline void AT91F_MC_EFC_PerformCmd (
1559         AT91PS_MC pMC, // pointer to a MC controller
1560     unsigned int transfer_cmd)
1561 {
1562         pMC->MC_FCR = transfer_cmd;
1563 }
1564
1565 //*----------------------------------------------------------------------------
1566 //* \fn    AT91F_MC_EFC_GetStatus
1567 //* \brief Return MC EFC Status
1568 //*----------------------------------------------------------------------------
1569 static inline unsigned int AT91F_MC_EFC_GetStatus(
1570         AT91PS_MC pMC) // pointer to a MC controller
1571 {
1572         return pMC->MC_FSR;
1573 }
1574
1575 //*----------------------------------------------------------------------------
1576 //* \fn    AT91F_MC_EFC_IsInterruptMasked
1577 //* \brief Test if EFC MC Interrupt is Masked
1578 //*----------------------------------------------------------------------------
1579 static inline unsigned int AT91F_MC_EFC_IsInterruptMasked(
1580         AT91PS_MC pMC,   // \arg  pointer to a MC controller
1581         unsigned int flag) // \arg  flag to be tested
1582 {
1583         return (AT91F_MC_EFC_GetModeReg(pMC) & flag);
1584 }
1585
1586 //*----------------------------------------------------------------------------
1587 //* \fn    AT91F_MC_EFC_IsInterruptSet
1588 //* \brief Test if EFC MC Interrupt is Set
1589 //*----------------------------------------------------------------------------
1590 static inline unsigned int AT91F_MC_EFC_IsInterruptSet(
1591         AT91PS_MC pMC,   // \arg  pointer to a MC controller
1592         unsigned int flag) // \arg  flag to be tested
1593 {
1594         return (AT91F_MC_EFC_GetStatus(pMC) & flag);
1595 }
1596
1597 /* *****************************************************************************
1598                 SOFTWARE API FOR SPI
1599    ***************************************************************************** */
1600 //*----------------------------------------------------------------------------
1601 //* \fn    AT91F_SPI_CfgCs
1602 //* \brief Configure SPI chip select register
1603 //*----------------------------------------------------------------------------
1604 static inline void AT91F_SPI_CfgCs (
1605         AT91PS_SPI pSPI,     // pointer to a SPI controller
1606         int cs,     // SPI cs number (0 to 3)
1607         int val)   //  chip select register
1608 {
1609         //* Write to the CSR register
1610         *(pSPI->SPI_CSR + cs) = val;
1611 }
1612
1613 //*----------------------------------------------------------------------------
1614 //* \fn    AT91F_SPI_EnableIt
1615 //* \brief Enable SPI interrupt
1616 //*----------------------------------------------------------------------------
1617 static inline void AT91F_SPI_EnableIt (
1618         AT91PS_SPI pSPI,     // pointer to a SPI controller
1619         unsigned int flag)   // IT to be enabled
1620 {
1621         //* Write to the IER register
1622         pSPI->SPI_IER = flag;
1623 }
1624
1625 //*----------------------------------------------------------------------------
1626 //* \fn    AT91F_SPI_DisableIt
1627 //* \brief Disable SPI interrupt
1628 //*----------------------------------------------------------------------------
1629 static inline void AT91F_SPI_DisableIt (
1630         AT91PS_SPI pSPI, // pointer to a SPI controller
1631         unsigned int flag) // IT to be disabled
1632 {
1633         //* Write to the IDR register
1634         pSPI->SPI_IDR = flag;
1635 }
1636
1637 //*----------------------------------------------------------------------------
1638 //* \fn    AT91F_SPI_Reset
1639 //* \brief Reset the SPI controller
1640 //*----------------------------------------------------------------------------
1641 static inline void AT91F_SPI_Reset (
1642         AT91PS_SPI pSPI // pointer to a SPI controller
1643         )
1644 {
1645         //* Write to the CR register
1646         pSPI->SPI_CR = AT91C_SPI_SWRST;
1647 }
1648
1649 //*----------------------------------------------------------------------------
1650 //* \fn    AT91F_SPI_Enable
1651 //* \brief Enable the SPI controller
1652 //*----------------------------------------------------------------------------
1653 static inline void AT91F_SPI_Enable (
1654         AT91PS_SPI pSPI // pointer to a SPI controller
1655         )
1656 {
1657         //* Write to the CR register
1658         pSPI->SPI_CR = AT91C_SPI_SPIEN;
1659 }
1660
1661 //*----------------------------------------------------------------------------
1662 //* \fn    AT91F_SPI_Disable
1663 //* \brief Disable the SPI controller
1664 //*----------------------------------------------------------------------------
1665 static inline void AT91F_SPI_Disable (
1666         AT91PS_SPI pSPI // pointer to a SPI controller
1667         )
1668 {
1669         //* Write to the CR register
1670         pSPI->SPI_CR = AT91C_SPI_SPIDIS;
1671 }
1672
1673 //*----------------------------------------------------------------------------
1674 //* \fn    AT91F_SPI_CfgMode
1675 //* \brief Enable the SPI controller
1676 //*----------------------------------------------------------------------------
1677 static inline void AT91F_SPI_CfgMode (
1678         AT91PS_SPI pSPI, // pointer to a SPI controller
1679         int mode)        // mode register
1680 {
1681         //* Write to the MR register
1682         pSPI->SPI_MR = mode;
1683 }
1684
1685 //*----------------------------------------------------------------------------
1686 //* \fn    AT91F_SPI_CfgPCS
1687 //* \brief Switch to the correct PCS of SPI Mode Register : Fixed Peripheral Selected
1688 //*----------------------------------------------------------------------------
1689 static inline void AT91F_SPI_CfgPCS (
1690         AT91PS_SPI pSPI, // pointer to a SPI controller
1691         char PCS_Device) // PCS of the Device
1692 {
1693         //* Write to the MR register
1694         pSPI->SPI_MR &= 0xFFF0FFFF;
1695         pSPI->SPI_MR |= ( (PCS_Device<<16) & AT91C_SPI_PCS );
1696 }
1697
1698 //*----------------------------------------------------------------------------
1699 //* \fn    AT91F_SPI_ReceiveFrame
1700 //* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy
1701 //*----------------------------------------------------------------------------
1702 static inline unsigned int AT91F_SPI_ReceiveFrame (
1703         AT91PS_SPI pSPI,
1704         unsigned char *pBuffer,
1705         unsigned int szBuffer,
1706         unsigned char *pNextBuffer,
1707         unsigned int szNextBuffer )
1708 {
1709         return AT91F_PDC_ReceiveFrame(
1710                 (AT91PS_PDC) &(pSPI->SPI_RPR),
1711                 pBuffer,
1712                 szBuffer,
1713                 pNextBuffer,
1714                 szNextBuffer);
1715 }
1716
1717 //*----------------------------------------------------------------------------
1718 //* \fn    AT91F_SPI_SendFrame
1719 //* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is bSPIy
1720 //*----------------------------------------------------------------------------
1721 static inline unsigned int AT91F_SPI_SendFrame(
1722         AT91PS_SPI pSPI,
1723         const unsigned char *pBuffer,
1724         unsigned int szBuffer,
1725         const unsigned char *pNextBuffer,
1726         unsigned int szNextBuffer )
1727 {
1728         return AT91F_PDC_SendFrame(
1729                 (AT91PS_PDC) &(pSPI->SPI_RPR),
1730                 pBuffer,
1731                 szBuffer,
1732                 pNextBuffer,
1733                 szNextBuffer);
1734 }
1735
1736 //*----------------------------------------------------------------------------
1737 //* \fn    AT91F_SPI_Close
1738 //* \brief Close SPI: disable IT disable transfert, close PDC
1739 //*----------------------------------------------------------------------------
1740 extern void AT91F_SPI_Close(AT91PS_SPI pSPI);     // \arg pointer to a SPI controller
1741
1742 //*----------------------------------------------------------------------------
1743 //* \fn    AT91F_SPI_PutChar
1744 //* \brief Send a character,does not check if ready to send
1745 //*----------------------------------------------------------------------------
1746 static inline void AT91F_SPI_PutChar (
1747         AT91PS_SPI pSPI,
1748         unsigned int character,
1749              unsigned int cs_number )
1750 {
1751     unsigned int value_for_cs;
1752     value_for_cs = (~(1 << cs_number)) & 0xF;  //Place a zero among a 4 ONEs number
1753     pSPI->SPI_TDR = (character & 0xFFFF) | (value_for_cs << 16);
1754 }
1755
1756 //*----------------------------------------------------------------------------
1757 //* \fn    AT91F_SPI_GetChar
1758 //* \brief Receive a character,does not check if a character is available
1759 //*----------------------------------------------------------------------------
1760 static inline int AT91F_SPI_GetChar (
1761         const AT91PS_SPI pSPI)
1762 {
1763     return((pSPI->SPI_RDR) & 0xFFFF);
1764 }
1765
1766 //*----------------------------------------------------------------------------
1767 //* \fn    AT91F_SPI_GetInterruptMaskStatus
1768 //* \brief Return SPI Interrupt Mask Status
1769 //*----------------------------------------------------------------------------
1770 static inline unsigned int AT91F_SPI_GetInterruptMaskStatus( // \return SPI Interrupt Mask Status
1771         AT91PS_SPI pSpi) // \arg  pointer to a SPI controller
1772 {
1773         return pSpi->SPI_IMR;
1774 }
1775
1776 //*----------------------------------------------------------------------------
1777 //* \fn    AT91F_SPI_IsInterruptMasked
1778 //* \brief Test if SPI Interrupt is Masked
1779 //*----------------------------------------------------------------------------
1780 static inline int AT91F_SPI_IsInterruptMasked(
1781         AT91PS_SPI pSpi,   // \arg  pointer to a SPI controller
1782         unsigned int flag) // \arg  flag to be tested
1783 {
1784         return (AT91F_SPI_GetInterruptMaskStatus(pSpi) & flag);
1785 }
1786
1787 /* *****************************************************************************
1788                 SOFTWARE API FOR ADC
1789    ***************************************************************************** */
1790 //*----------------------------------------------------------------------------
1791 //* \fn    AT91F_ADC_EnableIt
1792 //* \brief Enable ADC interrupt
1793 //*----------------------------------------------------------------------------
1794 static inline void AT91F_ADC_EnableIt (
1795         AT91PS_ADC pADC,     // pointer to a ADC controller
1796         unsigned int flag)   // IT to be enabled
1797 {
1798         //* Write to the IER register
1799         pADC->ADC_IER = flag;
1800 }
1801
1802 //*----------------------------------------------------------------------------
1803 //* \fn    AT91F_ADC_DisableIt
1804 //* \brief Disable ADC interrupt
1805 //*----------------------------------------------------------------------------
1806 static inline void AT91F_ADC_DisableIt (
1807         AT91PS_ADC pADC, // pointer to a ADC controller
1808         unsigned int flag) // IT to be disabled
1809 {
1810         //* Write to the IDR register
1811         pADC->ADC_IDR = flag;
1812 }
1813
1814 //*----------------------------------------------------------------------------
1815 //* \fn    AT91F_ADC_GetStatus
1816 //* \brief Return ADC Interrupt Status
1817 //*----------------------------------------------------------------------------
1818 static inline unsigned int AT91F_ADC_GetStatus( // \return ADC Interrupt Status
1819         AT91PS_ADC pADC) // pointer to a ADC controller
1820 {
1821         return pADC->ADC_SR;
1822 }
1823
1824 //*----------------------------------------------------------------------------
1825 //* \fn    AT91F_ADC_GetInterruptMaskStatus
1826 //* \brief Return ADC Interrupt Mask Status
1827 //*----------------------------------------------------------------------------
1828 static inline unsigned int AT91F_ADC_GetInterruptMaskStatus( // \return ADC Interrupt Mask Status
1829         AT91PS_ADC pADC) // pointer to a ADC controller
1830 {
1831         return pADC->ADC_IMR;
1832 }
1833
1834 //*----------------------------------------------------------------------------
1835 //* \fn    AT91F_ADC_IsInterruptMasked
1836 //* \brief Test if ADC Interrupt is Masked
1837 //*----------------------------------------------------------------------------
1838 static inline unsigned int AT91F_ADC_IsInterruptMasked(
1839         AT91PS_ADC pADC,   // \arg  pointer to a ADC controller
1840         unsigned int flag) // \arg  flag to be tested
1841 {
1842         return (AT91F_ADC_GetInterruptMaskStatus(pADC) & flag);
1843 }
1844
1845 //*----------------------------------------------------------------------------
1846 //* \fn    AT91F_ADC_IsStatusSet
1847 //* \brief Test if ADC Status is Set
1848 //*----------------------------------------------------------------------------
1849 static inline unsigned int AT91F_ADC_IsStatusSet(
1850         AT91PS_ADC pADC,   // \arg  pointer to a ADC controller
1851         unsigned int flag) // \arg  flag to be tested
1852 {
1853         return (AT91F_ADC_GetStatus(pADC) & flag);
1854 }
1855
1856 //*----------------------------------------------------------------------------
1857 //* \fn    AT91F_ADC_CfgModeReg
1858 //* \brief Configure the Mode Register of the ADC controller
1859 //*----------------------------------------------------------------------------
1860 static inline void AT91F_ADC_CfgModeReg (
1861         AT91PS_ADC pADC, // pointer to a ADC controller
1862         unsigned int mode)        // mode register
1863 {
1864         //* Write to the MR register
1865         pADC->ADC_MR = mode;
1866 }
1867
1868 //*----------------------------------------------------------------------------
1869 //* \fn    AT91F_ADC_GetModeReg
1870 //* \brief Return the Mode Register of the ADC controller value
1871 //*----------------------------------------------------------------------------
1872 static inline unsigned int AT91F_ADC_GetModeReg (
1873         AT91PS_ADC pADC // pointer to a ADC controller
1874         )
1875 {
1876         return pADC->ADC_MR;
1877 }
1878
1879 //*----------------------------------------------------------------------------
1880 //* \fn    AT91F_ADC_CfgTimings
1881 //* \brief Configure the different necessary timings of the ADC controller
1882 //*----------------------------------------------------------------------------
1883 extern void AT91F_ADC_CfgTimings (
1884         AT91PS_ADC pADC, // pointer to a ADC controller
1885         unsigned int mck_clock, // in MHz
1886         unsigned int adc_clock, // in MHz
1887         unsigned int startup_time, // in us
1888         unsigned int sample_and_hold_time);     // in ns
1889
1890 //*----------------------------------------------------------------------------
1891 //* \fn    AT91F_ADC_EnableChannel
1892 //* \brief Return ADC Timer Register Value
1893 //*----------------------------------------------------------------------------
1894 static inline void AT91F_ADC_EnableChannel (
1895         AT91PS_ADC pADC, // pointer to a ADC controller
1896         unsigned int channel)        // mode register
1897 {
1898         //* Write to the CHER register
1899         pADC->ADC_CHER = channel;
1900 }
1901
1902 //*----------------------------------------------------------------------------
1903 //* \fn    AT91F_ADC_DisableChannel
1904 //* \brief Return ADC Timer Register Value
1905 //*----------------------------------------------------------------------------
1906 static inline void AT91F_ADC_DisableChannel (
1907         AT91PS_ADC pADC, // pointer to a ADC controller
1908         unsigned int channel)        // mode register
1909 {
1910         //* Write to the CHDR register
1911         pADC->ADC_CHDR = channel;
1912 }
1913
1914 //*----------------------------------------------------------------------------
1915 //* \fn    AT91F_ADC_GetChannelStatus
1916 //* \brief Return ADC Timer Register Value
1917 //*----------------------------------------------------------------------------
1918 static inline unsigned int AT91F_ADC_GetChannelStatus (
1919         AT91PS_ADC pADC // pointer to a ADC controller
1920         )
1921 {
1922         return pADC->ADC_CHSR;
1923 }
1924
1925 //*----------------------------------------------------------------------------
1926 //* \fn    AT91F_ADC_StartConversion
1927 //* \brief Software request for a analog to digital conversion
1928 //*----------------------------------------------------------------------------
1929 static inline void AT91F_ADC_StartConversion (
1930         AT91PS_ADC pADC // pointer to a ADC controller
1931         )
1932 {
1933         pADC->ADC_CR = AT91C_ADC_START;
1934 }
1935
1936 //*----------------------------------------------------------------------------
1937 //* \fn    AT91F_ADC_SoftReset
1938 //* \brief Software reset
1939 //*----------------------------------------------------------------------------
1940 static inline void AT91F_ADC_SoftReset (
1941         AT91PS_ADC pADC // pointer to a ADC controller
1942         )
1943 {
1944         pADC->ADC_CR = AT91C_ADC_SWRST;
1945 }
1946
1947 //*----------------------------------------------------------------------------
1948 //* \fn    AT91F_ADC_GetLastConvertedData
1949 //* \brief Return the Last Converted Data
1950 //*----------------------------------------------------------------------------
1951 static inline unsigned int AT91F_ADC_GetLastConvertedData (
1952         AT91PS_ADC pADC // pointer to a ADC controller
1953         )
1954 {
1955         return pADC->ADC_LCDR;
1956 }
1957
1958 //*----------------------------------------------------------------------------
1959 //* \fn    AT91F_ADC_GetConvertedDataCH0
1960 //* \brief Return the Channel 0 Converted Data
1961 //*----------------------------------------------------------------------------
1962 static inline unsigned int AT91F_ADC_GetConvertedDataCH0 (
1963         AT91PS_ADC pADC // pointer to a ADC controller
1964         )
1965 {
1966         return pADC->ADC_CDR0;
1967 }
1968
1969 //*----------------------------------------------------------------------------
1970 //* \fn    AT91F_ADC_GetConvertedDataCH1
1971 //* \brief Return the Channel 1 Converted Data
1972 //*----------------------------------------------------------------------------
1973 static inline unsigned int AT91F_ADC_GetConvertedDataCH1 (
1974         AT91PS_ADC pADC // pointer to a ADC controller
1975         )
1976 {
1977         return pADC->ADC_CDR1;
1978 }
1979
1980 //*----------------------------------------------------------------------------
1981 //* \fn    AT91F_ADC_GetConvertedDataCH2
1982 //* \brief Return the Channel 2 Converted Data
1983 //*----------------------------------------------------------------------------
1984 static inline unsigned int AT91F_ADC_GetConvertedDataCH2 (
1985         AT91PS_ADC pADC // pointer to a ADC controller
1986         )
1987 {
1988         return pADC->ADC_CDR2;
1989 }
1990
1991 //*----------------------------------------------------------------------------
1992 //* \fn    AT91F_ADC_GetConvertedDataCH3
1993 //* \brief Return the Channel 3 Converted Data
1994 //*----------------------------------------------------------------------------
1995 static inline unsigned int AT91F_ADC_GetConvertedDataCH3 (
1996         AT91PS_ADC pADC // pointer to a ADC controller
1997         )
1998 {
1999         return pADC->ADC_CDR3;
2000 }
2001
2002 //*----------------------------------------------------------------------------
2003 //* \fn    AT91F_ADC_GetConvertedDataCH4
2004 //* \brief Return the Channel 4 Converted Data
2005 //*----------------------------------------------------------------------------
2006 static inline unsigned int AT91F_ADC_GetConvertedDataCH4 (
2007         AT91PS_ADC pADC // pointer to a ADC controller
2008         )
2009 {
2010         return pADC->ADC_CDR4;
2011 }
2012
2013 //*----------------------------------------------------------------------------
2014 //* \fn    AT91F_ADC_GetConvertedDataCH5
2015 //* \brief Return the Channel 5 Converted Data
2016 //*----------------------------------------------------------------------------
2017 static inline unsigned int AT91F_ADC_GetConvertedDataCH5 (
2018         AT91PS_ADC pADC // pointer to a ADC controller
2019         )
2020 {
2021         return pADC->ADC_CDR5;
2022 }
2023
2024 //*----------------------------------------------------------------------------
2025 //* \fn    AT91F_ADC_GetConvertedDataCH6
2026 //* \brief Return the Channel 6 Converted Data
2027 //*----------------------------------------------------------------------------
2028 static inline unsigned int AT91F_ADC_GetConvertedDataCH6 (
2029         AT91PS_ADC pADC // pointer to a ADC controller
2030         )
2031 {
2032         return pADC->ADC_CDR6;
2033 }
2034
2035 //*----------------------------------------------------------------------------
2036 //* \fn    AT91F_ADC_GetConvertedDataCH7
2037 //* \brief Return the Channel 7 Converted Data
2038 //*----------------------------------------------------------------------------
2039 static inline unsigned int AT91F_ADC_GetConvertedDataCH7 (
2040         AT91PS_ADC pADC // pointer to a ADC controller
2041         )
2042 {
2043         return pADC->ADC_CDR7;
2044 }
2045
2046 /* *****************************************************************************
2047                 SOFTWARE API FOR SSC
2048    ***************************************************************************** */
2049 //* Define the standard I2S mode configuration
2050
2051 //* Configuration to set in the SSC Transmit Clock Mode Register
2052 //* Parameters :  nb_bit_by_slot : 8, 16 or 32 bits
2053 //*                       nb_slot_by_frame : number of channels
2054 #define AT91C_I2S_ASY_MASTER_TX_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\
2055                                                                            AT91C_SSC_CKS_DIV   +\
2056                                            AT91C_SSC_CKO_CONTINOUS      +\
2057                                            AT91C_SSC_CKG_NONE    +\
2058                                        AT91C_SSC_START_FALL_RF +\
2059                                                    AT91C_SSC_STTOUT  +\
2060                                            ((1<<16) & AT91C_SSC_STTDLY) +\
2061                                            ((((nb_bit_by_slot*nb_slot_by_frame)/2)-1) <<24))
2062
2063
2064 //* Configuration to set in the SSC Transmit Frame Mode Register
2065 //* Parameters : nb_bit_by_slot : 8, 16 or 32 bits
2066 //*                      nb_slot_by_frame : number of channels
2067 #define AT91C_I2S_ASY_TX_FRAME_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\
2068                                                                         (nb_bit_by_slot-1)  +\
2069                                         AT91C_SSC_MSBF   +\
2070                                         (((nb_slot_by_frame-1)<<8) & AT91C_SSC_DATNB)  +\
2071                                         (((nb_bit_by_slot-1)<<16) & AT91C_SSC_FSLEN) +\
2072                                         AT91C_SSC_FSOS_NEGATIVE)
2073
2074
2075 //*----------------------------------------------------------------------------
2076 //* \fn    AT91F_SSC_SetBaudrate
2077 //* \brief Set the baudrate according to the CPU clock
2078 //*----------------------------------------------------------------------------
2079 extern void AT91F_SSC_SetBaudrate (
2080         AT91PS_SSC pSSC,        // \arg pointer to a SSC controller
2081         unsigned int mainClock, // \arg peripheral clock
2082         unsigned int speed);     // \arg SSC baudrate
2083
2084 //*----------------------------------------------------------------------------
2085 //* \fn    AT91F_SSC_Configure
2086 //* \brief Configure SSC
2087 //*----------------------------------------------------------------------------
2088 extern void AT91F_SSC_Configure (
2089              AT91PS_SSC pSSC,          // \arg pointer to a SSC controller
2090              unsigned int syst_clock,  // \arg System Clock Frequency
2091              unsigned int baud_rate,   // \arg Expected Baud Rate Frequency
2092              unsigned int clock_rx,    // \arg Receiver Clock Parameters
2093              unsigned int mode_rx,     // \arg mode Register to be programmed
2094              unsigned int clock_tx,    // \arg Transmitter Clock Parameters
2095              unsigned int mode_tx);    // \arg mode Register to be programmed
2096
2097 //*----------------------------------------------------------------------------
2098 //* \fn    AT91F_SSC_EnableRx
2099 //* \brief Enable receiving datas
2100 //*----------------------------------------------------------------------------
2101 static inline void AT91F_SSC_EnableRx (
2102         AT91PS_SSC pSSC)     // \arg pointer to a SSC controller
2103 {
2104     //* Enable receiver
2105     pSSC->SSC_CR = AT91C_SSC_RXEN;
2106 }
2107
2108 //*----------------------------------------------------------------------------
2109 //* \fn    AT91F_SSC_DisableRx
2110 //* \brief Disable receiving datas
2111 //*----------------------------------------------------------------------------
2112 static inline void AT91F_SSC_DisableRx (
2113         AT91PS_SSC pSSC)     // \arg pointer to a SSC controller
2114 {
2115     //* Disable receiver
2116     pSSC->SSC_CR = AT91C_SSC_RXDIS;
2117 }
2118
2119 //*----------------------------------------------------------------------------
2120 //* \fn    AT91F_SSC_EnableTx
2121 //* \brief Enable sending datas
2122 //*----------------------------------------------------------------------------
2123 static inline void AT91F_SSC_EnableTx (
2124         AT91PS_SSC pSSC)     // \arg pointer to a SSC controller
2125 {
2126     //* Enable  transmitter
2127     pSSC->SSC_CR = AT91C_SSC_TXEN;
2128 }
2129
2130 //*----------------------------------------------------------------------------
2131 //* \fn    AT91F_SSC_DisableTx
2132 //* \brief Disable sending datas
2133 //*----------------------------------------------------------------------------
2134 static inline void AT91F_SSC_DisableTx (
2135         AT91PS_SSC pSSC)     // \arg pointer to a SSC controller
2136 {
2137     //* Disable  transmitter
2138     pSSC->SSC_CR = AT91C_SSC_TXDIS;
2139 }
2140
2141 //*----------------------------------------------------------------------------
2142 //* \fn    AT91F_SSC_EnableIt
2143 //* \brief Enable SSC IT
2144 //*----------------------------------------------------------------------------
2145 static inline void AT91F_SSC_EnableIt (
2146         AT91PS_SSC pSSC, // \arg pointer to a SSC controller
2147         unsigned int flag)   // \arg IT to be enabled
2148 {
2149         //* Write to the IER register
2150         pSSC->SSC_IER = flag;
2151 }
2152
2153 //*----------------------------------------------------------------------------
2154 //* \fn    AT91F_SSC_DisableIt
2155 //* \brief Disable SSC IT
2156 //*----------------------------------------------------------------------------
2157 static inline void AT91F_SSC_DisableIt (
2158         AT91PS_SSC pSSC, // \arg pointer to a SSC controller
2159         unsigned int flag)   // \arg IT to be disabled
2160 {
2161         //* Write to the IDR register
2162         pSSC->SSC_IDR = flag;
2163 }
2164
2165 //*----------------------------------------------------------------------------
2166 //* \fn    AT91F_SSC_ReceiveFrame
2167 //* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy
2168 //*----------------------------------------------------------------------------
2169 static inline unsigned int AT91F_SSC_ReceiveFrame (
2170         AT91PS_SSC pSSC,
2171         unsigned char *pBuffer,
2172         unsigned int szBuffer,
2173         unsigned char *pNextBuffer,
2174         unsigned int szNextBuffer )
2175 {
2176         return AT91F_PDC_ReceiveFrame(
2177                 (AT91PS_PDC) &(pSSC->SSC_RPR),
2178                 pBuffer,
2179                 szBuffer,
2180                 pNextBuffer,
2181                 szNextBuffer);
2182 }
2183
2184 //*----------------------------------------------------------------------------
2185 //* \fn    AT91F_SSC_SendFrame
2186 //* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy
2187 //*----------------------------------------------------------------------------
2188 static inline unsigned int AT91F_SSC_SendFrame(
2189         AT91PS_SSC pSSC,
2190         const unsigned char *pBuffer,
2191         unsigned int szBuffer,
2192         const unsigned char *pNextBuffer,
2193         unsigned int szNextBuffer )
2194 {
2195         return AT91F_PDC_SendFrame(
2196                 (AT91PS_PDC) &(pSSC->SSC_RPR),
2197                 pBuffer,
2198                 szBuffer,
2199                 pNextBuffer,
2200                 szNextBuffer);
2201 }
2202
2203 //*----------------------------------------------------------------------------
2204 //* \fn    AT91F_SSC_GetInterruptMaskStatus
2205 //* \brief Return SSC Interrupt Mask Status
2206 //*----------------------------------------------------------------------------
2207 static inline unsigned int AT91F_SSC_GetInterruptMaskStatus( // \return SSC Interrupt Mask Status
2208         AT91PS_SSC pSsc) // \arg  pointer to a SSC controller
2209 {
2210         return pSsc->SSC_IMR;
2211 }
2212
2213 //*----------------------------------------------------------------------------
2214 //* \fn    AT91F_SSC_IsInterruptMasked
2215 //* \brief Test if SSC Interrupt is Masked
2216 //*----------------------------------------------------------------------------
2217 static inline int AT91F_SSC_IsInterruptMasked(
2218         AT91PS_SSC pSsc,   // \arg  pointer to a SSC controller
2219         unsigned int flag) // \arg  flag to be tested
2220 {
2221         return (AT91F_SSC_GetInterruptMaskStatus(pSsc) & flag);
2222 }
2223
2224 /* *****************************************************************************
2225                 SOFTWARE API FOR USART
2226    ***************************************************************************** */
2227 //*----------------------------------------------------------------------------
2228 //* \fn    AT91F_US_Baudrate
2229 //* \brief Calculate the baudrate
2230 //* Standard Asynchronous Mode : 8 bits , 1 stop , no parity
2231 #define AT91C_US_ASYNC_MODE ( AT91C_US_USMODE_NORMAL + \
2232                         AT91C_US_NBSTOP_1_BIT + \
2233                         AT91C_US_PAR_NONE + \
2234                         AT91C_US_CHRL_8_BITS + \
2235                         AT91C_US_CLKS_CLOCK )
2236
2237 //* Standard External Asynchronous Mode : 8 bits , 1 stop , no parity
2238 #define AT91C_US_ASYNC_SCK_MODE ( AT91C_US_USMODE_NORMAL + \
2239                             AT91C_US_NBSTOP_1_BIT + \
2240                             AT91C_US_PAR_NONE + \
2241                             AT91C_US_CHRL_8_BITS + \
2242                             AT91C_US_CLKS_EXT )
2243
2244 //* Standard Synchronous Mode : 8 bits , 1 stop , no parity
2245 #define AT91C_US_SYNC_MODE ( AT91C_US_SYNC + \
2246                        AT91C_US_USMODE_NORMAL + \
2247                        AT91C_US_NBSTOP_1_BIT + \
2248                        AT91C_US_PAR_NONE + \
2249                        AT91C_US_CHRL_8_BITS + \
2250                        AT91C_US_CLKS_CLOCK )
2251
2252 //* SCK used Label
2253 #define AT91C_US_SCK_USED (AT91C_US_CKLO | AT91C_US_CLKS_EXT)
2254
2255 //* Standard ISO T=0 Mode : 8 bits , 1 stop , parity
2256 #define AT91C_US_ISO_READER_MODE ( AT91C_US_USMODE_ISO7816_0 + \
2257                                                          AT91C_US_CLKS_CLOCK +\
2258                                  AT91C_US_NBSTOP_1_BIT + \
2259                                  AT91C_US_PAR_EVEN + \
2260                                  AT91C_US_CHRL_8_BITS + \
2261                                  AT91C_US_CKLO +\
2262                                  AT91C_US_OVER)
2263
2264 //* Standard IRDA mode
2265 #define AT91C_US_ASYNC_IRDA_MODE (  AT91C_US_USMODE_IRDA + \
2266                             AT91C_US_NBSTOP_1_BIT + \
2267                             AT91C_US_PAR_NONE + \
2268                             AT91C_US_CHRL_8_BITS + \
2269                             AT91C_US_CLKS_CLOCK )
2270
2271 //*----------------------------------------------------------------------------
2272 //* \fn    AT91F_US_Baudrate
2273 //* \brief Caluculate baud_value according to the main clock and the baud rate
2274 //*----------------------------------------------------------------------------
2275 static inline unsigned int AT91F_US_Baudrate (
2276         const unsigned int main_clock, // \arg peripheral clock
2277         const unsigned int baud_rate)  // \arg UART baudrate
2278 {
2279         unsigned int baud_value = ((main_clock*10)/(baud_rate * 16));
2280         if ((baud_value % 10) >= 5)
2281                 baud_value = (baud_value / 10) + 1;
2282         else
2283                 baud_value /= 10;
2284         return baud_value;
2285 }
2286
2287 //*----------------------------------------------------------------------------
2288 //* \fn    AT91F_US_SetBaudrate
2289 //* \brief Set the baudrate according to the CPU clock
2290 //*----------------------------------------------------------------------------
2291 static inline void AT91F_US_SetBaudrate (
2292         AT91PS_USART pUSART,    // \arg pointer to a USART controller
2293         unsigned int mainClock, // \arg peripheral clock
2294         unsigned int speed)     // \arg UART baudrate
2295 {
2296         //* Define the baud rate divisor register
2297         pUSART->US_BRGR = AT91F_US_Baudrate(mainClock, speed);
2298 }
2299
2300 //*----------------------------------------------------------------------------
2301 //* \fn    AT91F_US_SetTimeguard
2302 //* \brief Set USART timeguard
2303 //*----------------------------------------------------------------------------
2304 static inline void AT91F_US_SetTimeguard (
2305         AT91PS_USART pUSART,    // \arg pointer to a USART controller
2306         unsigned int timeguard) // \arg timeguard value
2307 {
2308         //* Write the Timeguard Register
2309         pUSART->US_TTGR = timeguard ;
2310 }
2311
2312 //*----------------------------------------------------------------------------
2313 //* \fn    AT91F_US_EnableIt
2314 //* \brief Enable USART IT
2315 //*----------------------------------------------------------------------------
2316 static inline void AT91F_US_EnableIt (
2317         AT91PS_USART pUSART, // \arg pointer to a USART controller
2318         unsigned int flag)   // \arg IT to be enabled
2319 {
2320         //* Write to the IER register
2321         pUSART->US_IER = flag;
2322 }
2323
2324 //*----------------------------------------------------------------------------
2325 //* \fn    AT91F_US_DisableIt
2326 //* \brief Disable USART IT
2327 //*----------------------------------------------------------------------------
2328 static inline void AT91F_US_DisableIt (
2329         AT91PS_USART pUSART, // \arg pointer to a USART controller
2330         unsigned int flag)   // \arg IT to be disabled
2331 {
2332         //* Write to the IER register
2333         pUSART->US_IDR = flag;
2334 }
2335
2336 //*----------------------------------------------------------------------------
2337 //* \fn    AT91F_US_Configure
2338 //* \brief Configure USART
2339 //*----------------------------------------------------------------------------
2340 extern void AT91F_US_Configure (
2341         AT91PS_USART pUSART,     // \arg pointer to a USART controller
2342         unsigned int mainClock,  // \arg peripheral clock
2343         unsigned int mode ,      // \arg mode Register to be programmed
2344         unsigned int baudRate ,  // \arg baudrate to be programmed
2345         unsigned int timeguard ); // \arg timeguard to be programmed
2346
2347 //*----------------------------------------------------------------------------
2348 //* \fn    AT91F_US_EnableRx
2349 //* \brief Enable receiving characters
2350 //*----------------------------------------------------------------------------
2351 static inline void AT91F_US_EnableRx (
2352         AT91PS_USART pUSART)     // \arg pointer to a USART controller
2353 {
2354     //* Enable receiver
2355     pUSART->US_CR = AT91C_US_RXEN;
2356 }
2357
2358 //*----------------------------------------------------------------------------
2359 //* \fn    AT91F_US_EnableTx
2360 //* \brief Enable sending characters
2361 //*----------------------------------------------------------------------------
2362 static inline void AT91F_US_EnableTx (
2363         AT91PS_USART pUSART)     // \arg pointer to a USART controller
2364 {
2365     //* Enable  transmitter
2366     pUSART->US_CR = AT91C_US_TXEN;
2367 }
2368
2369 //*----------------------------------------------------------------------------
2370 //* \fn    AT91F_US_ResetRx
2371 //* \brief Reset Receiver and re-enable it
2372 //*----------------------------------------------------------------------------
2373 static inline void AT91F_US_ResetRx (
2374         AT91PS_USART pUSART)     // \arg pointer to a USART controller
2375 {
2376         //* Reset receiver
2377         pUSART->US_CR = AT91C_US_RSTRX;
2378     //* Re-Enable receiver
2379     pUSART->US_CR = AT91C_US_RXEN;
2380 }
2381
2382 //*----------------------------------------------------------------------------
2383 //* \fn    AT91F_US_ResetTx
2384 //* \brief Reset Transmitter and re-enable it
2385 //*----------------------------------------------------------------------------
2386 static inline void AT91F_US_ResetTx (
2387         AT91PS_USART pUSART)     // \arg pointer to a USART controller
2388 {
2389         //* Reset transmitter
2390         pUSART->US_CR = AT91C_US_RSTTX;
2391     //* Enable transmitter
2392     pUSART->US_CR = AT91C_US_TXEN;
2393 }
2394
2395 //*----------------------------------------------------------------------------
2396 //* \fn    AT91F_US_DisableRx
2397 //* \brief Disable Receiver
2398 //*----------------------------------------------------------------------------
2399 static inline void AT91F_US_DisableRx (
2400         AT91PS_USART pUSART)     // \arg pointer to a USART controller
2401 {
2402     //* Disable receiver
2403     pUSART->US_CR = AT91C_US_RXDIS;
2404 }
2405
2406 //*----------------------------------------------------------------------------
2407 //* \fn    AT91F_US_DisableTx
2408 //* \brief Disable Transmitter
2409 //*----------------------------------------------------------------------------
2410 static inline void AT91F_US_DisableTx (
2411         AT91PS_USART pUSART)     // \arg pointer to a USART controller
2412 {
2413     //* Disable transmitter
2414     pUSART->US_CR = AT91C_US_TXDIS;
2415 }
2416
2417 //*----------------------------------------------------------------------------
2418 //* \fn    AT91F_US_Close
2419 //* \brief Close USART: disable IT disable receiver and transmitter, close PDC
2420 //*----------------------------------------------------------------------------
2421 extern void AT91F_US_Close(AT91PS_USART pUSART);     // \arg pointer to a USART controller
2422
2423 //*----------------------------------------------------------------------------
2424 //* \fn    AT91F_US_TxReady
2425 //* \brief Return 1 if a character can be written in US_THR
2426 //*----------------------------------------------------------------------------
2427 static inline unsigned int AT91F_US_TxReady (
2428         AT91PS_USART pUSART )     // \arg pointer to a USART controller
2429 {
2430     return (pUSART->US_CSR & AT91C_US_TXRDY);
2431 }
2432
2433 //*----------------------------------------------------------------------------
2434 //* \fn    AT91F_US_RxReady
2435 //* \brief Return 1 if a character can be read in US_RHR
2436 //*----------------------------------------------------------------------------
2437 static inline unsigned int AT91F_US_RxReady (
2438         AT91PS_USART pUSART )     // \arg pointer to a USART controller
2439 {
2440     return (pUSART->US_CSR & AT91C_US_RXRDY);
2441 }
2442
2443 //*----------------------------------------------------------------------------
2444 //* \fn    AT91F_US_Error
2445 //* \brief Return the error flag
2446 //*----------------------------------------------------------------------------
2447 static inline unsigned int AT91F_US_Error (
2448         AT91PS_USART pUSART )     // \arg pointer to a USART controller
2449 {
2450     return (pUSART->US_CSR &
2451         (AT91C_US_OVRE |  // Overrun error
2452          AT91C_US_FRAME | // Framing error
2453          AT91C_US_PARE));  // Parity error
2454 }
2455
2456 //*----------------------------------------------------------------------------
2457 //* \fn    AT91F_US_PutChar
2458 //* \brief Send a character,does not check if ready to send
2459 //*----------------------------------------------------------------------------
2460 static inline void AT91F_US_PutChar (
2461         AT91PS_USART pUSART,
2462         int character )
2463 {
2464     pUSART->US_THR = (character & 0x1FF);
2465 }
2466
2467 //*----------------------------------------------------------------------------
2468 //* \fn    AT91F_US_GetChar
2469 //* \brief Receive a character,does not check if a character is available
2470 //*----------------------------------------------------------------------------
2471 static inline int AT91F_US_GetChar (
2472         const AT91PS_USART pUSART)
2473 {
2474     return((pUSART->US_RHR) & 0x1FF);
2475 }
2476
2477 //*----------------------------------------------------------------------------
2478 //* \fn    AT91F_US_SendFrame
2479 //* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy
2480 //*----------------------------------------------------------------------------
2481 static inline unsigned int AT91F_US_SendFrame(
2482         AT91PS_USART pUSART,
2483         const unsigned char *pBuffer,
2484         unsigned int szBuffer,
2485         const unsigned char *pNextBuffer,
2486         unsigned int szNextBuffer )
2487 {
2488         return AT91F_PDC_SendFrame(
2489                 (AT91PS_PDC) &(pUSART->US_RPR),
2490                 pBuffer,
2491                 szBuffer,
2492                 pNextBuffer,
2493                 szNextBuffer);
2494 }
2495
2496 //*----------------------------------------------------------------------------
2497 //* \fn    AT91F_US_ReceiveFrame
2498 //* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy
2499 //*----------------------------------------------------------------------------
2500 static inline unsigned int AT91F_US_ReceiveFrame (
2501         AT91PS_USART pUSART,
2502         unsigned char *pBuffer,
2503         unsigned int szBuffer,
2504         unsigned char *pNextBuffer,
2505         unsigned int szNextBuffer )
2506 {
2507         return AT91F_PDC_ReceiveFrame(
2508                 (AT91PS_PDC) &(pUSART->US_RPR),
2509                 pBuffer,
2510                 szBuffer,
2511                 pNextBuffer,
2512                 szNextBuffer);
2513 }
2514
2515 //*----------------------------------------------------------------------------
2516 //* \fn    AT91F_US_SetIrdaFilter
2517 //* \brief Set the value of IrDa filter tregister
2518 //*----------------------------------------------------------------------------
2519 static inline void AT91F_US_SetIrdaFilter (
2520         AT91PS_USART pUSART,
2521         unsigned char value
2522 )
2523 {
2524         pUSART->US_IF = value;
2525 }
2526
2527 /* *****************************************************************************
2528                 SOFTWARE API FOR TWI
2529    ***************************************************************************** */
2530 //*----------------------------------------------------------------------------
2531 //* \fn    AT91F_TWI_EnableIt
2532 //* \brief Enable TWI IT
2533 //*----------------------------------------------------------------------------
2534 static inline void AT91F_TWI_EnableIt (
2535         AT91PS_TWI pTWI, // \arg pointer to a TWI controller
2536         unsigned int flag)   // \arg IT to be enabled
2537 {
2538         //* Write to the IER register
2539         pTWI->TWI_IER = flag;
2540 }
2541
2542 //*----------------------------------------------------------------------------
2543 //* \fn    AT91F_TWI_DisableIt
2544 //* \brief Disable TWI IT
2545 //*----------------------------------------------------------------------------
2546 static inline void AT91F_TWI_DisableIt (
2547         AT91PS_TWI pTWI, // \arg pointer to a TWI controller
2548         unsigned int flag)   // \arg IT to be disabled
2549 {
2550         //* Write to the IDR register
2551         pTWI->TWI_IDR = flag;
2552 }
2553
2554 //*----------------------------------------------------------------------------
2555 //* \fn    AT91F_TWI_Configure
2556 //* \brief Configure TWI in master mode
2557 //*----------------------------------------------------------------------------
2558 static inline void AT91F_TWI_Configure ( AT91PS_TWI pTWI )          // \arg pointer to a TWI controller
2559 {
2560     //* Disable interrupts
2561         pTWI->TWI_IDR = (unsigned int) -1;
2562
2563     //* Reset peripheral
2564         pTWI->TWI_CR = AT91C_TWI_SWRST;
2565
2566         //* Set Master mode
2567         pTWI->TWI_CR = AT91C_TWI_MSEN;
2568
2569 }
2570
2571 //*----------------------------------------------------------------------------
2572 //* \fn    AT91F_TWI_GetInterruptMaskStatus
2573 //* \brief Return TWI Interrupt Mask Status
2574 //*----------------------------------------------------------------------------
2575 static inline unsigned int AT91F_TWI_GetInterruptMaskStatus( // \return TWI Interrupt Mask Status
2576         AT91PS_TWI pTwi) // \arg  pointer to a TWI controller
2577 {
2578         return pTwi->TWI_IMR;
2579 }
2580
2581 //*----------------------------------------------------------------------------
2582 //* \fn    AT91F_TWI_IsInterruptMasked
2583 //* \brief Test if TWI Interrupt is Masked
2584 //*----------------------------------------------------------------------------
2585 static inline int AT91F_TWI_IsInterruptMasked(
2586         AT91PS_TWI pTwi,   // \arg  pointer to a TWI controller
2587         unsigned int flag) // \arg  flag to be tested
2588 {
2589         return (AT91F_TWI_GetInterruptMaskStatus(pTwi) & flag);
2590 }
2591
2592 /* *****************************************************************************
2593                 SOFTWARE API FOR TC
2594    ***************************************************************************** */
2595 //*----------------------------------------------------------------------------
2596 //* \fn    AT91F_TC_InterruptEnable
2597 //* \brief Enable TC Interrupt
2598 //*----------------------------------------------------------------------------
2599 static inline void AT91F_TC_InterruptEnable(
2600         AT91PS_TC pTc,   // \arg  pointer to a TC controller
2601         unsigned int flag) // \arg  TC interrupt to be enabled
2602 {
2603         pTc->TC_IER = flag;
2604 }
2605
2606 //*----------------------------------------------------------------------------
2607 //* \fn    AT91F_TC_InterruptDisable
2608 //* \brief Disable TC Interrupt
2609 //*----------------------------------------------------------------------------
2610 static inline void AT91F_TC_InterruptDisable(
2611         AT91PS_TC pTc,   // \arg  pointer to a TC controller
2612         unsigned int flag) // \arg  TC interrupt to be disabled
2613 {
2614         pTc->TC_IDR = flag;
2615 }
2616
2617 //*----------------------------------------------------------------------------
2618 //* \fn    AT91F_TC_GetInterruptMaskStatus
2619 //* \brief Return TC Interrupt Mask Status
2620 //*----------------------------------------------------------------------------
2621 static inline unsigned int AT91F_TC_GetInterruptMaskStatus( // \return TC Interrupt Mask Status
2622         AT91PS_TC pTc) // \arg  pointer to a TC controller
2623 {
2624         return pTc->TC_IMR;
2625 }
2626
2627 //*----------------------------------------------------------------------------
2628 //* \fn    AT91F_TC_IsInterruptMasked
2629 //* \brief Test if TC Interrupt is Masked
2630 //*----------------------------------------------------------------------------
2631 static inline int AT91F_TC_IsInterruptMasked(
2632         AT91PS_TC pTc,   // \arg  pointer to a TC controller
2633         unsigned int flag) // \arg  flag to be tested
2634 {
2635         return (AT91F_TC_GetInterruptMaskStatus(pTc) & flag);
2636 }
2637
2638 /* *****************************************************************************
2639                 SOFTWARE API FOR PWMC
2640    ***************************************************************************** */
2641 //*----------------------------------------------------------------------------
2642 //* \fn    AT91F_PWM_GetStatus
2643 //* \brief Return PWM Interrupt Status
2644 //*----------------------------------------------------------------------------
2645 static inline unsigned int AT91F_PWMC_GetStatus( // \return PWM Interrupt Status
2646         AT91PS_PWMC pPWM) // pointer to a PWM controller
2647 {
2648         return pPWM->PWMC_SR;
2649 }
2650
2651 //*----------------------------------------------------------------------------
2652 //* \fn    AT91F_PWM_InterruptEnable
2653 //* \brief Enable PWM Interrupt
2654 //*----------------------------------------------------------------------------
2655 static inline void AT91F_PWMC_InterruptEnable(
2656         AT91PS_PWMC pPwm,   // \arg  pointer to a PWM controller
2657         unsigned int flag) // \arg  PWM interrupt to be enabled
2658 {
2659         pPwm->PWMC_IER = flag;
2660 }
2661
2662 //*----------------------------------------------------------------------------
2663 //* \fn    AT91F_PWM_InterruptDisable
2664 //* \brief Disable PWM Interrupt
2665 //*----------------------------------------------------------------------------
2666 static inline void AT91F_PWMC_InterruptDisable(
2667         AT91PS_PWMC pPwm,   // \arg  pointer to a PWM controller
2668         unsigned int flag) // \arg  PWM interrupt to be disabled
2669 {
2670         pPwm->PWMC_IDR = flag;
2671 }
2672
2673 //*----------------------------------------------------------------------------
2674 //* \fn    AT91F_PWM_GetInterruptMaskStatus
2675 //* \brief Return PWM Interrupt Mask Status
2676 //*----------------------------------------------------------------------------
2677 static inline unsigned int AT91F_PWMC_GetInterruptMaskStatus( // \return PWM Interrupt Mask Status
2678         AT91PS_PWMC pPwm) // \arg  pointer to a PWM controller
2679 {
2680         return pPwm->PWMC_IMR;
2681 }
2682
2683 //*----------------------------------------------------------------------------
2684 //* \fn    AT91F_PWM_IsInterruptMasked
2685 //* \brief Test if PWM Interrupt is Masked
2686 //*----------------------------------------------------------------------------
2687 static inline unsigned int AT91F_PWMC_IsInterruptMasked(
2688         AT91PS_PWMC pPWM,   // \arg  pointer to a PWM controller
2689         unsigned int flag) // \arg  flag to be tested
2690 {
2691         return (AT91F_PWMC_GetInterruptMaskStatus(pPWM) & flag);
2692 }
2693
2694 //*----------------------------------------------------------------------------
2695 //* \fn    AT91F_PWM_IsStatusSet
2696 //* \brief Test if PWM Interrupt is Set
2697 //*----------------------------------------------------------------------------
2698 static inline unsigned int AT91F_PWMC_IsStatusSet(
2699         AT91PS_PWMC pPWM,   // \arg  pointer to a PWM controller
2700         unsigned int flag) // \arg  flag to be tested
2701 {
2702         return (AT91F_PWMC_GetStatus(pPWM) & flag);
2703 }
2704
2705 //*----------------------------------------------------------------------------
2706 //* \fn    AT91F_PWM_CfgChannel
2707 //* \brief Test if PWM Interrupt is Set
2708 //*----------------------------------------------------------------------------
2709 static inline void AT91F_PWMC_CfgChannel(
2710         AT91PS_PWMC pPWM,   // \arg  pointer to a PWM controller
2711         unsigned int channelId, // \arg PWM channel ID
2712         unsigned int mode, // \arg  PWM mode
2713         unsigned int period, // \arg PWM period
2714         unsigned int duty) // \arg PWM duty cycle
2715 {
2716         pPWM->PWMC_CH[channelId].PWMC_CMR = mode;
2717         pPWM->PWMC_CH[channelId].PWMC_CDTYR = duty;
2718         pPWM->PWMC_CH[channelId].PWMC_CPRDR = period;
2719 }
2720
2721 //*----------------------------------------------------------------------------
2722 //* \fn    AT91F_PWM_StartChannel
2723 //* \brief Enable channel
2724 //*----------------------------------------------------------------------------
2725 static inline void AT91F_PWMC_StartChannel(
2726         AT91PS_PWMC pPWM,   // \arg  pointer to a PWM controller
2727         unsigned int flag) // \arg  Channels IDs to be enabled
2728 {
2729         pPWM->PWMC_ENA = flag;
2730 }
2731
2732 //*----------------------------------------------------------------------------
2733 //* \fn    AT91F_PWM_StopChannel
2734 //* \brief Disable channel
2735 //*----------------------------------------------------------------------------
2736 static inline void AT91F_PWMC_StopChannel(
2737         AT91PS_PWMC pPWM,   // \arg  pointer to a PWM controller
2738         unsigned int flag) // \arg  Channels IDs to be enabled
2739 {
2740         pPWM->PWMC_DIS = flag;
2741 }
2742
2743 //*----------------------------------------------------------------------------
2744 //* \fn    AT91F_PWM_UpdateChannel
2745 //* \brief Update Period or Duty Cycle
2746 //*----------------------------------------------------------------------------
2747 static inline void AT91F_PWMC_UpdateChannel(
2748         AT91PS_PWMC pPWM,   // \arg  pointer to a PWM controller
2749         unsigned int channelId, // \arg PWM channel ID
2750         unsigned int update) // \arg  Channels IDs to be enabled
2751 {
2752         pPWM->PWMC_CH[channelId].PWMC_CUPDR = update;
2753 }
2754
2755 /* *****************************************************************************
2756                 SOFTWARE API FOR UDP
2757    ***************************************************************************** */
2758 //*----------------------------------------------------------------------------
2759 //* \fn    AT91F_UDP_EnableIt
2760 //* \brief Enable UDP IT
2761 //*----------------------------------------------------------------------------
2762 static inline void AT91F_UDP_EnableIt (
2763         AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
2764         unsigned int flag)   // \arg IT to be enabled
2765 {
2766         //* Write to the IER register
2767         pUDP->UDP_IER = flag;
2768 }
2769
2770 //*----------------------------------------------------------------------------
2771 //* \fn    AT91F_UDP_DisableIt
2772 //* \brief Disable UDP IT
2773 //*----------------------------------------------------------------------------
2774 static inline void AT91F_UDP_DisableIt (
2775         AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
2776         unsigned int flag)   // \arg IT to be disabled
2777 {
2778         //* Write to the IDR register
2779         pUDP->UDP_IDR = flag;
2780 }
2781
2782 //*----------------------------------------------------------------------------
2783 //* \fn    AT91F_UDP_SetAddress
2784 //* \brief Set UDP functional address
2785 //*----------------------------------------------------------------------------
2786 static inline void AT91F_UDP_SetAddress (
2787         AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
2788         unsigned char address)   // \arg new UDP address
2789 {
2790         pUDP->UDP_FADDR = (AT91C_UDP_FEN | address);
2791 }
2792
2793 //*----------------------------------------------------------------------------
2794 //* \fn    AT91F_UDP_EnableEp
2795 //* \brief Enable Endpoint
2796 //*----------------------------------------------------------------------------
2797 static inline void AT91F_UDP_EnableEp (
2798         AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
2799         unsigned char endpoint)   // \arg endpoint number
2800 {
2801         pUDP->UDP_CSR[endpoint] |= AT91C_UDP_EPEDS;
2802 }
2803
2804 //*----------------------------------------------------------------------------
2805 //* \fn    AT91F_UDP_DisableEp
2806 //* \brief Enable Endpoint
2807 //*----------------------------------------------------------------------------
2808 static inline void AT91F_UDP_DisableEp (
2809         AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
2810         unsigned char endpoint)   // \arg endpoint number
2811 {
2812         pUDP->UDP_CSR[endpoint] &= ~AT91C_UDP_EPEDS;
2813 }
2814
2815 //*----------------------------------------------------------------------------
2816 //* \fn    AT91F_UDP_SetState
2817 //* \brief Set UDP Device state
2818 //*----------------------------------------------------------------------------
2819 static inline void AT91F_UDP_SetState (
2820         AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
2821         unsigned int flag)   // \arg new UDP address
2822 {
2823         pUDP->UDP_GLBSTATE  &= ~(AT91C_UDP_FADDEN | AT91C_UDP_CONFG);
2824         pUDP->UDP_GLBSTATE  |= flag;
2825 }
2826
2827 //*----------------------------------------------------------------------------
2828 //* \fn    AT91F_UDP_GetState
2829 //* \brief return UDP Device state
2830 //*----------------------------------------------------------------------------
2831 static inline unsigned int AT91F_UDP_GetState ( // \return the UDP device state
2832         AT91PS_UDP pUDP)     // \arg pointer to a UDP controller
2833 {
2834         return (pUDP->UDP_GLBSTATE  & (AT91C_UDP_FADDEN | AT91C_UDP_CONFG));
2835 }
2836
2837 //*----------------------------------------------------------------------------
2838 //* \fn    AT91F_UDP_ResetEp
2839 //* \brief Reset UDP endpoint
2840 //*----------------------------------------------------------------------------
2841 static inline void AT91F_UDP_ResetEp ( // \return the UDP device state
2842         AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
2843         unsigned int flag)   // \arg Endpoints to be reset
2844 {
2845         pUDP->UDP_RSTEP = flag;
2846         pUDP->UDP_RSTEP = 0;
2847 }
2848
2849 //*----------------------------------------------------------------------------
2850 //* \fn    AT91F_UDP_EpStall
2851 //* \brief Endpoint will STALL requests
2852 //*----------------------------------------------------------------------------
2853 static inline void AT91F_UDP_EpStall(
2854         AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
2855         unsigned char endpoint)   // \arg endpoint number
2856 {
2857         pUDP->UDP_CSR[endpoint] |= AT91C_UDP_FORCESTALL;
2858 }
2859
2860 //*----------------------------------------------------------------------------
2861 //* \fn    AT91F_UDP_EpWrite
2862 //* \brief Write value in the DPR
2863 //*----------------------------------------------------------------------------
2864 static inline void AT91F_UDP_EpWrite(
2865         AT91PS_UDP pUDP,         // \arg pointer to a UDP controller
2866         unsigned char endpoint,  // \arg endpoint number
2867         unsigned char value)     // \arg value to be written in the DPR
2868 {
2869         pUDP->UDP_FDR[endpoint] = value;
2870 }
2871
2872 //*----------------------------------------------------------------------------
2873 //* \fn    AT91F_UDP_EpRead
2874 //* \brief Return value from the DPR
2875 //*----------------------------------------------------------------------------
2876 static inline unsigned int AT91F_UDP_EpRead(
2877         AT91PS_UDP pUDP,         // \arg pointer to a UDP controller
2878         unsigned char endpoint)  // \arg endpoint number
2879 {
2880         return pUDP->UDP_FDR[endpoint];
2881 }
2882
2883 //*----------------------------------------------------------------------------
2884 //* \fn    AT91F_UDP_EpEndOfWr
2885 //* \brief Notify the UDP that values in DPR are ready to be sent
2886 //*----------------------------------------------------------------------------
2887 static inline void AT91F_UDP_EpEndOfWr(
2888         AT91PS_UDP pUDP,         // \arg pointer to a UDP controller
2889         unsigned char endpoint)  // \arg endpoint number
2890 {
2891         pUDP->UDP_CSR[endpoint] |= AT91C_UDP_TXPKTRDY;
2892 }
2893
2894 //*----------------------------------------------------------------------------
2895 //* \fn    AT91F_UDP_EpClear
2896 //* \brief Clear flag in the endpoint CSR register
2897 //*----------------------------------------------------------------------------
2898 static inline void AT91F_UDP_EpClear(
2899         AT91PS_UDP pUDP,         // \arg pointer to a UDP controller
2900         unsigned char endpoint,  // \arg endpoint number
2901         unsigned int flag)       // \arg flag to be cleared
2902 {
2903         pUDP->UDP_CSR[endpoint] &= ~(flag);
2904 }
2905
2906 //*----------------------------------------------------------------------------
2907 //* \fn    AT91F_UDP_EpSet
2908 //* \brief Set flag in the endpoint CSR register
2909 //*----------------------------------------------------------------------------
2910 static inline void AT91F_UDP_EpSet(
2911         AT91PS_UDP pUDP,         // \arg pointer to a UDP controller
2912         unsigned char endpoint,  // \arg endpoint number
2913         unsigned int flag)       // \arg flag to be cleared
2914 {
2915         pUDP->UDP_CSR[endpoint] |= flag;
2916 }
2917
2918 //*----------------------------------------------------------------------------
2919 //* \fn    AT91F_UDP_EpStatus
2920 //* \brief Return the endpoint CSR register
2921 //*----------------------------------------------------------------------------
2922 static inline unsigned int AT91F_UDP_EpStatus(
2923         AT91PS_UDP pUDP,         // \arg pointer to a UDP controller
2924         unsigned char endpoint)  // \arg endpoint number
2925 {
2926         return pUDP->UDP_CSR[endpoint];
2927 }
2928
2929 //*----------------------------------------------------------------------------
2930 //* \fn    AT91F_UDP_GetInterruptMaskStatus
2931 //* \brief Return UDP Interrupt Mask Status
2932 //*----------------------------------------------------------------------------
2933 static inline unsigned int AT91F_UDP_GetInterruptMaskStatus(
2934   AT91PS_UDP pUdp)        // \arg  pointer to a UDP controller
2935 {
2936   return pUdp->UDP_IMR;
2937 }
2938
2939 //*----------------------------------------------------------------------------
2940 //* \fn    AT91F_UDP_IsInterruptMasked
2941 //* \brief Test if UDP Interrupt is Masked
2942 //*----------------------------------------------------------------------------
2943 static inline int AT91F_UDP_IsInterruptMasked(
2944   AT91PS_UDP pUdp,       // \arg  pointer to a UDP controller
2945   unsigned int flag)     // \arg  flag to be tested
2946 {
2947   return (AT91F_UDP_GetInterruptMaskStatus(pUdp) & flag);
2948 }
2949
2950 // ----------------------------------------------------------------------------
2951 //  \fn    AT91F_UDP_InterruptStatusRegister
2952 //  \brief Return the Interrupt Status Register
2953 // ----------------------------------------------------------------------------
2954 static inline unsigned int AT91F_UDP_InterruptStatusRegister(
2955   AT91PS_UDP pUDP )      // \arg  pointer to a UDP controller
2956 {
2957   return pUDP->UDP_ISR;
2958 }
2959
2960 // ----------------------------------------------------------------------------
2961 //  \fn    AT91F_UDP_InterruptClearRegister
2962 //  \brief Clear Interrupt Register
2963 // ----------------------------------------------------------------------------
2964 static inline void AT91F_UDP_InterruptClearRegister (
2965   AT91PS_UDP pUDP,       // \arg pointer to UDP controller
2966   unsigned int flag)     // \arg IT to be cleat
2967 {
2968   pUDP->UDP_ICR = flag;
2969 }
2970
2971 // ----------------------------------------------------------------------------
2972 //  \fn    AT91F_UDP_EnableTransceiver
2973 //  \brief Enable transceiver
2974 // ----------------------------------------------------------------------------
2975 static inline void AT91F_UDP_EnableTransceiver(
2976   AT91PS_UDP pUDP )      // \arg  pointer to a UDP controller
2977 {
2978     pUDP->UDP_TXVC &= ~AT91C_UDP_TXVDIS;
2979 }
2980
2981 // ----------------------------------------------------------------------------
2982 //  \fn    AT91F_UDP_DisableTransceiver
2983 //  \brief Disable transceiver
2984 // ----------------------------------------------------------------------------
2985 static inline void AT91F_UDP_DisableTransceiver(
2986   AT91PS_UDP pUDP )      // \arg  pointer to a UDP controller
2987 {
2988     pUDP->UDP_TXVC = AT91C_UDP_TXVDIS;
2989 }
2990
2991 //*----------------------------------------------------------------------------
2992 //* \fn    AT91F_DBGU_CfgPMC
2993 //* \brief Enable Peripheral clock in PMC for  DBGU
2994 //*----------------------------------------------------------------------------
2995 static inline void AT91F_DBGU_CfgPMC (void)
2996 {
2997         AT91F_PMC_EnablePeriphClock(
2998                 AT91C_BASE_PMC, // PIO controller base address
2999                 ((unsigned int) 1 << AT91C_ID_SYS));
3000 }
3001
3002 //*----------------------------------------------------------------------------
3003 //* \fn    AT91F_DBGU_CfgPIO
3004 //* \brief Configure PIO controllers to drive DBGU signals
3005 //*----------------------------------------------------------------------------
3006 static inline void AT91F_DBGU_CfgPIO (void)
3007 {
3008         // Configure PIO controllers to periph mode
3009         AT91F_PIO_CfgPeriph(
3010                 AT91C_BASE_PIOA, // PIO controller base address
3011                 ((unsigned int) AT91C_PA9_DRXD    ) |
3012                 ((unsigned int) AT91C_PA10_DTXD    ), // Peripheral A
3013                 0); // Peripheral B
3014 }
3015
3016 //*----------------------------------------------------------------------------
3017 //* \fn    AT91F_PMC_CfgPMC
3018 //* \brief Enable Peripheral clock in PMC for  PMC
3019 //*----------------------------------------------------------------------------
3020 static inline void AT91F_PMC_CfgPMC (void)
3021 {
3022         AT91F_PMC_EnablePeriphClock(
3023                 AT91C_BASE_PMC, // PIO controller base address
3024                 ((unsigned int) 1 << AT91C_ID_SYS));
3025 }
3026
3027 //*----------------------------------------------------------------------------
3028 //* \fn    AT91F_PMC_CfgPIO
3029 //* \brief Configure PIO controllers to drive PMC signals
3030 //*----------------------------------------------------------------------------
3031 static inline void AT91F_PMC_CfgPIO (void)
3032 {
3033         // Configure PIO controllers to periph mode
3034         AT91F_PIO_CfgPeriph(
3035                 AT91C_BASE_PIOA, // PIO controller base address
3036                 0, // Peripheral A
3037                 ((unsigned int) AT91C_PA6_PCK0    ) |
3038                 ((unsigned int) AT91C_PA18_PCK2    ) |
3039                 ((unsigned int) AT91C_PA31_PCK2    ) |
3040                 ((unsigned int) AT91C_PA21_PCK1    ) |
3041                 ((unsigned int) AT91C_PA17_PCK1    )); // Peripheral B
3042 }
3043
3044 //*----------------------------------------------------------------------------
3045 //* \fn    AT91F_VREG_CfgPMC
3046 //* \brief Enable Peripheral clock in PMC for  VREG
3047 //*----------------------------------------------------------------------------
3048 static inline void AT91F_VREG_CfgPMC (void)
3049 {
3050         AT91F_PMC_EnablePeriphClock(
3051                 AT91C_BASE_PMC, // PIO controller base address
3052                 ((unsigned int) 1 << AT91C_ID_SYS));
3053 }
3054
3055 //*----------------------------------------------------------------------------
3056 //* \fn    AT91F_RSTC_CfgPMC
3057 //* \brief Enable Peripheral clock in PMC for  RSTC
3058 //*----------------------------------------------------------------------------
3059 static inline void AT91F_RSTC_CfgPMC (void)
3060 {
3061         AT91F_PMC_EnablePeriphClock(
3062                 AT91C_BASE_PMC, // PIO controller base address
3063                 ((unsigned int) 1 << AT91C_ID_SYS));
3064 }
3065
3066 //*----------------------------------------------------------------------------
3067 //* \fn    AT91F_SSC_CfgPMC
3068 //* \brief Enable Peripheral clock in PMC for  SSC
3069 //*----------------------------------------------------------------------------
3070 static inline void AT91F_SSC_CfgPMC (void)
3071 {
3072         AT91F_PMC_EnablePeriphClock(
3073                 AT91C_BASE_PMC, // PIO controller base address
3074                 ((unsigned int) 1 << AT91C_ID_SSC));
3075 }
3076
3077 //*----------------------------------------------------------------------------
3078 //* \fn    AT91F_SSC_CfgPIO
3079 //* \brief Configure PIO controllers to drive SSC signals
3080 //*----------------------------------------------------------------------------
3081 static inline void AT91F_SSC_CfgPIO (void)
3082 {
3083         // Configure PIO controllers to periph mode
3084         AT91F_PIO_CfgPeriph(
3085                 AT91C_BASE_PIOA, // PIO controller base address
3086                 ((unsigned int) AT91C_PA19_RK      ) |
3087                 ((unsigned int) AT91C_PA16_TK      ) |
3088                 ((unsigned int) AT91C_PA15_TF      ) |
3089                 ((unsigned int) AT91C_PA18_RD      ) |
3090                 ((unsigned int) AT91C_PA20_RF      ) |
3091                 ((unsigned int) AT91C_PA17_TD      ), // Peripheral A
3092                 0); // Peripheral B
3093 }
3094
3095 //*----------------------------------------------------------------------------
3096 //* \fn    AT91F_WDTC_CfgPMC
3097 //* \brief Enable Peripheral clock in PMC for  WDTC
3098 //*----------------------------------------------------------------------------
3099 static inline void AT91F_WDTC_CfgPMC (void)
3100 {
3101         AT91F_PMC_EnablePeriphClock(
3102                 AT91C_BASE_PMC, // PIO controller base address
3103                 ((unsigned int) 1 << AT91C_ID_SYS));
3104 }
3105
3106 //*----------------------------------------------------------------------------
3107 //* \fn    AT91F_US1_CfgPMC
3108 //* \brief Enable Peripheral clock in PMC for  US1
3109 //*----------------------------------------------------------------------------
3110 static inline void AT91F_US1_CfgPMC (void)
3111 {
3112         AT91F_PMC_EnablePeriphClock(
3113                 AT91C_BASE_PMC, // PIO controller base address
3114                 ((unsigned int) 1 << AT91C_ID_US1));
3115 }
3116
3117 //*----------------------------------------------------------------------------
3118 //* \fn    AT91F_US1_CfgPIO
3119 //* \brief Configure PIO controllers to drive US1 signals
3120 //*----------------------------------------------------------------------------
3121 static inline void AT91F_US1_CfgPIO (void)
3122 {
3123         // Configure PIO controllers to periph mode
3124         AT91F_PIO_CfgPeriph(
3125                 AT91C_BASE_PIOA, // PIO controller base address
3126                 ((unsigned int) AT91C_PA29_RI1     ) |
3127                 ((unsigned int) AT91C_PA26_DCD1    ) |
3128                 ((unsigned int) AT91C_PA28_DSR1    ) |
3129                 ((unsigned int) AT91C_PA27_DTR1    ) |
3130                 ((unsigned int) AT91C_PA23_SCK1    ) |
3131                 ((unsigned int) AT91C_PA24_RTS1    ) |
3132                 ((unsigned int) AT91C_PA22_TXD1    ) |
3133                 ((unsigned int) AT91C_PA21_RXD1    ) |
3134                 ((unsigned int) AT91C_PA25_CTS1    ), // Peripheral A
3135                 0); // Peripheral B
3136 }
3137
3138 //*----------------------------------------------------------------------------
3139 //* \fn    AT91F_US0_CfgPMC
3140 //* \brief Enable Peripheral clock in PMC for  US0
3141 //*----------------------------------------------------------------------------
3142 static inline void AT91F_US0_CfgPMC (void)
3143 {
3144         AT91F_PMC_EnablePeriphClock(
3145                 AT91C_BASE_PMC, // PIO controller base address
3146                 ((unsigned int) 1 << AT91C_ID_US0));
3147 }
3148
3149 //*----------------------------------------------------------------------------
3150 //* \fn    AT91F_US0_CfgPIO
3151 //* \brief Configure PIO controllers to drive US0 signals
3152 //*----------------------------------------------------------------------------
3153 static inline void AT91F_US0_CfgPIO (void)
3154 {
3155         // Configure PIO controllers to periph mode
3156         AT91F_PIO_CfgPeriph(
3157                 AT91C_BASE_PIOA, // PIO controller base address
3158                 ((unsigned int) AT91C_PA5_RXD0    ) |
3159                 ((unsigned int) AT91C_PA8_CTS0    ) |
3160                 ((unsigned int) AT91C_PA7_RTS0    ) |
3161                 ((unsigned int) AT91C_PA6_TXD0    ), // Peripheral A
3162                 ((unsigned int) AT91C_PA2_SCK0    )); // Peripheral B
3163 }
3164
3165 //*----------------------------------------------------------------------------
3166 //* \fn    AT91F_SPI_CfgPMC
3167 //* \brief Enable Peripheral clock in PMC for  SPI
3168 //*----------------------------------------------------------------------------
3169 static inline void AT91F_SPI_CfgPMC (void)
3170 {
3171         AT91F_PMC_EnablePeriphClock(
3172                 AT91C_BASE_PMC, // PIO controller base address
3173                 ((unsigned int) 1 << AT91C_ID_SPI));
3174 }
3175
3176 //*----------------------------------------------------------------------------
3177 //* \fn    AT91F_SPI_CfgPIO
3178 //* \brief Configure PIO controllers to drive SPI signals
3179 //*----------------------------------------------------------------------------
3180 static inline void AT91F_SPI_CfgPIO (void)
3181 {
3182         // Configure PIO controllers to periph mode
3183         AT91F_PIO_CfgPeriph(
3184                 AT91C_BASE_PIOA, // PIO controller base address
3185                 ((unsigned int) AT91C_PA13_MOSI    ) |
3186                 ((unsigned int) AT91C_PA31_NPCS1   ) |
3187                 ((unsigned int) AT91C_PA14_SPCK    ) |
3188                 ((unsigned int) AT91C_PA11_NPCS0   ) |
3189                 ((unsigned int) AT91C_PA12_MISO    ), // Peripheral A
3190                 ((unsigned int) AT91C_PA9_NPCS1   ) |
3191                 ((unsigned int) AT91C_PA22_NPCS3   ) |
3192                 ((unsigned int) AT91C_PA3_NPCS3   ) |
3193                 ((unsigned int) AT91C_PA5_NPCS3   ) |
3194                 ((unsigned int) AT91C_PA10_NPCS2   ) |
3195                 ((unsigned int) AT91C_PA30_NPCS2   )); // Peripheral B
3196 }
3197
3198 //*----------------------------------------------------------------------------
3199 //* \fn    AT91F_PITC_CfgPMC
3200 //* \brief Enable Peripheral clock in PMC for  PITC
3201 //*----------------------------------------------------------------------------
3202 static inline void AT91F_PITC_CfgPMC (void)
3203 {
3204         AT91F_PMC_EnablePeriphClock(
3205                 AT91C_BASE_PMC, // PIO controller base address
3206                 ((unsigned int) 1 << AT91C_ID_SYS));
3207 }
3208
3209 //*----------------------------------------------------------------------------
3210 //* \fn    AT91F_AIC_CfgPMC
3211 //* \brief Enable Peripheral clock in PMC for  AIC
3212 //*----------------------------------------------------------------------------
3213 static inline void AT91F_AIC_CfgPMC (void)
3214 {
3215         AT91F_PMC_EnablePeriphClock(
3216                 AT91C_BASE_PMC, // PIO controller base address
3217                 ((unsigned int) 1 << AT91C_ID_FIQ) |
3218                 ((unsigned int) 1 << AT91C_ID_IRQ0) |
3219                 ((unsigned int) 1 << AT91C_ID_IRQ1));
3220 }
3221
3222 //*----------------------------------------------------------------------------
3223 //* \fn    AT91F_AIC_CfgPIO
3224 //* \brief Configure PIO controllers to drive AIC signals
3225 //*----------------------------------------------------------------------------
3226 static inline void AT91F_AIC_CfgPIO (void)
3227 {
3228         // Configure PIO controllers to periph mode
3229         AT91F_PIO_CfgPeriph(
3230                 AT91C_BASE_PIOA, // PIO controller base address
3231                 ((unsigned int) AT91C_PA30_IRQ1    ), // Peripheral A
3232                 ((unsigned int) AT91C_PA20_IRQ0    ) |
3233                 ((unsigned int) AT91C_PA19_FIQ     )); // Peripheral B
3234 }
3235
3236 //*----------------------------------------------------------------------------
3237 //* \fn    AT91F_TWI_CfgPMC
3238 //* \brief Enable Peripheral clock in PMC for  TWI
3239 //*----------------------------------------------------------------------------
3240 static inline void AT91F_TWI_CfgPMC (void)
3241 {
3242         AT91F_PMC_EnablePeriphClock(
3243                 AT91C_BASE_PMC, // PIO controller base address
3244                 ((unsigned int) 1 << AT91C_ID_TWI));
3245 }
3246
3247 //*----------------------------------------------------------------------------
3248 //* \fn    AT91F_TWI_CfgPIO
3249 //* \brief Configure PIO controllers to drive TWI signals
3250 //*----------------------------------------------------------------------------
3251 static inline void AT91F_TWI_CfgPIO (void)
3252 {
3253         // Configure PIO controllers to periph mode
3254         AT91F_PIO_CfgPeriph(
3255                 AT91C_BASE_PIOA, // PIO controller base address
3256                 ((unsigned int) AT91C_PA4_TWCK    ) |
3257                 ((unsigned int) AT91C_PA3_TWD     ), // Peripheral A
3258                 0); // Peripheral B
3259 }
3260
3261 //*----------------------------------------------------------------------------
3262 //* \fn    AT91F_PWMC_CH3_CfgPIO
3263 //* \brief Configure PIO controllers to drive PWMC_CH3 signals
3264 //*----------------------------------------------------------------------------
3265 static inline void AT91F_PWMC_CH3_CfgPIO (void)
3266 {
3267         // Configure PIO controllers to periph mode
3268         AT91F_PIO_CfgPeriph(
3269                 AT91C_BASE_PIOA, // PIO controller base address
3270                 0, // Peripheral A
3271                 ((unsigned int) AT91C_PA7_PWM3    ) |
3272                 ((unsigned int) AT91C_PA14_PWM3    )); // Peripheral B
3273 }
3274
3275 //*----------------------------------------------------------------------------
3276 //* \fn    AT91F_PWMC_CH2_CfgPIO
3277 //* \brief Configure PIO controllers to drive PWMC_CH2 signals
3278 //*----------------------------------------------------------------------------
3279 static inline void AT91F_PWMC_CH2_CfgPIO (void)
3280 {
3281         // Configure PIO controllers to periph mode
3282         AT91F_PIO_CfgPeriph(
3283                 AT91C_BASE_PIOA, // PIO controller base address
3284                 ((unsigned int) AT91C_PA2_PWM2    ), // Peripheral A
3285                 ((unsigned int) AT91C_PA13_PWM2    ) |
3286                 ((unsigned int) AT91C_PA25_PWM2    )); // Peripheral B
3287 }
3288
3289 //*----------------------------------------------------------------------------
3290 //* \fn    AT91F_PWMC_CH1_CfgPIO
3291 //* \brief Configure PIO controllers to drive PWMC_CH1 signals
3292 //*----------------------------------------------------------------------------
3293 static inline void AT91F_PWMC_CH1_CfgPIO (void)
3294 {
3295         // Configure PIO controllers to periph mode
3296         AT91F_PIO_CfgPeriph(
3297                 AT91C_BASE_PIOA, // PIO controller base address
3298                 ((unsigned int) AT91C_PA1_PWM1    ), // Peripheral A
3299                 ((unsigned int) AT91C_PA24_PWM1    ) |
3300                 ((unsigned int) AT91C_PA12_PWM1    )); // Peripheral B
3301 }
3302
3303 //*----------------------------------------------------------------------------
3304 //* \fn    AT91F_PWMC_CH0_CfgPIO
3305 //* \brief Configure PIO controllers to drive PWMC_CH0 signals
3306 //*----------------------------------------------------------------------------
3307 static inline void AT91F_PWMC_CH0_CfgPIO (void)
3308 {
3309         // Configure PIO controllers to periph mode
3310         AT91F_PIO_CfgPeriph(
3311                 AT91C_BASE_PIOA, // PIO controller base address
3312                 ((unsigned int) AT91C_PA0_PWM0    ), // Peripheral A
3313                 ((unsigned int) AT91C_PA23_PWM0    ) |
3314                 ((unsigned int) AT91C_PA11_PWM0    )); // Peripheral B
3315 }
3316
3317 //*----------------------------------------------------------------------------
3318 //* \fn    AT91F_ADC_CfgPMC
3319 //* \brief Enable Peripheral clock in PMC for  ADC
3320 //*----------------------------------------------------------------------------
3321 static inline void AT91F_ADC_CfgPMC (void)
3322 {
3323         AT91F_PMC_EnablePeriphClock(
3324                 AT91C_BASE_PMC, // PIO controller base address
3325                 ((unsigned int) 1 << AT91C_ID_ADC));
3326 }
3327
3328 //*----------------------------------------------------------------------------
3329 //* \fn    AT91F_ADC_CfgPIO
3330 //* \brief Configure PIO controllers to drive ADC signals
3331 //*----------------------------------------------------------------------------
3332 static inline void AT91F_ADC_CfgPIO (void)
3333 {
3334         // Configure PIO controllers to periph mode
3335         AT91F_PIO_CfgPeriph(
3336                 AT91C_BASE_PIOA, // PIO controller base address
3337                 0, // Peripheral A
3338                 ((unsigned int) AT91C_PA8_ADTRG   )); // Peripheral B
3339 }
3340
3341 //*----------------------------------------------------------------------------
3342 //* \fn    AT91F_RTTC_CfgPMC
3343 //* \brief Enable Peripheral clock in PMC for  RTTC
3344 //*----------------------------------------------------------------------------
3345 static inline void AT91F_RTTC_CfgPMC (void)
3346 {
3347         AT91F_PMC_EnablePeriphClock(
3348                 AT91C_BASE_PMC, // PIO controller base address
3349                 ((unsigned int) 1 << AT91C_ID_SYS));
3350 }
3351
3352 //*----------------------------------------------------------------------------
3353 //* \fn    AT91F_UDP_CfgPMC
3354 //* \brief Enable Peripheral clock in PMC for  UDP
3355 //*----------------------------------------------------------------------------
3356 static inline void AT91F_UDP_CfgPMC (void)
3357 {
3358         AT91F_PMC_EnablePeriphClock(
3359                 AT91C_BASE_PMC, // PIO controller base address
3360                 ((unsigned int) 1 << AT91C_ID_UDP));
3361 }
3362
3363 //*----------------------------------------------------------------------------
3364 //* \fn    AT91F_TC0_CfgPMC
3365 //* \brief Enable Peripheral clock in PMC for  TC0
3366 //*----------------------------------------------------------------------------
3367 static inline void AT91F_TC0_CfgPMC (void)
3368 {
3369         AT91F_PMC_EnablePeriphClock(
3370                 AT91C_BASE_PMC, // PIO controller base address
3371                 ((unsigned int) 1 << AT91C_ID_TC0));
3372 }
3373
3374 //*----------------------------------------------------------------------------
3375 //* \fn    AT91F_TC0_CfgPIO
3376 //* \brief Configure PIO controllers to drive TC0 signals
3377 //*----------------------------------------------------------------------------
3378 static inline void AT91F_TC0_CfgPIO (void)
3379 {
3380         // Configure PIO controllers to periph mode
3381         AT91F_PIO_CfgPeriph(
3382                 AT91C_BASE_PIOA, // PIO controller base address
3383                 0, // Peripheral A
3384                 ((unsigned int) AT91C_PA0_TIOA0   ) |
3385                 ((unsigned int) AT91C_PA4_TCLK0   ) |
3386                 ((unsigned int) AT91C_PA1_TIOB0   )); // Peripheral B
3387 }
3388
3389 //*----------------------------------------------------------------------------
3390 //* \fn    AT91F_TC1_CfgPMC
3391 //* \brief Enable Peripheral clock in PMC for  TC1
3392 //*----------------------------------------------------------------------------
3393 static inline void AT91F_TC1_CfgPMC (void)
3394 {
3395         AT91F_PMC_EnablePeriphClock(
3396                 AT91C_BASE_PMC, // PIO controller base address
3397                 ((unsigned int) 1 << AT91C_ID_TC1));
3398 }
3399
3400 //*----------------------------------------------------------------------------
3401 //* \fn    AT91F_TC1_CfgPIO
3402 //* \brief Configure PIO controllers to drive TC1 signals
3403 //*----------------------------------------------------------------------------
3404 static inline void AT91F_TC1_CfgPIO (void)
3405 {
3406         // Configure PIO controllers to periph mode
3407         AT91F_PIO_CfgPeriph(
3408                 AT91C_BASE_PIOA, // PIO controller base address
3409                 0, // Peripheral A
3410                 ((unsigned int) AT91C_PA15_TIOA1   ) |
3411                 ((unsigned int) AT91C_PA28_TCLK1   ) |
3412                 ((unsigned int) AT91C_PA16_TIOB1   )); // Peripheral B
3413 }
3414
3415 //*----------------------------------------------------------------------------
3416 //* \fn    AT91F_TC2_CfgPMC
3417 //* \brief Enable Peripheral clock in PMC for  TC2
3418 //*----------------------------------------------------------------------------
3419 static inline void AT91F_TC2_CfgPMC (void)
3420 {
3421         AT91F_PMC_EnablePeriphClock(
3422                 AT91C_BASE_PMC, // PIO controller base address
3423                 ((unsigned int) 1 << AT91C_ID_TC2));
3424 }
3425
3426 //*----------------------------------------------------------------------------
3427 //* \fn    AT91F_TC2_CfgPIO
3428 //* \brief Configure PIO controllers to drive TC2 signals
3429 //*----------------------------------------------------------------------------
3430 static inline void AT91F_TC2_CfgPIO (void)
3431 {
3432         // Configure PIO controllers to periph mode
3433         AT91F_PIO_CfgPeriph(
3434                 AT91C_BASE_PIOA, // PIO controller base address
3435                 0, // Peripheral A
3436                 ((unsigned int) AT91C_PA27_TIOB2   ) |
3437                 ((unsigned int) AT91C_PA26_TIOA2   ) |
3438                 ((unsigned int) AT91C_PA29_TCLK2   )); // Peripheral B
3439 }
3440
3441 //*----------------------------------------------------------------------------
3442 //* \fn    AT91F_MC_CfgPMC
3443 //* \brief Enable Peripheral clock in PMC for  MC
3444 //*----------------------------------------------------------------------------
3445 static inline void AT91F_MC_CfgPMC (void)
3446 {
3447         AT91F_PMC_EnablePeriphClock(
3448                 AT91C_BASE_PMC, // PIO controller base address
3449                 ((unsigned int) 1 << AT91C_ID_SYS));
3450 }
3451
3452 //*----------------------------------------------------------------------------
3453 //* \fn    AT91F_PIOA_CfgPMC
3454 //* \brief Enable Peripheral clock in PMC for  PIOA
3455 //*----------------------------------------------------------------------------
3456 static inline void AT91F_PIOA_CfgPMC (void)
3457 {
3458         AT91F_PMC_EnablePeriphClock(
3459                 AT91C_BASE_PMC, // PIO controller base address
3460                 ((unsigned int) 1 << AT91C_ID_PIOA));
3461 }
3462
3463 //*----------------------------------------------------------------------------
3464 //* \fn    AT91F_PWMC_CfgPMC
3465 //* \brief Enable Peripheral clock in PMC for  PWMC
3466 //*----------------------------------------------------------------------------
3467 static inline void AT91F_PWMC_CfgPMC (void)
3468 {
3469         AT91F_PMC_EnablePeriphClock(
3470                 AT91C_BASE_PMC, // PIO controller base address
3471                 ((unsigned int) 1 << AT91C_ID_PWMC));
3472 }
3473
3474 #define __ramfunc __attribute__ ((long_call, section (".fastrun")))
3475
3476 #endif // lib_AT91SAM7S64_H