firmware/lib/lib_AT91SAM7.c

   1 //* ----------------------------------------------------------------------------
   2 //*         ATMEL Microcontroller Software Support  -  ROUSSET  -
   3 //* ----------------------------------------------------------------------------
   4 //* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
   5 //* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
   6 //* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
   7 //* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
   8 //* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
   9 //* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
  10 //* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  11 //* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  12 //* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
  13 //* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  14 //* ----------------------------------------------------------------------------
  15 //* File Name           : lib_AT91SAM7S64.h
  16 //* Object              : AT91SAM7S64 inlined functions
  17 //* Generated           : AT91 SW Application Group  08/30/2005 (15:52:59)
  18 //*
  19
  20 #include <sys/types.h>
  21 #include <include/AT91SAM7.h>
  22 #include <include/lib_AT91SAM7.h>
  23
  24 //*----------------------------------------------------------------------------
  25 //* \fn    AT91F_AIC_ConfigureIt
  26 //* \brief Interrupt Handler Initialization
  27 //*----------------------------------------------------------------------------
  28 unsigned int AT91F_AIC_ConfigureIt (
  29         AT91PS_AIC pAic,  // \arg pointer to the AIC registers
  30         unsigned int irq_id,     // \arg interrupt number to initialize
  31         unsigned int priority,   // \arg priority to give to the interrupt
  32         unsigned int src_type,   // \arg activation and sense of activation
  33         void (*newHandler) () ) // \arg address of the interrupt handler
  34 {
  35         unsigned int oldHandler;
  36     unsigned int mask ;
  37
  38     oldHandler = pAic->AIC_SVR[irq_id];
  39
  40     mask = 0x1 << irq_id ;
  41     //* Disable the interrupt on the interrupt controller
  42     pAic->AIC_IDCR = mask ;
  43     //* Save the interrupt handler routine pointer and the interrupt priority
  44     pAic->AIC_SVR[irq_id] = (unsigned int) newHandler ;
  45     //* Store the Source Mode Register
  46     pAic->AIC_SMR[irq_id] = src_type | priority  ;
  47     //* Clear the interrupt on the interrupt controller
  48     pAic->AIC_ICCR = mask ;
  49
  50         return oldHandler;
  51 }
  52
  53 //*----------------------------------------------------------------------------
  54 //* \fn    AT91F_AIC_SetExceptionVector
  55 //* \brief Configure vector handler
  56 //*----------------------------------------------------------------------------
  57 unsigned int  AT91F_AIC_SetExceptionVector (
  58         unsigned int *pVector, // \arg pointer to the AIC registers
  59         void (*Handler) () )   // \arg Interrupt Handler
  60 {
  61         unsigned int oldVector = *pVector;
  62
  63         if ((unsigned int) Handler == (unsigned int) AT91C_AIC_BRANCH_OPCODE)
  64                 *pVector = (unsigned int) AT91C_AIC_BRANCH_OPCODE;
  65         else
  66                 *pVector = (((((unsigned int) Handler) - ((unsigned int) pVector) - 0x8) >> 2) & 0x00FFFFFF) | 0xEA000000;
  67
  68         return oldVector;
  69 }
  70
  71 //*----------------------------------------------------------------------------
  72 //* \fn    AT91F_AIC_Open
  73 //* \brief Set exception vectors and AIC registers to default values
  74 //*----------------------------------------------------------------------------
  75 void AT91F_AIC_Open(
  76         AT91PS_AIC pAic,        // \arg pointer to the AIC registers
  77         void (*IrqHandler) (),  // \arg Default IRQ vector exception
  78         void (*FiqHandler) (),  // \arg Default FIQ vector exception
  79         void (*DefaultHandler)  (), // \arg Default Handler set in ISR
  80         void (*SpuriousHandler) (), // \arg Default Spurious Handler
  81         unsigned int protectMode)   // \arg Debug Control Register
  82 {
  83         int i;
  84
  85         // Disable all interrupts and set IVR to the default handler
  86         for (i = 0; i < 32; ++i) {
  87                 AT91F_AIC_DisableIt(pAic, i);
  88                 AT91F_AIC_ConfigureIt(pAic, i, AT91C_AIC_PRIOR_LOWEST, AT91C_AIC_SRCTYPE_HIGH_LEVEL, DefaultHandler);
  89         }
  90
  91         // Set the IRQ exception vector
  92         AT91F_AIC_SetExceptionVector((unsigned int *) 0x18, IrqHandler);
  93         // Set the Fast Interrupt exception vector
  94         AT91F_AIC_SetExceptionVector((unsigned int *) 0x1C, FiqHandler);
  95
  96         pAic->AIC_SPU = (unsigned int) SpuriousHandler;
  97         pAic->AIC_DCR = protectMode;
  98 }
  99
 100 //*----------------------------------------------------------------------------
 101 //* \fn    AT91F_PDC_Open
 102 //* \brief Open PDC: disable TX and RX reset transfer descriptors, re-enable RX and TX
 103 //*----------------------------------------------------------------------------
 104 void AT91F_PDC_Open(AT91PS_PDC pPDC)       // \arg pointer to a PDC controller
 105 {
 106     //* Disable the RX and TX PDC transfer requests
 107         AT91F_PDC_DisableRx(pPDC);
 108         AT91F_PDC_DisableTx(pPDC);
 109
 110         //* Reset all Counter register Next buffer first
 111         AT91F_PDC_SetNextTx(pPDC, NULL, 0);
 112         AT91F_PDC_SetNextRx(pPDC, NULL, 0);
 113         AT91F_PDC_SetTx(pPDC, NULL, 0);
 114         AT91F_PDC_SetRx(pPDC, NULL, 0);
 115
 116     //* Enable the RX and TX PDC transfer requests
 117         AT91F_PDC_EnableRx(pPDC);
 118         AT91F_PDC_EnableTx(pPDC);
 119 }
 120
 121 //*----------------------------------------------------------------------------
 122 //* \fn    AT91F_PDC_Close
 123 //* \brief Close PDC: disable TX and RX reset transfer descriptors
 124 //*----------------------------------------------------------------------------
 125 void AT91F_PDC_Close(AT91PS_PDC pPDC)       // \arg pointer to a PDC controller
 126 {
 127     //* Disable the RX and TX PDC transfer requests
 128         AT91F_PDC_DisableRx(pPDC);
 129         AT91F_PDC_DisableTx(pPDC);
 130
 131         //* Reset all Counter register Next buffer first
 132         AT91F_PDC_SetNextTx(pPDC, NULL, 0);
 133         AT91F_PDC_SetNextRx(pPDC, NULL, 0);
 134         AT91F_PDC_SetTx(pPDC, NULL, 0);
 135         AT91F_PDC_SetRx(pPDC, NULL, 0);
 136
 137 }
 138
 139 //*----------------------------------------------------------------------------
 140 //* \fn    AT91F_PDC_SendFrame
 141 //* \brief Close PDC: disable TX and RX reset transfer descriptors
 142 //*----------------------------------------------------------------------------
 143 unsigned int AT91F_PDC_SendFrame(
 144         AT91PS_PDC pPDC,
 145         const unsigned char *pBuffer,
 146         unsigned int szBuffer,
 147         const unsigned char *pNextBuffer,
 148         unsigned int szNextBuffer )
 149 {
 150         if (AT91F_PDC_IsTxEmpty(pPDC)) {
 151                 //* Buffer and next buffer can be initialized
 152                 AT91F_PDC_SetTx(pPDC, pBuffer, szBuffer);
 153                 AT91F_PDC_SetNextTx(pPDC, pNextBuffer, szNextBuffer);
 154                 return 2;
 155         }
 156         else if (AT91F_PDC_IsNextTxEmpty(pPDC)) {
 157                 //* Only one buffer can be initialized
 158                 AT91F_PDC_SetNextTx(pPDC, pBuffer, szBuffer);
 159                 return 1;
 160         }
 161         else {
 162                 //* All buffer are in use...
 163                 return 0;
 164         }
 165 }
 166
 167 //*----------------------------------------------------------------------------
 168 //* \fn    AT91F_PDC_ReceiveFrame
 169 //* \brief Close PDC: disable TX and RX reset transfer descriptors
 170 //*----------------------------------------------------------------------------
 171 unsigned int AT91F_PDC_ReceiveFrame (
 172         AT91PS_PDC pPDC,
 173         unsigned char *pBuffer,
 174         unsigned int szBuffer,
 175         unsigned char *pNextBuffer,
 176         unsigned int szNextBuffer )
 177 {
 178         if (AT91F_PDC_IsRxEmpty(pPDC)) {
 179                 //* Buffer and next buffer can be initialized
 180                 AT91F_PDC_SetRx(pPDC, pBuffer, szBuffer);
 181                 AT91F_PDC_SetNextRx(pPDC, pNextBuffer, szNextBuffer);
 182                 return 2;
 183         }
 184         else if (AT91F_PDC_IsNextRxEmpty(pPDC)) {
 185                 //* Only one buffer can be initialized
 186                 AT91F_PDC_SetNextRx(pPDC, pBuffer, szBuffer);
 187                 return 1;
 188         }
 189         else {
 190                 //* All buffer are in use...
 191                 return 0;
 192         }
 193 }
 194
 195 //*------------------------------------------------------------------------------
 196 //* \fn    AT91F_PMC_GetMasterClock
 197 //* \brief Return master clock in Hz which correponds to processor clock for ARM7
 198 //*------------------------------------------------------------------------------
 199 unsigned int AT91F_PMC_GetMasterClock (
 200         AT91PS_PMC pPMC, // \arg pointer to PMC controller
 201         AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
 202         unsigned int slowClock)  // \arg slowClock in Hz
 203 {
 204         unsigned int reg = pPMC->PMC_MCKR;
 205         unsigned int prescaler = (1 << ((reg & AT91C_PMC_PRES) >> 2));
 206         unsigned int pllDivider, pllMultiplier;
 207
 208         switch (reg & AT91C_PMC_CSS) {
 209                 case AT91C_PMC_CSS_SLOW_CLK: // Slow clock selected
 210                         return slowClock / prescaler;
 211                 case AT91C_PMC_CSS_MAIN_CLK: // Main clock is selected
 212                         return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / prescaler;
 213                 case AT91C_PMC_CSS_PLL_CLK: // PLLB clock is selected
 214                         reg = pCKGR->CKGR_PLLR;
 215                         pllDivider    = (reg  & AT91C_CKGR_DIV);
 216                         pllMultiplier = ((reg  & AT91C_CKGR_MUL) >> 16) + 1;
 217                         return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / pllDivider * pllMultiplier / prescaler;
 218         }
 219         return 0;
 220 }
 221
 222 //*--------------------------------------------------------------------------------------
 223 //* \fn     AT91F_RTT_ReadValue()
 224 //* \brief  Read the RTT value
 225 //*--------------------------------------------------------------------------------------
 226 unsigned int AT91F_RTTReadValue(AT91PS_RTTC pRTTC)
 227 {
 228         register volatile unsigned int val1,val2;
 229         do
 230         {
 231                 val1 = pRTTC->RTTC_RTVR;
 232                 val2 = pRTTC->RTTC_RTVR;
 233         }
 234         while(val1 != val2);
 235         return(val1);
 236 }
 237
 238 //*----------------------------------------------------------------------------
 239 //* \fn    AT91F_SPI_Close
 240 //* \brief Close SPI: disable IT disable transfert, close PDC
 241 //*----------------------------------------------------------------------------
 242 void AT91F_SPI_Close(AT91PS_SPI pSPI)     // \arg pointer to a SPI controller
 243 {
 244     //* Reset all the Chip Select register
 245     pSPI->SPI_CSR[0] = 0 ;
 246     pSPI->SPI_CSR[1] = 0 ;
 247     pSPI->SPI_CSR[2] = 0 ;
 248     pSPI->SPI_CSR[3] = 0 ;
 249
 250     //* Reset the SPI mode
 251     pSPI->SPI_MR = 0  ;
 252
 253     //* Disable all interrupts
 254     pSPI->SPI_IDR = 0xFFFFFFFF ;
 255
 256     //* Abort the Peripheral Data Transfers
 257     AT91F_PDC_Close((AT91PS_PDC) &(pSPI->SPI_RPR));
 258
 259     //* Disable receiver and transmitter and stop any activity immediately
 260     pSPI->SPI_CR = AT91C_SPI_SPIDIS;
 261 }
 262
 263 //*----------------------------------------------------------------------------
 264 //* \fn    AT91F_ADC_CfgTimings
 265 //* \brief Configure the different necessary timings of the ADC controller
 266 //*----------------------------------------------------------------------------
 267 void AT91F_ADC_CfgTimings (
 268         AT91PS_ADC pADC, // pointer to a ADC controller
 269         unsigned int mck_clock, // in MHz
 270         unsigned int adc_clock, // in MHz
 271         unsigned int startup_time, // in us
 272         unsigned int sample_and_hold_time)      // in ns
 273 {
 274         unsigned int prescal,startup,shtim;
 275
 276         prescal = mck_clock/(2*adc_clock) - 1;
 277         startup = adc_clock*startup_time/8 - 1;
 278         shtim = adc_clock*sample_and_hold_time/1000 - 1;
 279
 280         //* Write to the MR register
 281         pADC->ADC_MR = ( (prescal<<8) & AT91C_ADC_PRESCAL) | ( (startup<<16) & AT91C_ADC_STARTUP) | ( (shtim<<24) & AT91C_ADC_SHTIM);
 282 }
 283
 284 //*----------------------------------------------------------------------------
 285 //* \fn    AT91F_SSC_SetBaudrate
 286 //* \brief Set the baudrate according to the CPU clock
 287 //*----------------------------------------------------------------------------
 288 void AT91F_SSC_SetBaudrate (
 289         AT91PS_SSC pSSC,        // \arg pointer to a SSC controller
 290         unsigned int mainClock, // \arg peripheral clock
 291         unsigned int speed)     // \arg SSC baudrate
 292 {
 293         unsigned int baud_value;
 294         //* Define the baud rate divisor register
 295         if (speed == 0)
 296            baud_value = 0;
 297         else
 298         {
 299            baud_value = (unsigned int) (mainClock * 10)/(2*speed);
 300            if ((baud_value % 10) >= 5)
 301                   baud_value = (baud_value / 10) + 1;
 302            else
 303                   baud_value /= 10;
 304         }
 305
 306         pSSC->SSC_CMR = baud_value;
 307 }
 308
 309 //*----------------------------------------------------------------------------
 310 //* \fn    AT91F_SSC_Configure
 311 //* \brief Configure SSC
 312 //*----------------------------------------------------------------------------
 313 void AT91F_SSC_Configure (
 314              AT91PS_SSC pSSC,          // \arg pointer to a SSC controller
 315              unsigned int syst_clock,  // \arg System Clock Frequency
 316              unsigned int baud_rate,   // \arg Expected Baud Rate Frequency
 317              unsigned int clock_rx,    // \arg Receiver Clock Parameters
 318              unsigned int mode_rx,     // \arg mode Register to be programmed
 319              unsigned int clock_tx,    // \arg Transmitter Clock Parameters
 320              unsigned int mode_tx)     // \arg mode Register to be programmed
 321 {
 322     //* Disable interrupts
 323         pSSC->SSC_IDR = (unsigned int) -1;
 324
 325     //* Reset receiver and transmitter
 326         pSSC->SSC_CR = AT91C_SSC_SWRST | AT91C_SSC_RXDIS | AT91C_SSC_TXDIS ;
 327
 328     //* Define the Clock Mode Register
 329         AT91F_SSC_SetBaudrate(pSSC, syst_clock, baud_rate);
 330
 331      //* Write the Receive Clock Mode Register
 332         pSSC->SSC_RCMR =  clock_rx;
 333
 334      //* Write the Transmit Clock Mode Register
 335         pSSC->SSC_TCMR =  clock_tx;
 336
 337      //* Write the Receive Frame Mode Register
 338         pSSC->SSC_RFMR =  mode_rx;
 339
 340      //* Write the Transmit Frame Mode Register
 341         pSSC->SSC_TFMR =  mode_tx;
 342
 343     //* Clear Transmit and Receive Counters
 344         AT91F_PDC_Open((AT91PS_PDC) &(pSSC->SSC_RPR));
 345
 346
 347 }
 348
 349 //*----------------------------------------------------------------------------
 350 //* \fn    AT91F_US_Configure
 351 //* \brief Configure USART
 352 //*----------------------------------------------------------------------------
 353 void AT91F_US_Configure (
 354         AT91PS_USART pUSART,     // \arg pointer to a USART controller
 355         unsigned int mainClock,  // \arg peripheral clock
 356         unsigned int mode ,      // \arg mode Register to be programmed
 357         unsigned int baudRate ,  // \arg baudrate to be programmed
 358         unsigned int timeguard ) // \arg timeguard to be programmed
 359 {
 360     //* Disable interrupts
 361     pUSART->US_IDR = (unsigned int) -1;
 362
 363     //* Reset receiver and transmitter
 364     pUSART->US_CR = AT91C_US_RSTRX | AT91C_US_RSTTX | AT91C_US_RXDIS | AT91C_US_TXDIS ;
 365
 366         //* Define the baud rate divisor register
 367         AT91F_US_SetBaudrate(pUSART, mainClock, baudRate);
 368
 369         //* Write the Timeguard Register
 370         AT91F_US_SetTimeguard(pUSART, timeguard);
 371
 372     //* Clear Transmit and Receive Counters
 373     AT91F_PDC_Open((AT91PS_PDC) &(pUSART->US_RPR));
 374
 375     //* Define the USART mode
 376     pUSART->US_MR = mode  ;
 377
 378 }
 379
 380 //*----------------------------------------------------------------------------
 381 //* \fn    AT91F_US_Close
 382 //* \brief Close USART: disable IT disable receiver and transmitter, close PDC
 383 //*----------------------------------------------------------------------------
 384 void AT91F_US_Close(AT91PS_USART pUSART)     // \arg pointer to a USART controller
 385 {
 386     //* Reset the baud rate divisor register
 387     pUSART->US_BRGR = 0 ;
 388
 389     //* Reset the USART mode
 390     pUSART->US_MR = 0  ;
 391
 392     //* Reset the Timeguard Register
 393     pUSART->US_TTGR = 0;
 394
 395     //* Disable all interrupts
 396     pUSART->US_IDR = 0xFFFFFFFF ;
 397
 398     //* Abort the Peripheral Data Transfers
 399     AT91F_PDC_Close((AT91PS_PDC) &(pUSART->US_RPR));
 400
 401     //* Disable receiver and transmitter and stop any activity immediately
 402     pUSART->US_CR = AT91C_US_TXDIS | AT91C_US_RXDIS | AT91C_US_RSTTX | AT91C_US_RSTRX ;
 403 }
 404
 405