firmware/src/picc/.svn/text-base/tc_cdiv_sync.c.svn-base

   1 /* Synchronize TC_CDIV divided sample clock with the SOF of the packet */
   2
   3 #include <lib_AT91SAM7.h>
   4 #include <AT91SAM7.h>
   5 #include <os/dbgu.h>
   6 #include "../openpcd.h"
   7
   8 //#define USE_IRQ
   9
  10 static u_int8_t enabled;
  11
  12 static void pio_data_change(u_int32_t pio)
  13 {
  14         DEBUGP("PIO_FRAME_IRQ: ");
  15         /* we get one interrupt for each change. If now, after the
  16          * change the level is high, then it must have been a rising
  17          * edge */
  18         if (*AT91C_PIOA_PDSR & OPENPICC_PIO_FRAME) {
  19                 *AT91C_TC0_CCR = AT91C_TC_SWTRG;
  20                 DEBUGPCR("CDIV_SYNC_FLIP SWTRG CV=0x%08x",
  21                           *AT91C_TC0_CV);
  22         } else
  23                 DEBUGPCR("");
  24 }
  25
  26 #if 0
  27 static void __ramfunc cdsync_cb(void)
  28 {
  29         DEBUGP("PIO_IRQ: ");
  30         if (*AT91C_PIOA_ISR & OPENPICC_PIO_FRAME) {
  31                 DEBUGP("PIO_FRAME_IRQ: ");
  32                 /* we get one interrupt for each change. If now, after the
  33                  * change the level is high, then it must have been a rising
  34                  * edge */
  35                 if (*AT91C_PIOA_PDSR & OPENPICC_PIO_FRAME) {
  36                         *AT91C_TC0_CCR = AT91C_TC_SWTRG;
  37                         DEBUGPCR("CDIV_SYNC_FLIP SWTRG CV=0x%08x",
  38                                   *AT91C_TC0_CV);
  39                 } else
  40                         DEBUGPCR("");
  41         } else
  42                 DEBUGPCR("");
  43 }
  44 #endif
  45
  46 void tc_cdiv_sync_reset(void)
  47 {
  48         if (enabled) {
  49                 u_int32_t tmp = *AT91C_PIOA_ISR;
  50                 volatile int i;
  51                 DEBUGPCRF("CDIV_SYNC_FLOP");
  52
  53                 /* reset the hardware flipflop */
  54                 AT91F_PIO_ClearOutput(AT91C_BASE_PIOA,
  55                                       OPENPICC_PIO_SSC_DATA_CONTROL);
  56                 for (i = 0; i < 0xff; i++) ;
  57                 AT91F_PIO_SetOutput(AT91C_BASE_PIOA,
  58                                     OPENPICC_PIO_SSC_DATA_CONTROL);
  59         }
  60 }
  61
  62 void tc_cdiv_sync_disable(void)
  63 {
  64         enabled = 0;
  65         *AT91C_PIOA_IDR = OPENPICC_PIO_FRAME;
  66 }
  67
  68 void tc_cdiv_sync_enable(void)
  69 {
  70         enabled = 1;
  71
  72         DEBUGPCRF("CDIV_SYNC_ENABLE ");
  73         tc_cdiv_sync_reset();
  74         *AT91C_PIOA_IER = OPENPICC_PIO_FRAME;
  75 }
  76
  77 extern void (*fiq_handler)(void);
  78 void tc_cdiv_sync_init(void)
  79 {
  80         DEBUGPCRF("initializing");
  81
  82         enabled = 0;
  83
  84         AT91F_PIOA_CfgPMC();
  85
  86 #ifdef USE_IRQ
  87         /* Configure IRQ */
  88         AT91F_AIC_ConfigureIt(AT91C_BASE_AIC, AT91C_ID_PIOA,
  89                               AT91C_AIC_PRIOR_HIGHEST,
  90                               AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL, &cdsync_cb);
  91 #else
  92         /* Configure FIQ */
  93         AT91F_AIC_ConfigureIt(AT91C_BASE_AIC, AT91C_ID_FIQ,
  94                               //0, AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL, &cdsync_cb);
  95                               0, AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL, &fiq_handler);
  96         /* enable fast forcing for PIOA interrupt */
  97         *AT91C_AIC_FFER = (1 << AT91C_ID_PIOA);
  98
  99         /* register pio irq handler */
 100         pio_irq_register(OPENPICC_PIO_FRAME, &pio_data_change);
 101 #endif
 102         AT91F_AIC_EnableIt(AT91C_BASE_AIC, AT91C_ID_PIOA);
 103
 104         tc_cdiv_sync_disable();
 105 }