firmware/src/picc/tc_fdt.c

   1 /* OpenPICC TC (Timer / Clock) support code
   2  * (C) 2006 by Harald Welte <hwelte@hmw-consulting.de>
   3  *
   4  *  This program is free software; you can redistribute it and/or modify
   5  *  it under the terms of the GNU General Public License as published by
   6  *  the Free Software Foundation; either version 2 of the License, or
   7  *  (at your option) any later version.
   8  *
   9  *  This program is distributed in the hope that it will be useful,
  10  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  *  GNU General Public License for more details.
  13  *
  14  *  You should have received a copy of the GNU General Public License
  15  *  along with this program; if not, write to the Free Software
  16  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  17  *
  18  */
  19
  20
  21 /* PICC Simulator Side:
  22  * In order to support responding to synchronous frames (REQA/WUPA/ANTICOL),
  23  * we need a second Timer/Counter (TC2).  This unit is reset by an external
  24  * event (rising edge of modulation pause PCD->PICC, falling edge of
  25  * demodulated data) connected to TIOB2, and counts up to a configurable
  26  * number of carrier clock cycles (RA). Once the RA value is reached, TIOA2
  27  * will see a rising edge.  This rising edge will be interconnected to TF (Tx
  28  * Frame) of the SSC to start transmitting our synchronous response.
  29  *
  30  */
  31
  32 #include <lib_AT91SAM7.h>
  33 #include <AT91SAM7.h>
  34 #include <os/dbgu.h>
  35
  36 #include "../openpcd.h"
  37 #include <os/tc_cdiv.h>
  38 #include <picc/tc_fdt.h>
  39
  40 static AT91PS_TC tcfdt = AT91C_BASE_TC2;
  41
  42 void tc_fdt_set(u_int16_t count)
  43 {
  44         tcfdt->TC_RA = count;
  45 }
  46
  47
  48 /* 'count' number of carrier cycles after the last modulation pause,
  49  * we deem the frame to have ended */
  50 void tc_frame_end_set(u_int16_t count)
  51 {
  52         tcfdt->TC_RB = count;
  53 }
  54
  55 static void tc_fdt_irq(void)
  56 {
  57         u_int32_t sr = tcfdt->TC_SR;
  58         DEBUGP("tc_fdt_irq: TC2_SR=0x%08x TC2_CV=0x%08x ",
  59                 sr, tcfdt->TC_CV);
  60
  61         if (sr & AT91C_TC_ETRGS) {
  62                 DEBUGP("Ext_trigger ");
  63         }
  64         if (sr & AT91C_TC_CPAS) {
  65                 DEBUGP("FDT_expired ");
  66                 /* FIXME: if we are in anticol / sync mode,
  67                  * we could do software triggering of SSC TX,
  68                  * but IIRC the hardware does this by TF */
  69         }
  70         if (sr & AT91C_TC_CPBS) {
  71                 DEBUGP("Frame_end ");
  72                 /* FIXME: stop ssc (in continuous mode),
  73                  * take care of preparing synchronous response if
  74                  * we operate in anticol mode.*/
  75         }
  76         if (sr & AT91C_TC_CPCS) {
  77                 DEBUGP("Compare_C ");
  78         }
  79         DEBUGPCR("");
  80 }
  81
  82 void tc_fdt_print(void)
  83 {
  84         DEBUGP("TC2_CV=0x%08x ", tcfdt->TC_CV);
  85         DEBUGP("TC2_CMR=0x%08x ", tcfdt->TC_CMR);
  86         DEBUGP("TC2_SR=0x%08x ", tcfdt->TC_SR);
  87         DEBUGP("TC2_RA=0x%04x, TC2_RB=0x%04x, TC2_RC=0x%04x",
  88                 tcfdt->TC_RA, tcfdt->TC_RB, tcfdt->TC_RC);
  89 }
  90
  91 void tc_fdt_init(void)
  92 {
  93         AT91F_PIO_CfgPeriph(AT91C_BASE_PIOA, AT91C_PA15_TF,
  94                             AT91C_PA26_TIOA2 | AT91C_PA27_TIOB2);
  95         AT91F_PMC_EnablePeriphClock(AT91C_BASE_PMC,
  96                                     ((unsigned int) 1 << AT91C_ID_TC2));
  97         /* Enable Clock for TC2 */
  98         tcfdt->TC_CCR = AT91C_TC_CLKEN;
  99
 100         tcfdt->TC_RC = 0xffff;
 101         tc_frame_end_set(128*2);
 102
 103         /* Clock XC1, Wave Mode, No automatic reset on RC comp
 104          * TIOA2 in RA comp = set, TIOA2 on RC comp = clear,
 105          * TIOA2 on EEVT = clear
 106          * TIOB2 as input, EEVT = TIOB2, Reset/Trigger on EEVT */
 107         tcfdt->TC_CMR = AT91C_TC_CLKS_XC1 | AT91C_TC_WAVE |
 108                       AT91C_TC_WAVESEL_UP |
 109                       AT91C_TC_ACPA_SET | AT91C_TC_ACPC_CLEAR |
 110                       AT91C_TC_AEEVT_CLEAR |
 111                       AT91C_TC_BEEVT_NONE | AT91C_TC_BCPB_NONE |
 112                       AT91C_TC_EEVT_TIOB | AT91C_TC_ETRGEDG_FALLING |
 113                       AT91C_TC_ENETRG | AT91C_TC_CPCSTOP ;
 114
 115         /* Reset to start timers */
 116         tcb->TCB_BCR = 1;
 117
 118         AT91F_AIC_ConfigureIt(AT91C_BASE_AIC, AT91C_ID_TC2,
 119                               OPENPCD_IRQ_PRIO_TC_FDT,
 120                               AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL, &tc_fdt_irq);
 121         AT91F_AIC_EnableIt(AT91C_BASE_AIC, AT91C_ID_TC2);
 122
 123         tcfdt->TC_IER = AT91C_TC_CPAS | AT91C_TC_CPBS | AT91C_TC_CPCS |
 124                         AT91C_TC_ETRGS;
 125 }
 126