firmware/export/pnx0101.h

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2005 by Tomasz Malesinski
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License
  14  * as published by the Free Software Foundation; either version 2
  15  * of the License, or (at your option) any later version.
  16  *
  17  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  18  * KIND, either express or implied.
  19  *
  20  ****************************************************************************/
  21
  22 #ifndef __PNX0101_H__
  23 #define __PNX0101_H__
  24
  25 #define GPIO0_READ (*(volatile unsigned long *)0x80003000)
  26 #define GPIO0_SET  (*(volatile unsigned long *)0x80003014)
  27 #define GPIO0_CLR  (*(volatile unsigned long *)0x80003018)
  28 #define GPIO1_READ (*(volatile unsigned long *)0x80003040)
  29 #define GPIO1_SET  (*(volatile unsigned long *)0x80003054)
  30 #define GPIO1_CLR  (*(volatile unsigned long *)0x80003058)
  31 #define GPIO2_READ (*(volatile unsigned long *)0x80003080)
  32 #define GPIO2_SET  (*(volatile unsigned long *)0x80003094)
  33 #define GPIO2_CLR  (*(volatile unsigned long *)0x80003098)
  34 #define GPIO3_READ (*(volatile unsigned long *)0x800030c0)
  35 #define GPIO3_SET  (*(volatile unsigned long *)0x800030d4)
  36 #define GPIO3_CLR  (*(volatile unsigned long *)0x800030d8)
  37 #define GPIO4_READ (*(volatile unsigned long *)0x80003100)
  38 #define GPIO4_SET  (*(volatile unsigned long *)0x80003114)
  39 #define GPIO4_CLR  (*(volatile unsigned long *)0x80003118)
  40 #define GPIO5_READ (*(volatile unsigned long *)0x80003140)
  41 #define GPIO5_SET  (*(volatile unsigned long *)0x80003154)
  42 #define GPIO5_CLR  (*(volatile unsigned long *)0x80003158)
  43 #define GPIO6_READ (*(volatile unsigned long *)0x80003180)
  44 #define GPIO6_SET  (*(volatile unsigned long *)0x80003194)
  45 #define GPIO6_CLR  (*(volatile unsigned long *)0x80003198)
  46 #define GPIO7_READ (*(volatile unsigned long *)0x800031c0)
  47 #define GPIO7_SET  (*(volatile unsigned long *)0x800031d4)
  48 #define GPIO7_CLR  (*(volatile unsigned long *)0x800031d8)
  49
  50 #define LCDREG04 (*(volatile unsigned long *)0x80104004)
  51 #define LCDSTAT  (*(volatile unsigned long *)0x80104008)
  52 #define LCDREG10 (*(volatile unsigned long *)0x80104010)
  53 #define LCDCMD   (*(volatile unsigned long *)0x80104020)
  54 #define LCDDATA  (*(volatile unsigned long *)0x80104030)
  55
  56 #define TIMERR00 (*(volatile unsigned long *)0x80020000)
  57 #define TIMERR08 (*(volatile unsigned long *)0x80020008)
  58 #define TIMERR0C (*(volatile unsigned long *)0x8002000c)
  59
  60 #define ADCCH0   (*(volatile unsigned long *)0x80002400)
  61 #define ADCCH1   (*(volatile unsigned long *)0x80002404)
  62 #define ADCCH2   (*(volatile unsigned long *)0x80002408)
  63 #define ADCCH3   (*(volatile unsigned long *)0x8000240c)
  64 #define ADCCH4   (*(volatile unsigned long *)0x80002410)
  65 #define ADCST    (*(volatile unsigned long *)0x80002420)
  66 #define ADCR24   (*(volatile unsigned long *)0x80002424)
  67 #define ADCR28   (*(volatile unsigned long *)0x80002428)
  68
  69 #define DMAINTSTAT   (*(volatile unsigned long *)0x80104c04)
  70 #define DMAINTEN     (*(volatile unsigned long *)0x80104c08)
  71
  72 #define DMASRC(n)    (*(volatile unsigned long *)(0x80104800 + (n) * 0x20))
  73 #define DMADEST(n)   (*(volatile unsigned long *)(0x80104804 + (n) * 0x20))
  74 #define DMALEN(n)    (*(volatile unsigned long *)(0x80104808 + (n) * 0x20))
  75 #define DMAR0C(n)    (*(volatile unsigned long *)(0x8010480c + (n) * 0x20))
  76 #define DMAR10(n)    (*(volatile unsigned long *)(0x80104810 + (n) * 0x20))
  77 #define DMAR1C(n)    (*(volatile unsigned long *)(0x8010481c + (n) * 0x20))
  78
  79 #define MMUBLOCK(n)  (*(volatile unsigned long *)(0x80105018 + (n) * 4))
  80
  81 #define CODECVOL     (*(volatile unsigned long *)0x80200398)
  82
  83 #ifndef ASM
  84
  85 /* Clock generation unit */
  86
  87 struct pnx0101_cgu {
  88     unsigned long base_scr[12];
  89     unsigned long base_fs1[12];
  90     unsigned long base_fs2[12];
  91     unsigned long base_ssr[12];
  92     unsigned long clk_pcr[73];
  93     unsigned long clk_psr[73];
  94     unsigned long clk_esr[67];
  95     unsigned long base_bcr[3];
  96     unsigned long base_fdc[18];
  97 };
  98
  99 #define CGU (*(volatile struct pnx0101_cgu *)0x80004000)
 100
 101 #define PNX0101_SEL_STAGE_SYS  0
 102 #define PNX0101_SEL_STAGE_APB0 1
 103 #define PNX0101_SEL_STAGE_APB1 2
 104 #define PNX0101_SEL_STAGE_APB3 3
 105 #define PNX0101_SEL_STAGE_DAIO 9
 106
 107 #define PNX0101_HIPREC_FDC 16
 108
 109 #define PNX0101_FIRST_DIV_SYS  0
 110 #define PNX0101_N_DIV_SYS      7
 111 #define PNX0101_FIRST_DIV_APB0 7
 112 #define PNX0101_N_DIV_APB0     2
 113 #define PNX0101_FIRST_DIV_APB1 9
 114 #define PNX0101_N_DIV_APB1     1
 115 #define PNX0101_FIRST_DIV_APB3 10
 116 #define PNX0101_N_DIV_APB3     1
 117 #define PNX0101_FIRST_DIV_DAIO 12
 118 #define PNX0101_N_DIV_DAIO     6
 119
 120 #define PNX0101_BCR_SYS  0
 121 #define PNX0101_BCR_APB0 1
 122 #define PNX0101_BCR_DAIO 2
 123
 124 #define PNX0101_FIRST_ESR_SYS  0
 125 #define PNX0101_N_ESR_SYS      28
 126 #define PNX0101_FIRST_ESR_APB0 28
 127 #define PNX0101_N_ESR_APB0     9
 128 #define PNX0101_FIRST_ESR_APB1 37
 129 #define PNX0101_N_ESR_APB1     4
 130 #define PNX0101_FIRST_ESR_APB3 41
 131 #define PNX0101_N_ESR_APB3     16
 132 #define PNX0101_FIRST_ESR_DAIO 58
 133 #define PNX0101_N_ESR_DAIO     9
 134
 135 #define PNX0101_ESR_APB1 0x25
 136 #define PNX0101_ESR_T0   0x26
 137 #define PNX0101_ESR_T1   0x27
 138 #define PNX0101_ESR_I2C  0x28
 139
 140 #define PNX0101_CLOCK_APB1 0x25
 141 #define PNX0101_CLOCK_T0   0x26
 142 #define PNX0101_CLOCK_T1   0x27
 143 #define PNX0101_CLOCK_I2C  0x28
 144
 145 #define PNX0101_MAIN_CLOCK_FAST     1
 146 #define PNX0101_MAIN_CLOCK_MAIN_PLL 9
 147
 148 struct pnx0101_pll {
 149     unsigned long hpfin;
 150     unsigned long hpmdec;
 151     unsigned long hpndec;
 152     unsigned long hppdec;
 153     unsigned long hpmode;
 154     unsigned long hpstat;
 155     unsigned long hpack;
 156     unsigned long hpreq;
 157     unsigned long hppad1;
 158     unsigned long hppad2;
 159     unsigned long hppad3;
 160     unsigned long hpselr;
 161     unsigned long hpseli;
 162     unsigned long hpselp;
 163     unsigned long lpfin;
 164     unsigned long lppdn;
 165     unsigned long lpmbyp;
 166     unsigned long lplock;
 167     unsigned long lpdbyp;
 168     unsigned long lpmsel;
 169     unsigned long lppsel;
 170 };
 171
 172 #define PLL (*(volatile struct pnx0101_pll *)0x80004cac)
 173
 174 struct pnx0101_emc {
 175     unsigned long control;
 176     unsigned long status;
 177 };
 178
 179 #define EMC (*(volatile struct pnx0101_emc *)0x80008000)
 180
 181 struct pnx0101_emcstatic {
 182     unsigned long config;
 183     unsigned long waitwen;
 184     unsigned long waitoen;
 185     unsigned long waitrd;
 186     unsigned long waitpage;
 187     unsigned long waitwr;
 188     unsigned long waitturn;
 189 };
 190
 191 #define EMCSTATIC0 (*(volatile struct pnx0101_emcstatic *)0x80008200)
 192 #define EMCSTATIC1 (*(volatile struct pnx0101_emcstatic *)0x80008220)
 193 #define EMCSTATIC2 (*(volatile struct pnx0101_emcstatic *)0x80008240)
 194
 195 /* Timers */
 196
 197 struct pnx0101_timer {
 198     unsigned long load;
 199     unsigned long value;
 200     unsigned long ctrl;
 201     unsigned long clr;
 202 };
 203
 204 #define TIMER0 (*(volatile struct pnx0101_timer *)0x80020000)
 205 #define TIMER1 (*(volatile struct pnx0101_timer *)0x80020400)
 206
 207 /* Interrupt controller */
 208
 209 #define IRQ_TIMER0 5
 210 #define IRQ_TIMER1 6
 211 #define IRQ_DMA    28
 212
 213 #define INTPRIOMASK ((volatile unsigned long *)0x80300000)
 214 #define INTVECTOR   ((volatile unsigned long *)0x80300100)
 215 #define INTPENDING  (*(volatile unsigned long *)0x80300200)
 216 #define INTFEATURES (*(volatile unsigned long *)0x80300300)
 217 #define INTREQ      ((volatile unsigned long *)0x80300400)
 218
 219 #define INTREQ_WEPRIO   0x10000000
 220 #define INTREQ_WETARGET 0x08000000
 221 #define INTREQ_WEENABLE 0x04000000
 222 #define INTREQ_WEACTVLO 0x02000000
 223 #define INTREQ_ENABLE   0x00010000
 224
 225 /* General purpose DMA */
 226
 227 struct pnx0101_dma_channel {
 228     unsigned long source;
 229     unsigned long dest;
 230     unsigned long length;
 231     unsigned long config;
 232     unsigned long enable;
 233     unsigned long pad1;
 234     unsigned long pad2;
 235     unsigned long count;
 236 };
 237
 238 #define DMACHANNEL ((volatile struct pnx0101_dma_channel *)0x80104800)
 239
 240 struct pnx0101_dma {
 241     unsigned long enable;
 242     unsigned long stat;
 243     unsigned long irqmask;
 244     unsigned long softint;
 245 };
 246
 247 #define DMA (*(volatile struct pnx0101_dma *)0x80104c00)
 248
 249 struct pnx0101_audio {
 250     unsigned long pad1;
 251     unsigned long siocr;
 252     unsigned long pad2;
 253     unsigned long pad3;
 254     unsigned long pad4;
 255     unsigned long pad5;
 256     unsigned long ddacctrl;
 257     unsigned long ddacstat;
 258     unsigned long ddacset;
 259 };
 260
 261 #define AUDIO (*(volatile struct pnx0101_audio *)0x80200380)
 262
 263 #endif /* ASM */
 264
 265 /* Timer frequency */
 266 #define TIMER_FREQ 3000000
 267
 268 #endif