1 /***************************************************************************
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
10 * Copyright (C) 2007-2008 Michael Sevakis (jhMikeS)
11 * Copyright (C) 2006-2007 Adam Gashlin (hcs)
12 * Copyright (C) 2004-2007 Shay Green (blargg)
13 * Copyright (C) 2002 Brad Martin
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version 2
18 * of the License, or (at your option) any later version.
20 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
21 * KIND, either express or implied.
23 ****************************************************************************/
25 /* lovingly ripped off from Game_Music_Emu 0.5.2. http://www.slack.net/~ant/ */
26 /* DSP Based on Brad Martin's OpenSPC DSP emulator */
27 /* tag reading from sexyspc by John Brawn (John_Brawn@yahoo.com) and others */
32 /* rather than comment out asserts, just define NDEBUG */
38 /** Basic configuration options **/
40 #define SPC_DUAL_CORE 1
42 #if !defined(SPC_DUAL_CORE) || NUM_CORES == 1
44 #define SPC_DUAL_CORE 0
47 /* TGB is the only target fast enough for gaussian and realtime BRR decode */
48 /* echo is almost fast enough but not quite */
49 #if defined(TOSHIBA_GIGABEAT_F) || defined(TOSHIBA_GIGABEAT_S) ||\
50 defined(SIMULATOR) || MEMORYSIZE <= 2
51 /* Don't cache BRR waves */
52 #define SPC_BRRCACHE 0
54 /* Allow gaussian interpolation */
55 #define SPC_NOINTERP 0
57 /* Allow echo processing */
59 #elif defined(CPU_COLDFIRE)
61 #define SPC_BRRCACHE 1
63 /* Disable gaussian interpolation */
64 #define SPC_NOINTERP 1
66 /* Allow echo processing */
68 #elif defined (CPU_PP) && SPC_DUAL_CORE
70 #define SPC_BRRCACHE 1
72 /* Disable gaussian interpolation */
73 #define SPC_NOINTERP 1
75 /* Allow echo processing */
79 #define SPC_BRRCACHE 1
81 /* Disable gaussian interpolation */
82 #define SPC_NOINTERP 1
84 /* Disable echo processing */
90 #if CONFIG_CPU != PP5002
105 #undef SHAREDBSS_ATTR
106 #define SHAREDBSS_ATTR __attribute__ ((section(".ibss")))
107 #undef SHAREDDATA_ATTR
108 #define SHAREDDATA_ATTR __attribute__((section(".idata")))
112 /* Samples per channel per iteration */
113 #if defined(CPU_PP) && NUM_CORES == 1
114 #define WAV_CHUNK_SIZE 2048
116 #define WAV_CHUNK_SIZE 1024
119 /**************** Little-endian handling ****************/
121 static inline unsigned get_le16( void const* p
)
123 return ((unsigned char const*) p
) [1] * 0x100u
+
124 ((unsigned char const*) p
) [0];
127 static inline int get_le16s( void const* p
)
129 return ((signed char const*) p
) [1] * 0x100 +
130 ((unsigned char const*) p
) [0];
133 static inline void set_le16( void* p
, unsigned n
)
135 ((unsigned char*) p
) [1] = (unsigned char) (n
>> 8);
136 ((unsigned char*) p
) [0] = (unsigned char) n
;
139 #define GET_LE16( addr ) get_le16( addr )
140 #define SET_LE16( addr, data ) set_le16( addr, data )
141 #define INT16A( addr ) (*(uint16_t*) (addr))
142 #define INT16SA( addr ) (*(int16_t*) (addr))
144 #ifdef ROCKBOX_LITTLE_ENDIAN
145 #define GET_LE16A( addr ) (*(uint16_t*) (addr))
146 #define GET_LE16SA( addr ) (*( int16_t*) (addr))
147 #define SET_LE16A( addr, data ) (void) (*(uint16_t*) (addr) = (data))
149 #define GET_LE16A( addr ) get_le16 ( addr )
150 #define GET_LE16SA( addr ) get_le16s( addr )
151 #define SET_LE16A( addr, data ) set_le16 ( addr, data )
155 #define THIS struct Spc_Emu* const this
157 /* The CPU portion (shock!) */
161 long pc
; /* more than 16 bits to allow overflow detection */
172 uint8_t padding1
[0x100];
175 uint8_t ram
[0x10000];
176 uint8_t padding2
[0x100];
181 extern struct cpu_ram_t ram
;
183 long CPU_run( THIS
, long start_time
) ICODE_ATTR
;
184 void CPU_Init( THIS
);
186 /* The DSP portion (awe!) */
187 enum { VOICE_COUNT
= 8 };
188 enum { REGISTER_COUNT
= 128 };
195 uint8_t adsr
[2]; /* envelope rates for attack, decay, and sustain */
196 uint8_t gain
; /* envelope gain (if not using ADSR) */
197 int8_t envx
; /* current envelope level */
198 int8_t outx
; /* current sample */
205 int8_t volume_0
; /* 0C Main Volume Left (-.7) */
206 int8_t echo_feedback
; /* 0D Echo Feedback (-.7) */
208 int8_t volume_1
; /* 1C Main Volume Right (-.7) */
210 int8_t echo_volume_0
; /* 2C Echo Volume Left (-.7) */
211 uint8_t pitch_mods
; /* 2D Pitch Modulation on/off for each voice */
213 int8_t echo_volume_1
; /* 3C Echo Volume Right (-.7) */
214 uint8_t noise_enables
; /* 3D Noise output on/off for each voice */
216 uint8_t key_ons
; /* 4C Key On for each voice */
217 uint8_t echo_ons
; /* 4D Echo on/off for each voice */
219 uint8_t key_offs
; /* 5C key off for each voice
220 (instantiates release mode) */
221 uint8_t wave_page
; /* 5D source directory (wave table offsets) */
223 uint8_t flags
; /* 6C flags and noise freq */
224 uint8_t echo_page
; /* 6D */
226 uint8_t wave_ended
; /* 7C */
227 uint8_t echo_delay
; /* 7D ms >> 4 */
232 { /* -1, 0, +1 allows more efficient if statements */
241 int16_t const* samples
;
242 unsigned end
; /* past-the-end position */
243 unsigned loop
; /* number of samples in loop */
247 enum { BRR_BLOCK_SIZE
= 16 };
248 enum { BRR_CACHE_SIZE
= 0x20000 + 32} ;
253 int16_t const* samples
;
257 int16_t samples
[3 + BRR_BLOCK_SIZE
+ 1];
258 int block_header
; /* header byte from current block */
262 long position
;/* position in samples buffer, with 12-bit fraction */
270 /* a little extra for samples that go past end */
271 extern int16_t BRRcache
[BRR_CACHE_SIZE
];
274 enum { FIR_BUF_HALF
= 8 };
276 #if defined(CPU_COLDFIRE)
277 /* global because of the large aligment requirement for hardware masking -
278 * L-R interleaved 16-bit samples for easy loading and mac.w use.
282 FIR_BUF_CNT
= FIR_BUF_HALF
,
283 FIR_BUF_SIZE
= FIR_BUF_CNT
* sizeof ( int32_t ),
284 FIR_BUF_ALIGN
= FIR_BUF_SIZE
* 2,
285 FIR_BUF_MASK
= ~((FIR_BUF_ALIGN
/ 2) | (sizeof ( int32_t ) - 1))
287 #elif defined (CPU_ARM)
290 FIR_BUF_CNT
= FIR_BUF_HALF
* 2 * 2,
291 FIR_BUF_SIZE
= FIR_BUF_CNT
* sizeof ( int32_t ),
292 FIR_BUF_ALIGN
= FIR_BUF_SIZE
,
293 FIR_BUF_MASK
= ~((FIR_BUF_ALIGN
/ 2) | (sizeof ( int32_t ) * 2 - 1))
301 struct raw_voice_t voice
[VOICE_COUNT
];
302 uint8_t reg
[REGISTER_COUNT
];
310 uint16_t noise
; /* also read as int16_t */
312 #if defined(CPU_COLDFIRE)
313 /* circularly hardware masked address */
315 /* wrapped address just behind current position -
316 allows mac.w to increment and mask fir_ptr */
317 int32_t *last_fir_ptr
;
318 /* copy of echo FIR constants as int16_t for use with mac.w */
319 int16_t fir_coeff
[VOICE_COUNT
];
320 #elif defined (CPU_ARM)
321 /* fir_buf [i + 8] == fir_buf [i], to avoid wrap checking in FIR code */
323 /* copy of echo FIR constants as int32_t, for faster access */
324 int32_t fir_coeff
[VOICE_COUNT
];
326 /* fir_buf [i + 8] == fir_buf [i], to avoid wrap checking in FIR code */
327 int fir_pos
; /* (0 to 7) */
328 int fir_buf
[FIR_BUF_HALF
* 2] [2];
329 /* copy of echo FIR constants as int, for faster access */
330 int fir_coeff
[VOICE_COUNT
];
333 struct voice_t voice_state
[VOICE_COUNT
];
337 struct cache_entry_t wave_entry
[256];
338 struct cache_entry_t wave_entry_old
[256];
348 void DSP_run_( struct Spc_Dsp
* this, long count
, int32_t* out_buf
) ICODE_ATTR
;
349 void DSP_reset( struct Spc_Dsp
* this );
351 static inline void DSP_run( struct Spc_Dsp
* this, long count
, int32_t* out
)
353 /* Should we just fill the buffer with silence? Flags won't be cleared */
354 /* during this run so it seems it should keep resetting every sample. */
355 if ( this->r
.g
.flags
& 0x80 )
358 DSP_run_( this, count
, out
);
361 /**************** SPC emulator ****************/
362 /* 1.024 MHz clock / 32000 samples per second */
363 enum { CLOCKS_PER_SAMPLE
= 32 };
365 enum { EXTRA_CLOCKS
= CLOCKS_PER_SAMPLE
/ 2 };
367 /* using this disables timer (since this will always be in the future) */
368 enum { TIMER_DISABLED_TIME
= 127 };
370 enum { ROM_SIZE
= 64 };
371 enum { ROM_ADDR
= 0xFFC0 };
373 enum { TIMER_COUNT
= 3 };
385 void Timer_run_( struct Timer
* t
, long time
) ICODE_ATTR
;
387 static inline void Timer_run( struct Timer
* t
, long time
)
389 if ( time
>= t
->next_tick
)
390 Timer_run_( t
, time
);
395 uint8_t cycle_table
[0x100];
403 struct Timer timer
[TIMER_COUNT
];
405 /* large objects at end */
407 uint8_t extra_ram
[ROM_SIZE
];
408 uint8_t boot_rom
[ROM_SIZE
];
411 enum { SPC_FILE_SIZE
= 0x10180 };
424 uint8_t ram
[0x10000];
426 uint8_t ipl_rom
[128];
429 void SPC_Init( THIS
);
431 int SPC_load_spc( THIS
, const void* data
, long size
);
433 /**************** DSP interaction ****************/
434 void DSP_write( struct Spc_Dsp
* this, int i
, int data
) ICODE_ATTR
;
436 static inline int DSP_read( struct Spc_Dsp
* this, int i
)
438 assert( (unsigned) i
< REGISTER_COUNT
);
439 return this->r
.reg
[i
];
442 void SPC_run_dsp_( THIS
, long time
) ICODE_ATTR
;
444 static inline void SPC_run_dsp( THIS
, long time
)
446 if ( time
>= this->next_dsp
)
447 SPC_run_dsp_( this, time
);
450 int SPC_read( THIS
, unsigned addr
, long const time
) ICODE_ATTR
;
451 void SPC_write( THIS
, unsigned addr
, int data
, long const time
) ICODE_ATTR
;
453 /**************** Sample generation ****************/
454 int SPC_play( THIS
, long count
, int32_t* out
) ICODE_ATTR
;
456 #endif /* _SPC_CODEC_H_ */